Stick Diagram

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STICK Diagrams
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Kavita Mehta
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Stick Diagrams
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N+ N+
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Stick Diagrams
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VDD
X
X
Stick
Diagram X
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Gnd Gnd
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Stick Diagrams
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VDD
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VDD
X
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X
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Gnd Gnd
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Stick Diagrams
•VLSI design aims to translate circuitwww.vlsi-expert.com

concepts onto silicon.
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•stick diagrams are a means of capturing topography and layer information

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using simple diagrams.

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•Stick diagrams convey layer information through colourwww.vlsi-expert.com
codes (or
monochrome encoding).
•Acts as an interface between symbolic circuit and the actual layout.
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Stick Diagrams
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 Does show all components/vias.

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 It shows relative placement of components. www.vlsi-expert.com
 Goes one step closer to the layout

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 Helps plan the layout and routing
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A stick
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Stick Diagrams
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 Does not show

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• Exact placement of components www.vlsi-expert.com
• Transistor sizes
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• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitic.
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•VLSI design aims to translate circuit concepts onto silicon.

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•Stick diagrams are a means of capturing topography and layer
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information using simple diagrams.

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•Stick diagrams convey layer information throughwww.vlsi-expert.com
color codes (or
monochrome encoding).
•Acts as an interface between symbolic circuit and the actual layout.
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•Does
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.com all components/vias.
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•Via is used to connect higher level metals from metal connection

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•It showswww.vlsi-expert.com
relative placement of components. www.vlsi-expert.com
•Goes one step closer to the layout
•Helps plan the layout and routing www.vlsi-expert.com
A stick diagram is a cartoon

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of a layout.
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λ and design rules
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•λwww. .com
is the size of a minimum feature.
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•Specifying λ particularizes the scalable rules.

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•Parasitic are generally not specified www.vlsi-expert.com
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Wires
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are multiples of 
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6 metal 3
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3 metal 2
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3 metal 1
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3 pdiff/ndiff
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2 poly
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Transistors
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2
poly
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3
diffusion
3
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substrate
1
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All measures are multiples of 

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Vias
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•Types of via: metal1/diff, metal1/poly, metal1/metal2.
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4 4
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1
2
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Stick Diagrams – Notations
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Metal 1
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poly
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pdiff
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in shades of
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Buried Contact
Contact Cut
Stick Diagrams – Some Rules
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Rule 1: www.vlsi-expert.com
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When two or more ‘sticks’ of the same type cross or touch each other that
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represents electrical contact.

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Stick Diagrams – Some Rules www.vlsi-expert.com
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When two or more ‘sticks’ of different type cross or touch each

other there is no electrical contact.
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(If electrical contact is needed we have to show the connection
explicitly)
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When a poly crosses diffusion it represents a transistor.

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Note: If a contact is shown then it is not a transistor.

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In CMOS a demarcation line is drawn to avoid touching of p-diff

with n-diff. All PMOS must lie on one side of the line and all
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NMOS will have to be on the other side.
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Examples of Stick Diagrams
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Vdd = 5V Vdd = 5V

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pMOS
Vin Vout Vin Vout
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VDD
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VDD
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X
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X
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X
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Gnd Gnd
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* Note the depletion mode device
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Vdd = 5V
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www.vlsi-expert.com Vout www.vlsi-expert.com

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Vin
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NOR gate and NAND using NMOS Transistors

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f= [(xy) +z]’ using NMOS Transistors

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Why we use design rules?
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•Interface between designer and process engineer

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•Historically, the process technology referred to the length of the silicon
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channel between the source and drain terminals in field effect transistors.
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• The sizes of other features are generally derived as a www.vlsi-expert.com
ratio of the channel
length, where some may be larger than the channel size and some smaller.
•For example, in a 90 nm process, thewww.vlsi-expert.com
length of the channel may be 90 nm,
but the width of the gate terminal may be only 50 nm.
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• Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in
silicon
• Interface between circuit designer and fabrication engineer
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• Compromise www.vlsi-expert.com
• designer - tighter, smaller www.vlsi-expert.com
• fabricator - controllable, reproducible

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•Design
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• Examples: www.vlsi-expert.com
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www.vlsi-expert.com• min. wire widths to avoid breaks
• min. spacing to avoid shorts www.vlsi-expert.com
• minimum overlaps to ensure complete overlaps

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• Measured in microns www.vlsi-expert.com
• Required for resolution/tolerances of masks
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•Fabrication processes defined by minimum channel
width
• Also minimum width of poly traceswww.vlsi-expert.com
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• Defines “how fast” a fabrication process is

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•Two major
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• “Micron” rules: stated at micron resolution.

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•
www.vlsi-expert.com rules: simplified micron rules www.vlsi-expert.com
with limited scaling attributes.
•Design rules represents a tolerance which insures www.vlsi-expert.com
very high probability of correct fabrication

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• scalable design rules: lambda parameter www.vlsi-expert.com
• absolute dimensions (micron rules)
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• All minimum sizes and spacing specified in microns.
• Rules don't have to be multiples of λ. www.vlsi-expert.com
• Can result in 50% reduction in area over λ based rules

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• Standard in industry.
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www.vlsi-expert.com DESIGN RULES
www.vlsi-expert.com Lambda-based Design Rules www.vlsi-expert.com
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•Lambda-based (scalable CMOS) design rules define
scalable rules based on l (which is half of the
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minimum channel length)

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• classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON

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•Stick diagram is a draft of real layout, it serves as an

abstract view between the schematic
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and layout.
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UNIT – II CIRCUIT DESIGN PROCESSES

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•Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
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•On the other hand, the process engineer wants design
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rules that result in a controllable and reproducible
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•Generally we find there has to be a compromise for a
competitive circuit to be produced at a reasonable cost.
•All widths, spacing, and distances
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are written in the form
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• l = 0.5 X minimum drawn transistor length

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•Design rules based on single parameter, λ www.vlsi-expert.com
•Simple for the designer

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•Wide acceptance www.vlsi-expert.com
•Provide feature size independent way of setting out mask
•If design rules are obeyed, www.vlsi-expert.com
masks will produce working
circuits
•Minimum feature size is defined as 2 λ
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•Used to preserve topological features on a chip

•Prevents shorting, opens, contacts from slipping out of
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area to be contacted
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www.vlsi-expert.com Design Rules – Reality www.vlsi-expert.com
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• Manufacturing processes have inherent limitations in
accuracy and repeatability
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• Design rules specify geometry of masks that provide
reasonable yield www.vlsi-expert.com
• Design rules are determined by experience

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•Photoresist shrinking / tearing www.vlsi-expert.com
•Variations in material deposition

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•Variations in temperature www.vlsi-expert.com
•Variations in oxide thickness
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•Impurities
•Variations between lots
•Variations across the wafer
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•Variations in threshold voltage www.vlsi-expert.com
• oxide thickness
• ion implantation
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• poly variations www.vlsi-expert.com
•Diffusion - changes in doping (variation in R, C)
•Poly, metal variations in height and width
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•Shorts and opens

•Via may not be cut all the way through
•Undersize via has too much resistance

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•Oversize via may short
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www.vlsi-expert.com Advantages of Generalized Design Rules www.vlsi-expert.com
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•Ease of learning because they are scalable, portable,
durable
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•Long-levity of designs that are simple, abstract and
minimal clutter www.vlsi-expert.com
•Increased designer efficiency

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•Automatic translation
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• Minimum width of PolySi and diffusion line 2

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• Minimum width of Metal line 3 as metal lines run over a more
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uneven surface than other www.vlsi-expert.com

conducting layers to ensure their
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continuity
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Metal
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Diffusion
3
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2
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www.vlsi-expert.com 2 Polysilicon
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• PolySi – PolySi space 2

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• Metal - Metal space 2 www.vlsi-expert.com
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Diffusion – Diffusion space
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3 To avoid the possibility of
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their associated regions overlapping and conducting current
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Metal
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2
Diffusion
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2 3 Polysilicon
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• Diffusion – PolySi space  To prevent the lines overlapping

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• Metal lines can pass over www.vlsi-expert.com

both diffusion and polySi without
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electrical effect. Where no separation is specified, metal lines
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can overlap or cross www.vlsi-expert.com
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Metal
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Diffusion
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
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• Metal lines can pass over both diffusion and polySi without
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electrical effect www.vlsi-expert.com
• It is recommended practice to leave  between a metal edge

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and a polySi or diffusion line to which it is not electrically
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
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Polysilicon
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• Recall
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• poly-poly spacing
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•diff-diff spacing 3l (depletion regions tend to spread outward)
• metal-metal spacing 2l
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• diff-poly spacing l
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Buried Contact
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contact mask relative to the polySi and therefore vary by .
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PolySi
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Channel length 
 2 
Buried contact
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2
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Diffusion
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Contact Cut
•.com
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• Contact area: 2 l X 2 l www.vlsi-expert.com
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Metal and polySi or diffusion must overlap this contact
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area by l so that the two desired conductors encompass the
contact area despite any mis-alignment between
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conducting layers and the contact hole
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4l www.vlsi-expert.com
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Contact Cut
•.com
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Contact cut – any gate: 2www.vlsi-expert.com
• Why? No contact to any part of the gate. www.vlsi-expert.com
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4l
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2l
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Contact Cut
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www.vlsi-expert Contact cut – contact cut:www.vlsi-expert.com
• Why? To prevent holes from merging. www.vlsi-expert.com
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2l
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3
6
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2
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All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
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Thinox
Metal 1
n-diffusion p-diffusion
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www. .com www.vlsi-expert.com 3λ
2 vlsi-expert
λ
3 λwww.vlsi-expert.com 3λ
2λ www.vlsi-expert.com 3λ
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Metal 2
2λ www.vlsi-expert.com 4λ
2λ
2λ 4λ
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4λ
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• Wells must surround transistors by 6 l www.vlsi-expert.com
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–
.com Implies 12 l between opposite transistor flavors
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– Leaves room for one wire track www.vlsi-expert.com
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• A wiring track is the space required for a wire www.vlsi-expert.com
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from neighbour = 8 l pitch
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• Transistors also consume one wiring track www.vlsi-expert.com
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Top view of the FET pattern www.vlsi-expert.com
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NMOS NMOS www.vlsi-expert.com
PMOS PMOS
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n+ n+ n+ n+ p+ p+ p+ p+
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n-well
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General Layout Geometry www.vlsi-expert.com
Vp www.vlsi-expert.com
Shared drain/
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source
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Individual
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Transistors
Gnd
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Metal Interconnect Layers www.vlsi-expert.com
• Metal layers are electrically isolated from each other

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• .com
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Electrical contact between adjacent conducting layers requires contact cuts
and vias www.vlsi-expert.com
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Via www.vlsi-expert.com
Metal2
Active www.vlsi-expert.com
Ox2
contact
Metal1
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p-substrate
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Interconnect Layout Example www.vlsi-expert.com
Gate contact
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Metal1
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Metal2
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Metal1 www.vlsi-expert.com
MOS
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Active contact
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Designing MOS Arrays www.vlsi-expert.com
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x y
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A
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y
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x
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Parallel Connected MOS Patterning www.vlsi-expert.com
x x
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A B
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X X X
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y
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x
X X
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A B
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X X
y y
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Basic Gate Design www.vlsi-expert.com
• Both the power supply and ground are routed using the Metal
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layer
• n+ and p+ regions are denoted using the same fill pattern. The
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only difference is the n-well

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• Contacts are needed from Metal to n+ or p+
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The CMOS NOT Gate www.vlsi-expert.com
Contact
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X n-well
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X www.vlsi-expert.com
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X
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Vp
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X X
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X X
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The CMOS NAND Gate www.vlsi-expert.com
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Gnd
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The CMOS NAND Gate www.vlsi-expert.com
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The CMOS NOR Gate www.vlsi-expert.com
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Gndwww.vlsi-expert.com X X Xwww.vlsi-expert.com
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The CMOS NOR Gate www.vlsi-expert.com
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The 3-Input NAND Gate www.vlsi-expert.com
3-input NAND www.vlsi-expert.com

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The 3-D View of a Design www.vlsi-expert.com
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GENERAL LAYOUT GUIDELINES www.vlsi-expert.com
1. The electrical gate design must be completed by checking the

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followings:
a. Right power and ground supplies www.vlsi-expert.com
b. Noise at the gate input

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c. Faulty connections and transistors www.vlsi-expert.com
d. Improper ratios
e. Incorrect clocking and charge sharing
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top and the bottom of the design
3. Vertical poysilicon for each gate input
4. Order polysilicon gate signals for maximal connection between
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The connectivity requires to place NMOS close to VSS and PMOS
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close to VDD
6. Connection to complete the logic must be made using poly, metal
and even metal2
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GENERAL LAYOUT GUIDELINES www.vlsi-expert.com
The factors for density improvement are (optimization):

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• Efficient routing space usage. They can be placed over the cells
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• Source drain connections must be merged better.

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• White (blank) spaces must be minimum.

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• The devices must be of optimum sizes.
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• Transparent routing can be provided for cell to cell
interconnection, this reduces global wiring problems
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LAYOUT OPTIMIZATION FOR PERFORMANCE

1. Vary the size of the transistor according to its position in series. The transistor
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closest to the output is the smallest. The transistor nearest to the VSS line is the
largest. This helps in increasing the performance by 30%. A three input NAND
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gate with the varying size is shown.

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2. When drains are connected in parallel, must try and reduce the number of
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least at the output. This arrangement could reduce the capacitance at the output
enabling good voltage levels.
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The VLSI design flow for any IC design is as follows

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1. Specification (problem definition)
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2. Schematic (gate level design) (equivalence check)
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3. Layout (equivalence check)

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4. Floor Planning
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Routing, Placement
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6. On to Silicon

Stick Diagram

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Stick Diagram

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•VLSI design aims to translate circuitwww.vlsi-expert.com

•stick diagrams are a means of capturing topography and layer information

using simple diagrams.

 Does show all components/vias.

 Goes one step closer to the layout

 Does not show

•VLSI design aims to translate circuit concepts onto silicon.

information using simple diagrams.

•Via is used to connect higher level metals from metal connection

A stick diagram is a cartoon

•Specifying λ particularizes the scalable rules.

www.vlsi-expert.com All wire widthswww.vlsi-expert.com

All measures are multiples of 

represents electrical contact.

When two or more ‘sticks’ of different type cross or touch each

When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

In CMOS a demarcation line is drawn to avoid touching of p-diff

www.vlsi-expert.com Vout www.vlsi-expert.com

NOR gate and NAND using NMOS Transistors

f= [(xy) +z]’ using NMOS Transistors

•Interface between designer and process engineer

• fabricator - controllable, reproducible

• minimum overlaps to ensure complete overlaps

• Defines “how fast” a fabrication process is

• “Micron” rules: stated at micron resolution.

very high probability of correct fabrication

www.vlsi-expert.com “Micron” rules www.vlsi-expert.com

• Can result in 50% reduction in area over λ based rules

www.vlsi-expert.com Lambda-based Design Rules www.vlsi-expert.com

minimum channel length)

• classes of MOSIS SCMOS rules: SUBMICRON, DEEPSUBMICRON

•Stick diagram is a draft of real layout, it serves as an

UNIT – II CIRCUIT DESIGN PROCESSES

www.vlsi-expert.com Lambda-based Design Rules www.vlsi-expert.com

• l = 0.5 X minimum drawn transistor length

www.vlsi-expert.com Lambda-based Design Rules www.vlsi-expert.com

•Simple for the designer

•Used to preserve topological features on a chip

www.vlsi-expert.com Design Rules – Reality www.vlsi-expert.com

• Design rules are determined by experience

www.vlsi-expert.com Problems in Manufacturing www.vlsi-expert.com

•Variations in material deposition

www.vlsi-expert.com Problems in Manufacturing www.vlsi-expert.com

•Shorts and opens

•Undersize via has too much resistance

www.vlsi-expert.com Advantages of Generalized Design Rules www.vlsi-expert.com

•Increased designer efficiency

• Minimum width of PolySi and diffusion line 2

uneven surface than other www.vlsi-expert.com

• PolySi – PolySi space 2

• Diffusion – PolySi space  To prevent the lines overlapping

• Metal lines can pass over www.vlsi-expert.com

can overlap or cross www.vlsi-expert.com

• It is recommended practice to leave  between a metal edge

• Contact area: 2 l X 2 l www.vlsi-expert.com

• Metal layers are electrically isolated from each other

only difference is the n-well

3-input NAND www.vlsi-expert.com

1. The electrical gate design must be completed by checking the

b. Noise at the gate input

The factors for density improvement are (optimization):