Interrupt in AVR

S u m a i y a Ta s n i m
Lecturer(Provisional)
Department of CSE
Va r e n d r a U n i v e r s i t y
 A s i m p l i fi e d a r c h i t e c t u r e o v e r v i e w o f ATm e g a 1 6 :

Program Timer/
SRAM EEPROM USART TWI ADC
ROM Counter

CPU

MCU
OSC Control Watchdog Interrupt
I/O Ports SPI ISP
& Timing Timer Unit
Crystal
Oscillator
Internal PORTA PORTB PORTC PORTD
Oscillator
Interrupt
Interrupts are the events that temporarily suspend the main program, pass the
control to the external sources and execute their task. It then passes the control
to the main program where it had left off. Interrupts are basically events that
require immediate attention by the microcontroller.

In order to responding to an interrupt event the interrupt feature of the

microcontroller must be enabled along with the specific interrupt. This is done by
setting the Global Interrupt Enabled bit and the Interrupt Enable bit of the
specific interrupt.
When an interrupt event occurs the microcontroller pause its current task and
attend to the interrupt by executing an Interrupt Sub Routine (ISR). At the end
of the ISR, the microcontroller returns to the task it had pause and continue its
normal operations.

ISR Code
Background Code Enter ISR Exit ISR Background Code

Interrupt Request

Interrupt Enable

Fig: Basic Workflow of an Interrupt

 Classification of Interrupt
Interrupt

Software/Internal Hardware/External

Example: INT0,INT1 in
Example: Timer/Counter
ATmega8
 Sources of Interrupt:

The AVR 8 bits microcontrollers provide both internal and external sources for
Interrupt.

• The internal interrupts are associated with timer/counter, ADC, USART etc.
• The external interrupts are triggered via external pins.
In ATmega8, there are two external pins for interrupt:
INT0 and INT1

Here we can input 1 or 0 into the

PD2/INT0 pin through a switch.
This is the alert or signal that triggers
the Interrupt.
There are three ways of triggering:
i) Low to high transition (0-1)
Ii) High to Low transition (1-0)
Iii) Any logical change (0-1 and 1-0)
Low to High Transition/ Rising Edge:
When the initial value in the interrupt pin
is 0, and later through any Switch or Button
or Sensor or any other device the pin is
provided power, this will change the pin
value to 1. And this 0-1 transition will
generate an interrupt request. This is also
called Rising Edge.
High to Low Transition/ Falling Edge:
When the initial value in the interrupt pin
is 1, and the pin is grounded, this will
change the pin value to 0. And this 1-0
transition will generate an interrupt
request. This is also called Falling Edge.

1 1

Rising Edge
Falling Edge
0 0
Re g i s t e r s f o r C o n fi g u r i n g E x t e r n a l I n t e r r u p t s i n ATm e g a 8 :

• SREG (Status Register)

• GICR (General Interrupt Control Register)
• MCUCR (Microcontroller Control Register)
• GIFR (General Interrupt Flag Register)
 C o n fi g u r i n g E x t e r n a l I n t e r r u p t s i n ATm e g a 8 :

Mainly there are two concerns:

• Which interrupt will be triggered (INT0 or INT1 or Both?)

---configured by GICR register
• How the interrupt will be triggered (Falling edge or rising edge or any other)
---configured by MCUCR register
 G I C R ( G e n e r a l I n t e r r u p t C o n t r o l Re g i s t e r ) :

BIT 7 6 5 4 3 2 1 0
INT1 INT0
Read/Write R/W R/W

Initial Value 0 0

Bi t 6 – I N T 0 : E xt er n a l I nt er ru pt Req u est 0 En a b l e

Bi t 7 – I N T 1 : E xt er n a l I nt er ru pt Req u est 1 En a b l e
 M C U C R ( M C U C o n t r o l Re g i s t e r ) :

BIT 7 6 5 4 3 2 1 0
ISC 11 ISC 10 ISC ISC 00
01
Read/Write R/W R/W R/W R/W

Initial Value 0 0 0 0

Fo r I N T 0 : B i t 0 , 1 – I S C 0 0 , I S C 0 1 : I n t e r r u p t S e n s e C o n t r o l - 0 B i t 0 a n d B i t 1

Fo r I N T 1 : B i t 2 , 3 – I S C 1 0 , I S C 1 1 : I n t e r r u p t S e n s e C o n t r o l - 1 B i t 0 a n d B i t 1
 M C U C R ( M C U C o n t r o l Re g i s t e r ) :

The level and edges on the external INT0 pin that activate the interrupt are defined
in below table:

Description ISC00 ISC01

The low level of INT0 generates an interrupt request. 0 0

Any logical change on INT0 generates an interrupt request. 1 0

The falling edge of INT0 generates an interrupt request. 0 1

The rising edge of INT0 generates an interrupt request. 1 1

 M C U C R ( M C U C o n t r o l Re g i s t e r ) :

The level and edges on the external INT1 pin that activate the interrupt are defined
in below table:

Description ISC10 ISC11

The low level of INT1 generates an interrupt request. 0 0

Any logical change on INT1 generates an interrupt request. 1 0

The falling edge of INT1 generates an interrupt request. 0 1

The rising edge of INT1 generates an interrupt request. 1 1

 P r o g r a m m i n g f o r I n t e r r u p t i n ATm e g a 8 :

1) A new Header File named #include<avr/interrupt.h>

2) Two(2) User Define Functions

a. One for Initializing Interrupt Function.

b. Another for Interrupt Sub Routine.
3) Registers and their Bits combination for

a. Using INT0 or INT1 or both of them making high the corresponding bits of GICR.
b. Using the Rising edge or Falling edge state of INT0 or INT1 to generate an interrupt
request making high the corresponding bits of MCUCR.
c. Declaring the global interrupt sei();
 A sample problem:

Wr i t e a p r o g r a m t o t r i g g e r a n e x t e r n a l i n t e r r u p t w i t h r i s i n g
e d g e b y I N T 0 p i n i n ATm e g a 8 m i c r o c o n t r o l l e r.
Solution:

GICR|=(1<<INT0);
MCUCR|=(1<<ISC00);
MCUCR|=(1<<ISC01);
sei();
}
 Important bits in Interrupt:

• The global interrupt enable bit must be enabled to activate the mcu interrupt.
This bit is located at 7th bit of Status Register (SREG)
• sei() is a function in Embedded C to enable Global Interrupt.
• Beside the global interrupt bit, each interrupt is associated with 2-bits: An
Interrupt Enable Bit and Interrupt Flag Bit
• The Interrupt Enable Bit is used to enable or disable a specific interrupt.
Basically through this bit is decided whether a mcu should respond to the
interrupt or not.
• The Interrupt Flag Bit is set whenever the interrupt event takes place.
SREG (Status Register ):
BIT 7 6 5 4 3 2 1 0
I T H S V N Z C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

GIFR (General Interrupt Flag Register):

BIT 7 6 5 4 3 2 1 0
INTF1 INTF0
Read/Write R/W R/W

Initial Value 0 0
 Sequence of tasks while triggering an Interrupt:

For every interrupt there is a fixed location in program memory that holds the
address of its ISR and this is known as Interrupt Vector.

1) When an interrupt is triggered, the mcu completes the execution of the current
instruction, clears the I bit of SREG and stores the address of next instruction on
the stack . Which means, the address that was on the PC (Program Counter) is
now safely stored in the stack.
2) The interrupt vector of the triggered interrupt is loaded in the PC (Program
Counter) and the mcu starts executing corresponding ISR.
 Sequence of tasks while triggering an Interrupt:

3) After execution of ISR block, the address that was stored on the stack in step-1,
is now reloaded into the PC and the I bit in SREG is re-enabled.

The mcu then starts executing instructions from the point it left off when the
interrupt was triggered.
“Be kind, for everyone you meet is fi ghti ng
a harder batt le..”

-Plato