Microprocessor & Computer

Architecture (μpCA)

Unit 4: Cache - 6th OPTIMIZATION

UE19CS252

Session : 4.3
Microprocessor & Computer Architecture (μpCA)
6th Optimization: Reduce Miss Time

Avoid Address Translation In Cache Indexing To Reduce Hit Time

Main Memory
P1
P1
P2

d dress P3
A

CPU Addre
ss P4

P4
P5

Physical Address Keeps P6

changing as a part of Memory
Management by OS
Microprocessor & Computer Architecture (μpCA)
6th Optimization: Reduce Miss Time

Avoid Address Translation In Cache Indexing To Reduce Hit Time

Main Memory

Address Translation P1
by MMU using TLB

Physical Address
CPU Virtual Address

P1

• OS help to Convert Virtual

Address to Physical Address
using MMU and Translation
Lookahead Buffer (TLB)
Microprocessor & Computer Architecture (μpCA)
What is the Problem?

Accessing data from Cache involve:

• Indexing
• Tagging

Converting Virtual Address to Physical Address take some time.

Solution1: PIPT 

Solution 2: Virtually Indexed & Physically Tagged

• Do not wait for VA to PA translation.
• Extract Index information from Virtual Address
• Extract Tag Information from the Physical Address.
 Microprocessor & Computer Architecture (μpCA)
Physically Indexed and Physically Tagged (PIPT)
CPU
Virtual Address

Page Number Offset CPU generate VA

TLB is referred to check if required Frame present or not

TLB
Frame #
PA is generated

Hit Cache is Indexed and Tagged using PA

Physical Address

Frame# ---Index----- Word

Tagging Indexing
PA Tag

== Cache
Miss Main Memory
 Microprocessor & Computer Architecture (μpCA)
Virtually Indexed and Physically Tagged

1: CPU generate VA
CPU
Virtual Address
2: TLB is referred to check if required Frame present or not &
Page Number Offset Offset is used to Index Cache

Indexing 3: PA is generated
TLB
Frame # 4: Cache is Tagged using PA
PA Tag Cache

Physical Address
Hit or
Frame# ---Index----- Offset ==
Miss

Tagging
Microprocessor & Computer Architecture (μpCA)
6th Optimization : Case Study

64 Bits Virtual Address

51 Bits Page# 13 Bits Offset • Consider the following Specification

43 Bits TLB TAG, 8 Bits TLB index 7 bits Index, 6 Bits Word • 64 bit Virtual Address

43 Bits Tag 28 Bits Frame #

• 41 bit Physical Address
L1 Cache
28 Bits Tag, 512 Bits Data • 8 KB (2^13)Page Size
== L1 28 Bits Frame #

• TLB is Direct Mapped with 256 Entries

==
To CPU

41 (28+13) Bits Physical Address

• 8 KB (2^13) Direct Mapped L1 Cache

19 Bits TAG, 16 Cache Index, 6 Bits Word • Block Size = 64 Bytes (2^6 words)
L2 Cache
19 Bits Tag, 512 Bits Data
• 4 MB Direct Mapped L2 Cache
• 2^22/2^6= 2^16
== To CPU
Microprocessor & Computer Architecture (μpCA)
6th Optimization : Optimized to Improve the Hit Time

64 Bits Virtual Address

50 Bits Page# 14 Bits Offset • Modified Specification for Cache

43 Bits TLB TAG, 7 Bits TLB index 8 bits Index, 6 Bits Word • 64 bit Virtual Address

43 Bits Tag 27 Bits Frame #

• 41 bit Physical Address
L1 Cache
27 Bits Tag, 512 Bits Data • 16 KB (2^14)Page Size
== L1 27 Bits Frame #

• 2 Way, 256 Entry TLB

==
To CPU

41 (27+14) Bits Physical Address

• 16 KB (2^14) Direct Mapped L1 Cache

21 Bits TAG, 14 Cache Index, 6 Bits Word • Block Size = 64 Bytes (2^6 words)
L2 Cache
21 Bits Tag, 512 Bits Data
• 4 MB, 4 Way, L2 Cache

== To CPU • 2^22/2^6x 2^2= 2^14

THANK YOU

Team MPCA
Department of Computer Science and Engineering