AMC Unit I PPT

UNIT- I
INTRODUCTION TO PIC
MICROCONTROLLERS
1
2
1.1
Introduction
3
1.1
Introduction
4
1.1
Introduction
Classification of PIC microcontroller
Low-end architectures Mid-range devices
• 12-bit wide • Upgradation of low-end
instructions with architectures with more
basic I/O functions. number of peripherals,
more number of registers.
• An enhancement of Analog
to Digital converter
capability
5
1.1
Introduction
Classification of PIC microcontroller
Low-end architectures Mid-range devices
• 12C5XX • 16C6X
• 16C5X • 16C7X
• 16F87X
• 16C505
• limited program • More data/program
memory memory
• Applicable only in • Applicable in Medium range
simple interface projects.
functions.
6
1.1
Introduction
Princeton Architecture
7
1.1
Introduction
Harvard Architecture
8
1.2
Series of PIC16C6X
• PIC16C61 • PIC16C64A
• PIC16C62 • PIC16CR64
• PIC16C62A • PIC16C65
• PIC16CR62 • PIC16C65A
• PIC16C63 • PIC16CR65
• PIC16CR63 • PIC16C66
• PIC16C64 • PIC16C67
9
1.2
Core features of PIC16C6X
10
1.2
Core features of PIC16C6X
11
1.2
Peripheral features of PIC16C6X
12
1.2
Peripheral features of PIC16C6X
13
1.2
Pin Diagram of PIC16C6X
14
1.2
Pin out Description of PIC16C61
Pin Name Pin Type Description
OSC1/CLKIN I Oscillator crystal input/
external clock source input.
Oscillator crystal output. Connects to crystal or
O resonator in crystal oscillator mode.
OSC2/CLKOUT In RC mode, the pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP I/P Master clear reset input or programming voltage
input. This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0 I/O
RA1 I/O
RA2 I/O
RA3 I/O
RA4/T0CKI I/O RA4 can also be the clock input to the Timer0
timer/counter.
Output is open drain type.
15
1.2
Pinout Description of PIC16C61
PORTB is a bi-directional I/O port.
PORTB can be software programmed for internal
weak pull-up on all inputs.
RB0/INT I/O RB0 can also be the external interrupt pin.
RB1 I/O
RB2 I/O
RB3 I/O
RB4 I/O Interrupt on change pin.
RB6 I/O Interrupt on change pin. Serial programming clock.
RB7 I/O Interrupt on change pin. Serial programming data.
VSS P Ground reference for logic and I/O pins.
VDD P Positive supply for logic and I/O pins.
16
1.2
PIC16C62
17
1.2
18
1.2
PIC16C63
PIC16CR63
PIC16C66
19
1.2
Pinout Description of
PIC16C62/62A/R62/63/R63/66
OSC1/CLKIN I Oscillator crystal input/external clock source input.
RA0 I/O PORTA is a bi-directional I/O port.
RA1 I/O
RA2 I/O
RA3 I/O
timer/counter. Output is open drain type.
RA5/SS RA5 can also be the slave select for the synchronous
serial port. 20
1.2
PIC16C62/62A/R62/63/R63/66
RB1 I/O
RB2 I/O
RB3 I/O
21
1.2 Pinout Description of
PIC16C62/62A/R62/63/R63/66
Pin Name Pin Description
Type
I/O PORTC is a bi-directional I/O port.
RC0/T1OSO(1)/T1CKI RC0 can also be the Timer1 oscillator output(1) or
Timer1 clock input.
RC1/T1OSI(1)/CCP2(2) I/O RC1 can also be the Timer1 oscillator input(1) or
Capture2 input/Compare2 output/PWM2 output(2).
RC2/CCP1 I/O RC2 can also be the Capture1 input/Compare1

output/PWM1 output.
RC3/SCK/SCL I/O RC3 can also be the synchronous serial clock
input/output for both SPI and I2C modes
RC4/SDI/SDA I/O RC4 can also be the SPI Data In (SPI mode) or data I/O
(I2C mode).
RC5/SDO I/O RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK(2) I/O RC6 can also be the USART Asynchronous Transmit(2)
or Synchronous Clock(2).
RC7/RX/DT(2) I/O RC7 can also be the USART Asynchronous Receive(2)
or Synchronous Data(2).
22
1.2
MZCET/EEE/EE6008/1 23
1.2
24
1.2
PIC16C65A
PIC16CR65
PIC16C67
25
1.2
PIC16C64/64A/65/65A/67
RA0 I/O PORTA is a bi-directional I/O port.
RA1 I/O
RA2 I/O
RA3 I/O
RA5/SS RA5 can also be the slave select for the synchronous
serial port. 26
1.2
PIC16C64/64A/65/65A/67
RB1 I/O
RB2 I/O
RB3 I/O
27
1.2
PIC16C64/64A/65/65A/67
Type
Timer1 clock input.

output/
PWM1 output.
(I2C mode).
28
or Synchronous Data(2).
MZCET/EEE/EE6008/1
1.2
PIC16C64/64A/65/65A/67
RD0/PSP0 I/O PORTD can be a bi-directional I/O port or parallel slave
RD1/PSP1 I/O port for interfacing to a microprocessor bus.
RD2/PSP2 I/O
RD3/PSP3 I/O
RD4/PSP4 I/O
RD5/PSP5 I/O
RD6/PSP6 I/O
RD7/PSP7 I/O
PORTE is a bi-directional I/O port.
RE0/RD I/O RE0 can also be read control for the parallel slave port.
RE1/WR I/O RE1 can also be write control for the parallel slave port.
RE2/CS I/O RE2 can also be select control for the parallel slave port.
NC - These pins are not internally connected. These pins should
be left unconnected.
29
1.2
PIC16C6X Device varieties
C, as in PIC16C64- EPROM type memory and
operate over the standard
voltage range
LC, as in PIC16LC64 EPROM type memory and
operate over an extended
voltage range
CR, as in PIC16CR64 ROM program memory and
operate over the standard
voltage range
LCR, as in ROM program memory and
PIC16LCR64 operate over an extended
voltage range
30
1.2
PIC16C6X Device varieties
UV Erasable Devices
• The UV erasable version, offered in CERDIP package is optimal
for prototype development and pilot programs.
• This version can be erased and reprogrammed to any of the
oscillator modes.
One-Time-Programmable (OTP) Devices
• Flexibility for frequent code updates and small volume
applications.
• Packaged in plastic packages, permit the user to program
them once.
• In addition to the program memory, the configuration bits
must also be programmed.
31
1.2
PIC16C6X DEVICE VARIETIES
Quick-Turnaround-Production (QTP) Devices
• Available for users who choose not to program a medium to

high quantity of units
• whose code patterns have stabilized.
• Identical to the OTP devices but with all EPROM locations and
configuration options already programmed by the factory.
Read Only Memory (ROM) Devices

• Masked ROM versions of several of the highest volume parts
• Low cost option for high volume, mature products.
32
1.2
PIC16C6X DEVICE VARIETIES
Serialized Quick-Turnaround Production
(SQTPSM) Devices
• A unique programming service where a few user-defined
locations in each device are programmed with different serial
numbers.
• The serial numbers may be random, pseudo-random, or
sequential.
• Serial programming allows each device to have a unique number
which can serve as an entry-code, password, or ID number.
• ROM devices do not allow serialization information in the
program memory space.
• The user may have this information programmed in the data
memory space.
33
1.2
Architecture of
PIC16C61
34
1.2
PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM 35

1.2
PIC16C62/62A/R62/64/64A/R64
BLOCK DIAGRAM
1: Higher order bits are from the STATUS register.
2: PORTD, PORTE and the Parallel Slave Port are not available on
the PIC16C62/62A/R62.
3: Brown-out Reset is not available on the PIC16C62/64.
4: Pin functions T1OSI and T1OSO are swapped on the

PIC16C62/64.
36
1.2
37
PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM
1.2
PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM
2: PORTD, PORTE and the Parallel Slave Port are not available
on the PIC16C63/R63.
3: Brown-out Reset is not available on the PIC16C65.
38
1.2
PIC16C66/67 BLOCK DIAGRAM

39
1.2
PIC16C66/67 BLOCK DIAGRAM
1: Higher order bits are from the STATUS

register.
2: PORTD, PORTE and the Parallel Slave Port are

not available on the PIC16C66.
40
1.2
Architectural overview
• RISC microprocessors.
• Harvard architecture, in which, program and data are
accessed from separate memories using separate buses.
• This improves bandwidth over traditional von Neumann
architecture.
• Separating program and data busses further allows
instructions to be sized differently than 8-bit wide data
words.
• Instruction opcodes are 14-bits wide making it possible to
have all single word instructions.
• A 14-bit wide program memory access bus fetches a 14-
bit instruction in a single cycle.
• All instructions execute in a single cycle (200 ns @ 20
MHz) except for program branches.
41
1.2
• The PIC16CXX device contains an 8-bit ALU and working
register (W).
Arithmetic and logic unit

• It performs arithmetic and Boolean functions between data
in the working register and any register file.
• The ALU is 8-bits wide and capable of addition, subtraction,
shift, and logical operations.
• Arithmetic operations are two's complement in nature.
• Depending upon the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and Zero
(Z) bits in the STATUS register.
• Bits C and DC operate as a borrow and digit borrow out bit,
respectively, in subtraction.
42
1.2
Working register (W register)
• The W register is an 8-bit working register used for ALU

operations.
• It is not an addressable register.
• In two-operand instructions, typically one operand is the
working register (W register), the other operand is a file
register or an immediate constant.
• In single operand instructions, the operand is either the W
register or a file register.
43
1.2 Comparison of 16C6X series
PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63
Clock Maximum 20 20 20 20 20
Frequency
of
Operation
(MHz)
Memory EPROM 1K 2K - 4K -
Program
Memory
(x14 words)
ROM - - 2K - 4K
Program
Memory
(x14 words)
Data 36 128 128 192 192
Memory
(bytes)
44
PIC16C64A PIC16C65A PIC16C66 PIC16C67
Clock Maximum 20 20 20 20
Frequency
of Operation
(MHz)
Memory EPROM 2K 4K 8K 8K
Program
Memory
(x14 words)
ROM - - - -
Program
Memory
(x14 words)
Data Memory 128 192 368 368
(bytes)
45
Peripheral Timer TMR0 TMR0, TMR0, TMR0, TMR0,

s Module(s) TMR1, TMR1, TMR1, TMR1,
TMR2 TMR2 TMR2 TMR2
Capture/ - 1 1 2 2
Compare/
PWM
Module(s)
Serial - SPI/I2C SPI/I2C SPI/I2C SPI/I2C
Port(s) USART USART
(SPI/I2C,
USART)
Parallel - - - - -
Slave Port
46
Peripherals Timer TMR0, TMR0, TMR0, TMR0,
Module(s) TMR1, TMR1, TMR1, TMR1,
TMR2 TMR2 TMR2 TMR2
Capture/ 1 2 2 2
Compare/
PWM
Module(s)
Serial Port(s) SPI/I2C SPI/I2C SPI/I2C SPI/I2C
(SPI/I2C, USART USART USART
USART)
Parallel Slave Yes Yes Yes Yes
Port
47
Features Interrupt 3 7 7 10 10
Sources
I/O Pins 13 22 22 22 22
Voltage 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Range
(Volts)
In-Circuit Yes Yes Yes Yes Yes
Serial
Programmin
g
Brown-out - Yes Yes Yes Yes
Reset
Packages 18-pin 28-pin SDIP, 28-pin SDIP, 28-pin 28-pin
DIP, SO SOIC, SSOP SOIC, SSOP SDIP, SDIP,
SOIC SOIC
48
Features Interrupt 8 11 10 11
Sources
I/O Pins 33 33 22 33
Voltage Range 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
(Volts)
In-Circuit Yes Yes Yes Yes
Serial
Programming
Brown-out Yes Yes Yes Yes
Reset
Packages 40-pin DIP; 40-pin DIP; 28-pin SDIP, 40-pin DIP;
44-pin 44-pin PLCC, SOIC, SSOP 44-pin
PLCC, MQFP, TQFP PLCC,
MQFP, MQFP,
TQFP TQFP
49
1.2
PIC16C7X
PIC 16C7X
series
50
1.2
PIC16C7X Core Features:
1.2
PIC16C7X Core Features:
52
1.2
PIC16C7X Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler, can be

incremented during sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register,
prescaler and postscaler
Capture, Compare, PWM module(s)
Capture is 16-bit, max. resolution is 12.5 ns
Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit
53
1.2
PIC16C7X Peripheral Features:
54
1.2
PIC16C72
55
1.2
PIC16C73
PIC16C76
56
1.2
PIC16C74
PIC16C77
57
1.2 Pin out Description of PIC16C72/73/76
PORTA is a bi-directional I/O port.
RA0/AN0 I/O Can also be analog input 0
RA3/AN3/Vref I/O Can also be analog input 3
RA5/SS/AN4 RA5 can also be the slave select for the synchronous
serial port. Or analog input 4
58
1.2 Pin out Description of PIC16C72/73/76
RB1 I/O
RB2 I/O
RB3 I/O
59
1.2
Pin out Description of PIC16C72/73/76
Type
Timer1 clock input.

output/
PWM1 output.
(I2C mode).
or Synchronous Data(2). 60
1.2 Pinout Description of PIC16C74/77
(additional apart from 72/73/76)
RD0/PSP0 I/O PORTD can be a bi-directional I/O port or parallel slave
RD1/PSP1 I/O port for interfacing to a microprocessor bus.
RD2/PSP2 I/O
RD3/PSP3 I/O
RD4/PSP4 I/O
RD5/PSP5 I/O
RD6/PSP6 I/O
RD7/PSP7 I/O
PORTE is a bi-directional I/O port.
RE0/RD/AN5 I/O RE0 can also be read control for the parallel slave port OR
analog Input 5
RE1/WR/AN6 I/O RE1 can also be write control for the parallel slave port. Or
Analog input 6
RE2/CS/AN7 I/O RE2 can also be select control for the parallel slave port or
Analog input7
NC - These pins are not internally connected. These pins should
be left unconnected. 61
1.2
PIC16C72 BLOCK DIAGRAM
62
1.2
PIC16C73/73A/76
BLOCK DIAGRAM
63
1.2 PIC16C73/73A/76 BLOCK DIAGRAM
Device Program Data Memory
Memory (RAM)
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
Note
64
1.2
PIC16C74/74A/77
BLOCK DIAGRAM
65
1.2 PIC16C74/74A/77 BLOCK DIAGRAM
Device Program Data Memory
Memory (RAM)
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C77 8K x 14 368 x 8
Note
66
1.2 Architectural overview
67
1.2 Architectural overview
68
1.2
CPU Registers
• Working Register (W)

• Status – Register
• FSR – File Select Register
• INDF
• PCLATH
• Program Counter
• PCL
• Eight Level Stack
69
1.2
Comparison of 16C7X series
PIC16C72 PIC16C73 PIC16C74 PIC16C76 PIC16C77
Clock Maximum 20 20 20 20 20
Frequency
of
Operation
(MHz)
Memory EPROM 2K 4K 4K 8K 8K
Program
Memory
(x14 words)
Data 128 192 192 368 368
Memory
(bytes)
70
1.2
Comparison of 16C7X series
Peripherals Timer TMR0, TMR0, TMR0, TMR0, TMR0,
Module(s) TMR1, TMR1, TMR1, TMR1, TMR1,
TMR2 TMR2 TMR2 TMR2 TMR2
Capture/ 1 2 2 2 2
Compare/
PWM
Module(s)
Serial SPI/I2C SPI/I2C SPI/I2C SPI/I2C SPI/I2C
Port(s) USART USART USART USART
(SPI/I2C,
USART)
Parallel - - Yes - Yes
Slave Port
A/D 5 5 8 5 8
Converter
Channels
71
Features Interrupt 8 11 12 11 12
Sources
I/O Pins 22 22 33 22 33
Voltage 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Range
(Volts)
In-Circuit Yes Yes Yes Yes Yes
Serial
Programmin
g
Brown-out - Yes Yes Yes Yes
Reset
Packages 28-pin 28-pin SDIP, 40-pin SDIP, 28-pin 40-pin
SDIP, SOIC, SSOP PLCC, MQFP, SDIP, SDIP,
SOIC, TQFP SOIC PLCC,
SSOP MQFP,
TQFP
72
1.3 Pipelining
73
1.3 Pipelining
74
1.3 Pipelining
Clocking Scheme/Instruction Cycle
 Internal division of oscillator clock input as Q1, Q2, Q3, and

Q4.
 PC is incremented every Q1
 Instruction is fetched from the program memory
 Latched into the instruction register in Q4.
 Decoding and execution in next Q1 through Q4.
75
1.3 Pipelining
Cycle Cycle Cycle Cycle
Fetch of nth
Execution
instruction
of nth
from
instruction
address n
Fetch of (n+1)th
Change
instruction from
program
address n+1
counter to
(goto New
new address
address
Instruction)
Fetch of (n+2)th Ignore the (n+2)th
instruction from instruction
address n+2
Fetch instruction
from new address
1.3 Pipelining
1.3 Pipelining
Two cycle instruction(Branch)
• A fetch cycle begins with the program counter (PC)

incrementing in Q1.
• In the execution cycle, the fetched instruction is latched into

the “Instruction Register (IR)” in cycle Q1.
• This instruction is then decoded and executed during the Q2,

Q3, and Q4 cycles.
• Data memory is read during Q2 (operand read) and written

during Q4 (destination write).
78
1.3 Pipelining (Example)
CY1 CY2 CY3 CY4 CY5 CY6
Fetch1 Execute1
Fetch 2 Execute2
Fetch3 Execute3
loop Address Instruction Fetch4 Flush

1 MOVLW 55h
Fetch SUB-1 Execute SUB-1
2 MOVWF PORTB
3 CALL SUB-1
4 BSF PORTA, BIT3
SUB-1 5 ADDW
All instructions are single cycle, except for any program branches. These
take two cycles since the fetch instruction is “flushed” from the pipeline
while the new instruction is being fetched and then executed.
79
1.4
Memory organisation
It has three memory blocks.

• Program memory
• Data memory
• Stack
80
1.4
Program memory Considerations
How to access 2K Program memory
Program memory
Program counter (13 bit) Hex address
000
12 11 10 0
X X 0 1 1 1 1 1 0 0 1 1 1
3 E 7
.
2K
Addresses .
Ignored Bits
(11 bit range) .
3E7
.
.
.
.
81
7FF
1.4
How to access 4K Program memory
Program memory
Program counter (13 bit) Hex address
000
12 11 0
X 1 0 1 1 1 0 1 0 0 1 0 1
B A 5
.
4K
Addresses .
Ignored Bit
(12 bit range) .
BA5
.
.
.
.
82
FFF
1.4
• Each PIC 16CXX family either consists of 2K or 4K addresses of
program memory
• A program memory of 2K needs only an 11 bit program

counter to access any address.
• A program memory of 4K needs only an 12 bit program

counter to access any address.
• 13 bit program counter allowing extension of PROM into 8K

program memory without changing the CPU structure.
• For the 4K and 2K parts the upper bits are similarly ingored
during fetches from program memory.
83
1.4
Structure of Mainline program

Mainline
Call Initial ; Initialize everything
Mainloop
Call Task1 ; Deal with Task1
Call Task2 ; Deal with Task2,
.
.
.
.
Call Looptime ;Force looptime to a fixed value
goto mainloop ;Repeat
1.4
Program Memory Map Hex address 0 00 Goto main line Program memory
001
002
003
004 Go to Int service
005
Tables
End of Tables
Mainline
Mainline
program and
its subroutines
IntService
Interrupt
service routine
and its
End of subroutines
code . 85
MZCET/EEE/EE6008/1 FFF
1.4
• Two addresses are treated in a special way by the CPU.

• After reset state, its program counter is at zero.
• Content of address H’000’1 being goto Mainline
instruction.
• when an interrupt occurs, second special address
H’004’, is loaded into the PC.
• A goto Intservice instruction can be assigned to this
address
• Cause the CPU to jump to the beginning of the
interrupt service routine.
1.4
• If task 1 is supposed to toggle an LED indicator lamp
every half second, then it need only increment a scale of
50 counter once per call of Task1.
• Then LED will be toggled once for each complete cycle
of this counter.
• The mainline program begins execution when PIC
comes out of resent.
• It continues running until one of the PIC’s interrupt
sources request service.
• At that point, the execution of mainline code is
temporarily suspended.
1.4
• CPU begins the execution of the interrupt service
routine by automaticaaly loading the program
counter with H’004’.
• At the completion of interrupt service routine,
CPU returns to where it left off in the Mainline
program.
• Program writing is somewhat simplified if all the
program code for the tables, the mainline
program and its subroutines, interrupt service
routine and its subroutines take up less than 2K
words of instruction.
1.4
Program memory
How 11 bit call instruction is executed
Hex address
X X
000
.
4 3 . 2K
0 PC LATH . Addresses
PC LATH,3 = (11 bit range)
0 .
7FF 4K
12 11 0 Addresses
800
(12 bit range)
0
Program counter (13 bit)

.
PC LATH,3 = .
1 .
FFF
1.4
• It is a result of having a one word subroutine call

instruction.
• Bits of 10….0 of the call instruction are loaded into the

program counter.
• At the same time, bits 4 and 3 of a special register called

PCLATH ( program counter Latch) are loaded into bits 12
and 11 of the program counter.
1.4
• As long as the program memory is less than 2048 words,

bits 4 and 3 of PCLATH can be left initialized to H’00’,.
• 11 address bits in the call instruction will identify the

starting address of any subroutine located upto address
F’7FF’.
• Programs larger than this, it is necessary to ensure that bit

3 of PCLATH is set or cleared appropriately each time a
subroutine is called.
• The Goto instruction which also has an 11 bit address field

requires an same treatment.
1.5 Data memory
Data Memory is also known as Register File.
Register File consists of two components.

• General purpose register file ( RAM).
• Special purpose register file (similar to SFR in
8051).
1.5 Register File Structure
00 80
Special Purpose Special Purpose

Registers Registers
(32 bytes) (32 bytes)
9F
1F A0
20
RAM
(32 bytes)
RAM Extra RAM

(96 bytes) (64 bytes)
In
PIC16C63
PIC16C65A
PIC16C73A
PIC16C74A
7F FF
Bank 0 Bank 1
93
(128 bytes) (128 bytes) MZCET/EEE/EE6008/1
GPR
Typical SFRs
General Purpose Registers
STATUS Status word + flags
User program data
OPTION Timer options
PCLATH Components of program
SFR PCL counter (PC)
Special Function Registers File Select for indirect data
FSR
Reserved for addressing
Control / configuration INTCON, PIR1, PIE1, Components of interrupt
Peripheral access PIR2, PIE2 handling
Indirect addressing PORTA, TRISA, … Access to parallel ports
Program counter TMR0, OPTION,
Timer0
INTCON, …
Core SFRs TXREG, TXSTA,

Access to serial port
RCREG, RCSTA, …
Appear in every bank at
same file address ADRESH, ADRESL,
Access to A/D converter
ADCON0, …
Access to EEPROM and
EEADRH, EEDATA, …
Flash memory
The register file can be accessed either

directly, or indirectly, through the File Select
Register (FSR)
95
1.5 SPECIAL FUNCTION REGISTERS
STATUS REGISTER (ADDRESS 03h, 83h)
bit 7 IRP(1): Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) ; 0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1(1):RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh) ;
10 = Bank 2 (100h - 17Fh) ;
01 = Bank 1 (80h - FFh) ;
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
96
STATUS REGISTER (ADDRESS 03h, 83h)
bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction ;
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)

(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C(2): Carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
97
1.5 Special Purpose Registers
• The special purpose register file consists of

input/output ports and control registers.
• Addressing from 00H to FFH requires 8 bits of address.
• Instructions that use direct addressing modes in PIC to

address these register files use 7 bits of instruction
only.
• Register bank select (RP0) bit in the STATUS register is

used to select one of the register bank
98
INDF INDF Register
Core SFR accessible at file address 00h in all banks
Virtual pointer — not physical register In register file,
Tracks contents of FSR [05] = 10h
Simplifies pointer arithmetic [06] = 0Ah
Load FSR ← 05
Example
[INDF] = 10h
In register file,
FSR++
[05] = 10h
[INDF] = 0Ah
[06] = 0Ah
Load FSR ← 05 ; FSR points to file address 05

[INDF] = 10h ; INDF points to file address 05
FSR++ ; increment FSR ⇒ FSR = 06
[INDF] = 0Ah ; INDF points to file address 06
99
OPTION Register (ADDRESS 81h)
The OPTION_REG register is a readable and writable

register, which contains various control bits to configure the
TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the
weak pull-ups on PORTB.
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
100
bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
101
bit 2-0 PS2:PS0:

Prescaler Rate Select bits
Bit value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128
102
INTCON Register (ADDRESS 0Bh, 8Bh)
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts ;
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts;
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt;
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt;
0 = Disables the RB0/INT external interrupt
103
INTCON Register (ADDRESS 0Bh, 8Bh)
bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt;
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state(1)
0 = None of the RB7:RB4 pins have changed state
104
PIE1 Register (ADDRESS 8Ch)
bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt;
0 = Disables the PSP read/write interrupt
bit 6 ADIE(2): A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt;
0 = Disables the A/D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt;
0 = Disables the USART receive interrupt
105
PIE1 Register (ADDRESS 8Ch)
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt;
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt;
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt;
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt;
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt;
0 = Disables the TMR1 overflow interrupt
106
PCON REGISTER (ADDRESS 8Eh)
R = Readable bit
W = Writable bit
bit 7-2: Unimplemented: Read as '0' U = Unimplemented bit, read as
bit 1: POR: Power-on Reset Status bit ‘0’
1 = No Power-on Reset occurred - n = Value at POR reset
0 = A Power-on Reset occurred q = value depends on conditions
(must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
107
1.5 CPU Registers
Program Counter
PC low (PCL) = PC<7:0>

Accessible by instruction reads/writes
PC high (PCH) = PC<12:8>
Not directly accessible to instructions
PC latch high (PCLATH)

Core SFR accessible at file address 0Ah in all
banks
PCH = PC<12:8> = PCLATH<4:0>
PCLATH<7:5> not implemented
page offset
PCH PCL
PC 12 11 10 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0 PCLATH
108
1.5 CPU Registers
PCL and PCLATH

• The program counter (PC) is 13-bits
wide.
• The low byte comes from the PCL
register, which is a readable and
writable register.
• The upper bits (PC<12:8>) are not
readable, but are indirectly writable
through the PCLATH register.
• On any RESET, the upper bits of the
PC will be cleared
• The upper one how the PC is
loaded on a write to PCL
(PCLATH<4:0> → PCH).
• The lower one how the PC is loaded
during a CALL or GOTO instruction
(PCLATH<4:3> → PCH).
109
1.5 Instruction Memory Space
All 8‐bit MCUs
Instruction address instruction 1…1 1…11

n bit location address … …
Location = instruction Page 2
instruction 1…1 0…00
… …
≤ 2n instructions instruction 0…1 1…11

Instruction width … …
12 / 14 / 16 bits instruction 0…1 0…11
Page instruction 0…1 0…10
Page 1
instruction 0…1 0…01
Partition of instruction instruction 0…1 0…00
memory space instruction 0…0 1…11
2k instructions / page … …
k bit offset instruction 0…0 0…11
Page 0 instruction 0…0 0…10
n bit address instruction 0…0 0…01
n – k bits k bits instruction 0…0 0…00
page offset Memory page offset
Location Address
110
1.5 Instruction Memory Space
All 8‐bit MCUs
Mid-Range instruction memory
14-bit instruction word 13 bit PC
n = 13 2 bits 11 bits
213 = 8192 instruction words page offset
k = 11 12 11 10 0
Page = 211 = 2048 = 800h words

Program counter (PC)
PC<12:11> = page number ⇒ 4 pages
PC<10:0> = offset
Reserved addresses
Address 0h
Reset vector — pointer to reset routine
Address 4h
Interrupt vector — pointer to interrupt service routine
111
1.5 Call / Return
Stack
8 level FILO buffer
Holds 13 bit instruction addresses on CALL/RETURN
literal 10 9 8 7 6 5 4 3 2 1 0
CALL
STACK PC 12 11 10 9 8 7 6 5 4 3 2 1 0
RETURN
4 3 2 1 0 PCLATH
Function entry
CALL instruction
STACK ← PC<12:0>
PCL ← literal<10:0> from instruction
PCH<12:11> ← PCLATH<4:3>
Function exit
RETURN instruction
PC<12:0> ← STACK
PCLATH not updated
May be different from PCH after RETURN
112
1.6 Instruction Format
13 8 7 6 0 Byte oriented
opcode d f d = 0 ⇒ destination = W
d = 1 ⇒ destination = f
f = 7 bit file address
13 10 9 7 6 0 Bit oriented
opcode b f b = bit position in register
f = 7 bit file address
13 8 7 0 General literal
opcode k
k = 8 bit literal (immediate)
13 11 10 0 CALL / GOTO
opcode k k = 11 bit literal (immediate)
113
1.6 Instruction Set
Single bit Manipulation

Mnemonic Operands Description Cycles Status bits
affected
bcf f,b Clear bit b of register f, 1

Where bit b = 0 to 7
bsf f,b set bit b of register f, 1
Where bit b = 0 to 7
114
1.6 Instruction Set
Clear/move

affected
clrw Clear W 1 Z
clrf f Clear f 1 Z
movlw k Move literal value to W 1
movwf f Move the value of W to f 1
movf f,F(W) Move the value of f to F 1 Z
or W
swapf f,F(W) Swap nibbles of f, putting 1
result into F or W
115
1.6 Instruction Set
Increment/Decrement/complement
affected
incf f,F(W) Increment f, putting result 1 Z

into F or W
decf f,F(W) Decrement f, putting 1 Z
result into F or W
comf f,F(W) Complement f, putting 1 Z
result into F or W
116
1.6 Instruction Set
Addition/Subtraction
affected
addlw k Add literal value into W 1 C, DC, Z
addwf f,F(W) Add W with f, Putting 1 C, DC, Z

result into F or W
sublw k Subtract W from literal 1 C, DC, Z
value, putting result in W
subwf f,F(W) Subtract W from f, putting 1 C, DC, Z
result in F or W
117
1.6 Instruction Set
Multiple bit manipulation
affected
andlw k AND literal value into W 1 Z

andwf f,F(W) AND W with f, Putting 1 Z
result into F or W
iorlw k Inclusive OR literal value 1 Z
into W
iorwf f,F(W) Inclusive OR W with f, 1 Z
Putting result into F or W
xorlw k Exclusive OR literal value 1 Z
into W
xorwf f,F(W) Exclusive OR with f, Putting 1 Z
result into F or W
118
1.6 Instruction Set
Rotate

affected
rlf f,F(W) Copy f into F or W; 1 C

Rotate F or W left through
the carry bit
rrf f,F(W) Copy f into F or W; 1 C
Rotate F or W right
through the carry bit
119
1.6 Instruction Set
Conditional Branch
affected
btfsc f,b Test bit b of register f, 1 (2)

where bit b = 0 to 7;
Skip if clear.
btfss f,b Test bit b of register f, 1 (2)
where bit b = 0 to 7;
Skip if set.
decfsz f,F(W) Decrement f, putting 1 (2)
result into F or W;
Skip if zero.
incfsz f,F(W) increment f, putting result 1 (2)
into F or W;
Skip if zero.
120
1.6 Instruction Set
unconditional Branch
affected
goto Label Go to labeled instruction 2
call label Call labeled instruction 2

return Return from subroutine 2
retlw k Return from subroutine, 2
putting literal value in W
retfie Return from interrupt 2

service routine;
Re enable interrupts
121
1.6 Instruction Set
Miscellaneous

affected
clrwdt Clear watch dog timer 1 NOT_T0,

NOT_PD
sleep Go to in standby mode 1 NOT_T0,
NOT_PD
nop No operation 1
122
1.7 Addressing Modes
Direct Addressing
7 6 5 4 3 2 1 0
STATUS Register
X X X X X X
RP1 RP0 6 5 4 3 2 1 0
Instruction
0 0
Address
Bank
00 80
Content Bank0 Bank1
7F FF 123
Notation
REG<b> Bit b in register REG
REG<a:b> Bits a to b in register REG
Concatenation of A and B
A.B
(A bits followed by B bits)
Direct addressing RP1 RP0 7 bits from instruction

Program specifies data address bank file address
Bank selection 8 7 6 5 4 3 2 1 0
STATUS bits RP1 and RP0
On reset
RP1 = RP0 = 0 ⇒ bank 0 selected
Bank switching
Write to STATUS<6:5>
File Address
Literal field in instruction
124
Indirect Addressing
7 6 5 4 3 2 1 0
STATUS Register
X X X X X X X
IRP1 7 6 5 4 3 2 1 0 FSR
0
1
Address
Bank
00 80
INDF Bank0 Bank1
7F FF 125
Indirect addressing
Program writes to Special Function Registers (SFRs)
Address formed from SFRs
Instructions can increment/decrement SFR values
Similar to pointer arithmetic
File Select Register (FSR)
Core SFR accessible at file address 08h in all banks
File Address IRP 8 bits of FSR

FSR<6:0>
bank file address
Bank 8 7 6 5 4 3 2 1 0
IRP.FSR<7>
STATUS bit IRP (Indirect Register Pointer)
On small devices
1 or 2 banks = 128 or 256 bytes of data memory
8 bit FSR address covers 2 banks
IRP not implemented (read 0 / write = NOP)
126
1.8
Sample Program
RAM Initialization In register file,
[05] = 10h
CLRF STATUS ; STATUS ← 0 [06] = 0Ah
MOVLW 0x20 ; W ← 1st address in GPR bank 0 Load FSR ← 05
MOVWF FSR ; Indirect address register ← W [INDF] = 10h
Bank0_LP FSR++
CLRF INDF0 ; address in GPR ← 0
[INDF] = 0Ah
INCF FSR ; FSR++ (next GPR address)
BTFSS FSR, 7 ; skip if (FSR<7> == 1) ⇒ FSR = 80h
GOTO Bank0_LP ; continue
; ** IF DEVICE HAS BANK1 **
MOVLW 0x80 ; W ← 1st address in GPR bank 1
MOVWF FSR ; Indirect address register ← W
Bank1_LP
CLRF INDF0 ; address in GPR ← 0
INCF FSR ; FSR++ (next GPR address)
BTFSS STATUS, C ; skip if (STATUS<0> == 1) ⇒
FSR = 00h
GOTO Bank1_LP ; continue
127
1.8
Sample Program
Branch to address in new page
Prog:
movlw HIGH Prog10
; W ← Prog10<15:8>
; operator HIGH reads bits <15:8>
of pointer
movwf PCLATH ; PCLATH ← W
goto Prog10 ; PC<10:0> ← Prog10<7:0>
; PC<12:11> ← PCLATH<4:3>
Prog10:
;
; Prog10 labels some address in program memory
;
128
1.8
Sample Program
Computed goto
movlw HIGH Prog20 ; W ← Prog20<15:8>
movlw LOW Prog20 ; W ← Prog20<7:0>
movwf PCL ; PCL ← Prog20<7:0>
; PCH ← PCLATH<4:0>
Prog20:
;
; Prog20 labels some address in program memory
;
129
1.8 Sample Programs
if‐else branch
btfss f,b ; skip one instruction if
; bit b in register f = 1
goto Action2
Action1:
Yes No
; instructions for Action1 F<b> =1?
goto Action3
Action2:
; instructions for Action2
Action3:
; instructions for Action3
130
1.8
Sample Programs
Static loop
movlw times ; W ← times

movwf COUNTER ; COUNTER ← W (times)
Loop:
;
; loop instructions
;
decfsz COUNTER, f ; COUNTER--
; COUNTER = 0 ⇒ skip next
instruction
goto Loop ; next iteration
End:
;
;
131
1..8
Sample Programs
Data table in instruction memory
; Function call returns data at Table.INDEX
movlw HIGH Table ; W ← Table<15:8>
movf INDEX, W ; W ← INDEX
call Table ; Call to subroutine table
;
Table:
addwf PCL, f ; PCL ← PCL + W = PCL + INDEX
; computed goto
retlw ; return with W ← 'A'

retlw
retlw
retlw
retlw
132

AMC Unit I PPT

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UNIT- I

RC2/CCP1 I/O RC2 can also be the Capture1 input/Compare1

RC2/CCP1 I/O RC2 can also be the Capture1 input/Compare1

• Available for users who choose not to program a medium to

Read Only Memory (ROM) Devices

PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM 35

1: Higher order bits are from the STATUS register.

3: Brown-out Reset is not available on the PIC16C62/64.

4: Pin functions T1OSI and T1OSO are swapped on the

1: Higher order bits are from the STATUS register.

3: Brown-out Reset is not available on the PIC16C65.

PIC16C66/67 BLOCK DIAGRAM

1: Higher order bits are from the STATUS

2: PORTD, PORTE and the Parallel Slave Port are

Arithmetic and logic unit

• The W register is an 8-bit working register used for ALU

Peripheral Timer TMR0 TMR0, TMR0, TMR0, TMR0,

Timer0: 8-bit timer/counter with 8-bit prescaler

Timer1: 16-bit timer/counter with prescaler, can be

Compare is 16-bit, max. resolution is 200 ns

PWM max. resolution is 10-bit

RC2/CCP1 I/O RC2 can also be the Capture1 input/Compare1

PIC16C72 BLOCK DIAGRAM

• Working Register (W)

 Internal division of oscillator clock input as Q1, Q2, Q3, and

• A fetch cycle begins with the program counter (PC)

• In the execution cycle, the fetched instruction is latched into

• This instruction is then decoded and executed during the Q2,

• Data memory is read during Q2 (operand read) and written

loop Address Instruction Fetch4 Flush

It has three memory blocks.

• A program memory of 2K needs only an 11 bit program

• A program memory of 4K needs only an 12 bit program

• 13 bit program counter allowing extension of PROM into 8K

Structure of Mainline program

• Two addresses are treated in a special way by the CPU.

Program counter (13 bit)

• It is a result of having a one word subroutine call

• Bits of 10….0 of the call instruction are loaded into the

• At the same time, bits 4 and 3 of a special register called

• As long as the program memory is less than 2048 words,

• 11 address bits in the call instruction will identify the

• Programs larger than this, it is necessary to ensure that bit

• The Goto instruction which also has an 11 bit address field

Data Memory is also known as Register File.

Register File consists of two components.

Special Purpose Special Purpose

RAM Extra RAM

Core SFRs TXREG, TXSTA,

The register file can be accessed either

STATUS REGISTER (ADDRESS 03h, 83h)

STATUS REGISTER (ADDRESS 03h, 83h)

bit 3 PD: Power-down bit

bit 2 Z: Zero bit

bit 1 DC: Digit carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)

bit 0 C(2): Carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)

• The special purpose register file consists of

• Addressing from 00H to FFH requires 8 bits of address.

• Instructions that use direct addressing modes in PIC to

• Register bank select (RP0) bit in the STATUS register is

Load FSR ← 05 ; FSR points to file address 05

OPTION Register (ADDRESS 81h)

The OPTION_REG register is a readable and writable