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Introduction to Engineering

Boolean Algebra and


Digital Logic
Objectives

• Understand the relationship between Boolean logic


and digital computer circuits.
• Learn how to design simple logic circuits.
• Understand how digital circuits work together to
form complex computer systems.

2
Overview
1. Binary logic
2. Boolean Algebra
– Basic Properties
– Algebraic Manipulation
3. Standard and Canonical Forms
– Minterms and Maxterms (Canonical forms)
– SOP and POS (Standard forms)
4. Karnaugh Maps (K-Maps)
– 2, 3, 4, and 5 variable maps
– Simplification using K-Maps
5. K-Map Manipulation
– Implicants: Prime, Essential
– Don’t Cares
6. Logic Gates

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Note: From here to end of the
presentation, for easy typing,
symbol Ā equivalen A’, .... (and
similar with other variables)

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1. BINARY LOGIC

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Binary Logic
• Deals with binary variables that take 2 discrete
values (0 and 1), and with logic operations
• Three basic logic operations:
– AND, OR, NOT
• Binary/logic variables are typically represented
as letters: A,B,C,…,X,Y,Z

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Binary Logic Function
F(vars) = expression
Operators ( +, •, ‘ )
Variables (x, y, z, ..a, b, c)
set of binary
Constants ( 0, 1 )
variables
Groupings (parenthesis)

Example: F(a,b) = a’•b + b’ =


G(x,y,z) = x•(y+z’)
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Basic Logic Operators
• AND
Binary
• OR
Unary
• NOT

• F(a,b) = a•b, F is 1 if and only if a=b=1


• G(a,b) = a+b, G is 1 if either a=1 or b=1
• H(a) = a’, H is 1 if a=0

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Basic Logic Operators (cont.)
• 1-bit logic AND resembles binary
multiplication:
0 • 0 = 0, 0 • 1 = 0,
1 • 0 = 0, 1•1 =1
• 1-bit logic OR resembles binary addition,
except for one operation:
0 + 0 = 0, 0 + 1 = 1,
1 + 0 = 1, 1 + 1 = 1 (≠ 102)

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2. BOOLEAN ALGEBRA

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Boolean Algebra
• Boolean Algebra is the mathematics that use to analyse digital
gates and circuits. We can use these “Laws of Boolean” to
both reduce and simplify a complex Boolean expression in an
attempt to reduce the number of logic gates required. 
• Boolean Algebra is therefore a system of mathematics based
on logic that has its own set of rules or laws which are used to
define and reduce Boolean expressions.
• Terminology:
– Literal: A variable or its complement
– Product term: literals connected by •
– Sum term: literals connected by +

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2.1 Laws of Boolean Algebra
• A set of rules or Laws of Boolean Algebra
expressions have been invented to help
reduce the number of logic gates needed to
perform a particular logic operation resulting
in a list of functions or theorems known
commonly as the Laws of Boolean Algebra.

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Truth Tables for the Laws of Boolean

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Description of the Laws of Boolean Algebra

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Description of the Laws of Boolean Algebra

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Description of the Laws of Boolean Algebra

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Description of the Laws of Boolean Algebra

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DeMorgan’s theorems

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Description of the Laws of Boolean Algebra

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Duality
With respect to duality, Identities 1 – 8
have the following relationship:

1. X+0=X 2. X•1 =X (dual of 1)


3. X+1 =1 4. X•0 =0 (dual of 3)
5. X+X=X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)

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2.2 Boolean Algebra Truth Tables
• Tabular form that uniguely represents the
relationship between the input variables of a
function and its output.
• A logic gate truth table shows each possible
input combination to the gate or circuit with
the resultant output depending upon the
combination of these input(s).

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Boolean Algebra Truth Tables
• 2-input AND Gate
For a 2-input AND gate, the output Q is true if BOTH
input A “AND” input B are both true, giving the Boolean
Expression of: ( Q = A and B)

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Boolean Algebra Truth Tables
• 2-input OR (Inclusive OR) Gate
• For a 2-input OR gate, the output Q is true if EITHER
input A “OR” input B is true, giving the Boolean
Expression of: ( Q = A or B ).

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Boolean Algebra Truth Tables
• NOT Gate (Inverter)
• For a single input NOT gate, the output Q is ONLY true
when the input is “NOT” true, the output is the inverse
or complement of the input giving the Boolean
Expression of: ( Q = NOT A ).

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Boolean Algebra Truth Tables
• 2-input NAND (Not AND) Gate
• For a 2-input NAND gate, the output Q is NOT true if
BOTH input A and input B are true, giving the Boolean
Expression of: ( Q = not(A AND B) ).

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Boolean Algebra Truth Tables
• 2-input NOR (Not OR) Gate
• For a 2-input NOR gate, the output Q is true if BOTH
input A and input B are NOT true, giving the Boolean
Expression of: ( Q = not(A OR B) ).

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Common logic functions

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Truth Tables (cont.)
• Q: Let a function F() depend on n variables.
How many rows are there in the truth table of
F() ?

n n
 A: 2 rows, since there are 2 possible
binary patterns/combinations for the n
variables

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Truth Tables (revisited)
• Enumerates all possible x y z F1 F2 F3
combinations of variable values 0 0 0 0 1 1
and the corresponding function 0 0 1 0 0 1
value
0 1 0 0 0 1
• Truth tables for some arbitrary
0 1 1 0 1 1
functions
F1(x,y,z), F2(x,y,z), and F3(x,y,z) are 1 0 0 0 1 0
shown to the right. 1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 1 0 1
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Truth Tables (cont.)
• Truth table: a unique representation of a Boolean
function
• If two functions have identical truth tables, the
functions are equivalent (and vice-versa).
• Truth tables can be used to prove equality theorems.
• However, the size of a truth table grows
exponentially with the number of variables involved,
hence unwieldy. This motivates the use of Boolean
Algebra.

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Boolean expressions-NOT unique
• Unlike truth tables, expressions x y z F G
representing a Boolean function are NOT 0 0 0 1 1
unique.
0 0 1 0 0
• Example:
– F(x,y,z) = x’•y’•z’ + x’•y•z’ + x•y•z’ 0 1 0 1 1
– G(x,y,z) = x’•y’•z’ + y•z’ 0 1 1 0 0
• The corresponding truth tables for F() and
1 0 0 0 0
G() are to the right. They are identical.
• Thus, F() = G() 1 0 1 0 0
1 1 0 1 1
1 1 1 0 0
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3. STANDARD AND CANONICAL
FORMS
Note: From here to end of the presentation,
for easy typing, symbol Ā equivalen A’, .... (and
similar with other variables)

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Canonical and Standard Forms
• We need to consider formal techniques for the
simplification of Boolean functions.
– Identical functions will have exactly the same
canonical form.
– Minterms and Maxterms
– Sum-of-Minterms and Product-of- Maxterms
– Product and Sum terms
– Sum-of-Products (SOP) and Product-of-Sums (POS)

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Definitions
• Literal: A variable or its complement
• Product term: literals connected by •
• Sum term: literals connected by +
• Minterm: a product term in which all the variables
appear exactly once, either complemented or
uncomplemented
• Maxterm: a sum term in which all the variables
appear exactly once, either complemented or
uncomplemented

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Minterm
• Represents exactly one combination in the truth table.
• Denoted by mj, where j is the decimal equivalent of
the minterm’s corresponding binary combination (bj).
• A variable in mj is complemented if its value in bj is 0,
otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3. Then, bj
= 011 and its corresponding minterm is denoted by mj
= A’BC

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Maxterm
• Represents exactly one combination in the truth table.
• Denoted by Mj, where j is the decimal equivalent of
the maxterm’s corresponding binary combination (bj).
• A variable in Mj is complemented if its value in bj is 1,
otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3. Then, bj
= 011 and its corresponding maxterm is denoted by Mj
= A+B’+C’

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Truth Table notation for Minterms and
Maxterms
• Minterms and x y z Minterm Maxterm
Maxterms are easy 0 0 0 x’y’z’ = m0 x+y+z = M0
to denote using a 0 0 1 x’y’z = m1 x+y+z’ = M1
truth table. 0 1 0 x’yz’ = m2 x+y’+z = M2
• Example: 0 1 1 x’yz = m3 x+y’+z’= M3
Assume 3 variables 1 0 0 xy’z’ = m4 x’+y+z = M4
x,y,z 1 0 1 xy’z = m5 x’+y+z’ = M5
(order is fixed) 1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7

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Canonical Forms (Unique)
• Any Boolean function F( ) can be expressed as a
unique sum of minterms and a unique product
of maxterms (under a fixed variable ordering).
• In other words, every function F() has two
canonical forms:
– Canonical Sum-Of-Products (sum of minterms)
– Canonical Product-Of-Sums (product of maxterms)

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Canonical Forms (cont.)
• Canonical Sum-Of-Products:
The minterms included are those mj such that
F( ) = 1 in row j of the truth table for F( ).
• Canonical Product-Of-Sums:
The maxterms included are those Mj such that
F( ) = 0 in row j of the truth table for F( ).

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Converting an SOP Expression into a Truth Table

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Converting an POS Expression into a Truth Table

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Example
• Truth table for f1(a,b,c) at right
a b c f1
• The canonical sum-of-products form for f1 is
f1(a,b,c) = m1 + m2 + m4 + m6 00 0 0
= a’b’c + a’bc’ + ab’c’ + abc’ 00 1 1
• The canonical product-of-sums form for f1 is 01 0 1
f1(a,b,c) = M0 • M3 • M5 • M7
01 1 0
= (a+b+c)•(a+b’+c’)•
(a’+b+c’)•(a’+b’+c’). 10 0 1
• Observe that: mj = Mj’ 10 1 0
1 1 0 1
1 1 1 0
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Shorthand: ∑ and ∏
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a
sum-of-products form, and m(1,2,4,6) indicates that
the minterms to be included are m1, m2, m4, and m6.
• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is
a product-of-sums form, and M(0,3,5,7) indicates that
the maxterms to be included are M0, M3, M5, and M7.
• Since mj = Mj’ for any j,
∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)

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Conversion Between Canonical Forms

• Replace ∑ with ∏ (or vice versa) and replace those j’s that
appeared in the original form with those that do not.
• Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)

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Standard Forms (NOT Unique)
• Standard forms are “like” canonical forms,
except that not all variables need appear in
the individual product (SOP) or sum (POS)
terms.
• Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.

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Conversion of SOP from standard to
canonical form
• Expand non-canonical terms by inserting
equivalent of 1 in each missing variable x:
(x + x’) = 1
• Remove duplicate minterms
• f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc + ab’c’
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Conversion of POS from standard to
canonical form
• Expand noncanonical terms by adding 0 in terms of
missing variables (e.g., xx’ = 0) and using the
distributive law
• Remove duplicate maxterms
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)

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4. KARNAUGH MAPS

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Karnaugh Maps
• Karnaugh maps (K-maps) are graphical
representations of boolean functions.
• One map cell corresponds to a row in the
truth table.
• Also, one map cell corresponds to a minterm
or a maxterm in the boolean expression
• Multiple-cell areas of the map correspond to
standard terms.

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Two-Variable Map
x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1
OR 0 m0 m2
2 3 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT for f(x1,x2),


x1 is the row, x2 is the column.
Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc.
If a minterm is present in the function, then a 1 is
placed in the corresponding cell.
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Two-Variable Map (cont.)
• Any two adjacent cells in the map differ by ONLY one
variable, which appears complemented in one cell
and uncomplemented in the other.
• Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2 (=x1x2’)
but NOT m3 (=x1x2)

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2-Variable Map - Example
• f(x1,x2) = x1’x2’+ x1’x2 + x1x2’
= m 0 + m1 + m 2
= x1’ + x2’
• 1s placed in K-map for specified
x2
minterms m0, m1, m2 x1 0 1
• Grouping (ORing) of 1s allows 0 1
simplification
• What (simpler) function is 0 1 1
represented by each dashed
rectangle? 2 3
– x1’ = m0 + m1
– x2’ = m0 + m2
1 1 0
• Note m0 covered twice

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Minimization as SOP using K-map
• Enter 1s in the K-map for each product term in the
function
• Group adjacent K-map cells containing 1s to obtain a
product with fewer variables. Group size must be in
power of 2 (2, 4, 8, …)
• Handle “boundary wrap” for K-maps of 3 or more
variables.
• Realize that answer may not be unique

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Three-Variable Map
yz
x 00 01 11 10
0 1 3 2

0 m0 m1 m3 m2
4 5 7 6
1 m4 m5 m7 m6

-Note: variable ordering is (x,y,z); yz specifies column, x


specifies row.
-Each cell is adjacent to three other cells (left or right or
top or bottom or edge wrap)

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Three-Variable Map (cont.)
minterm
The types of structures that are
either minterms or are
generated by repeated
application of the minimization
theorem on a three variable map
are shown at right.
Groups of 1, 2, 4, 8 are possible.

group of 2 terms

group of 4 terms
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Simplification
• Enter minterms of the Boolean function into
the map, then group terms
• Example: f(a,b,c) = a’c + abc + bc’
• Result: f(a,b,c) = a’c+ b
a bc
1 1 1
1 1
1 1 1
1 1

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More Examples
yz
X 00 01 11 10

• f1(x, y, z) = ∑ m(2,3,5,7) 0 1 1
 f1(x, y, z) = x’y + xz 1 1 1

• f2(x, y, z) = ∑ m (0,1,2,3,6)
1 1 1 1
f2(x, y, z) = x’+yz’
1

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Four-Variable Maps
YZ

WX 00 01 11 10

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

• Top cells are adjacent to bottom cells. Left-edge cells


are adjacent to right-edge cells.
• Note variable ordering (WXYZ).

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Four-variable Map Simplification
• One square represents a minterm of 4 literals.
• A rectangle of 2 adjacent squares represents a
product term of 3 literals.
• A rectangle of 4 squares represents a product term of
2 literals.
• A rectangle of 8 squares represents a product term of
1 literal.
• A rectangle of 16 squares produces a function that is
equal to logic 1.

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Example
• Simplify the following Boolean function (A,B,C,D) =
∑m(0,1,2,4,5,7,8,9,10,12,13).
• First put the function g( ) into the map, and then
group as many 1s as possible.
cd
ab
1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

1 1 1 1 1 1

g(A,B,C,D) = c’+b’d’+a’bd
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Don't Care Conditions
• There may be a combination of input values which
– will never occur
– if they do occur, the output is of no concern.
• The function value for such combinations is called a don't
care.
• They are denoted with x or –. Each x may be arbitrarily
assigned the value 0 or 1 in an implementation.
• Don’t cares can be used to further simplify a function

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Minimization using Don’t Cares
• Treat don't cares as if they are 1s to generate
PIs.
• Delete PI's that cover only don't care
minterms.
• Treat the covering of remaining don't care
minterms as optional in the selection process
(i.e. they may be, but need not be, covered).

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cd
ab 00 01 11 10
Example 00 0 1 0 1
01 1 1 0 1
• Simplify the function f(a,b,c,d) 11 0 0 x x
10 1 1 x x
whose K-map is shown at the
right. 0 1 0 1
• f = a’c’d+ab’+cd’+a’bc’ 1 1 0 1
0 0 x x
or 1 1 x x
• f = a’c’d+ab’+cd’+a’bd’
0 1 0 1
1 1 0 1
0 0 x x
1 1 x x
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cd
Another Example ab
x 1 0 0
1 x 0 x
• Simplify the function 1 x x 1

g(a,b,c,d) whose K-map is 0 x x 0

shown at right. x 1 0 0
• g = a’c’+ ab 1 x 0 x
1 x x 1
or 0 x x 0
• g = a’c’+b’d
x 1 0 0
1 x 0 x
1 x x 1
0 x x 0
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5. LOGIC GATES

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Logic Gates
• Logic gates are abstractions of electronic circuit
components that operate on one or more input
signals to produce an output signal.

2-Input AND 2-Input OR NOT (Inverter)

A A
B F G A H
B

F = A•B G = A+B H = A’

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NOT Gate – IC 7404
A NOT gate can only have one input and the output is
the inverse of the input. A NOT gate is also called an
inverter.
The output Q is true when the input A is NOT
true: Q = NOT A

Input A Output Q
0 1
1 0
75/Chapter3

AND Gate – IC 7408


An AND gate can have two
A Kí hiệu phần or more inputs, its output is
Q
B tử true if all inputs are true. The
output Q is true if input A
AND input B are both
true: Q = A.B (A AND B)
76/Chapter3

OR Gate – IC 7432
• 2-input (A, B) Logic OR
Kí hiệu phần Gate has an output term
tử represented by the Boolean
expression of:  Q = A+B
• Output action will become
TRUE if either one “OR”
more events are TRUE.
Mạch điện
77/Chapter3

NAND Gate – IC 7400


The NAND or “Not AND”
function is a combination of
Kí hiệu phần Bảng trạng
the two separate thái
logical
tử functions, the AND function
and the NOT function in
series. The logic NAND
function can be expressed by
the Boolean expression
of, A.B
Mạch điện
NOR Gate - IC 7402

To create a NOR gate,


the OR function and
the NOT function are
connected together in
series with its operation
given by the Boolean
expression as, A + B

Mạch điện
XOR and XNOR
X Y F = XY
XOR: “not-equal” gate 0 0 0
0 1 1
X F
1 0 1
Y 1 1 0

X Y F = XY
XNOR: “equal” gate 0 0 1
0 1 0
X F
1 0 0
Y 1 1 1

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Symbols of electronic devices
Timing Diagram
t0 t1 t2 t3 t4 t5 t6
1
Input A 0
1 Transitions
signals B 0

1
F=A•B 0 Basic
Gate
1 Assumption:
Output G=A+B 0 Zero time for
Signals
1 signals to
H=A’ 0 propagate
Through gates
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Combinational Logic Circuit
from Logic Function
• Consider function F = A’ + B•C’ + A’•B’
• A combinational logic circuit can be constructed to implement F, by
appropriately connecting input signals and logic gates:
– Circuit input signals  from function variables (A, B, C)
– Circuit output signal  function output (F)
– Logic gates  from logic operations

A F

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Combinational Logic Circuit
from Logic Function (cont.)
• In order to design a cost-effective and
A B C F G
efficient circuit, we must minimize
0 0 0 1 1
the circuit’s size (area) and
propagation delay (time required for 0 0 1 1 1
an input signal change to be 0 1 0 1 1
observed at the output line) 0 1 1 1 1
• Observe the truth table of F=A’ + 1 0 0 0 0
B•C’ + A’•B’ and G=A’ + B•C’ 1 0 1 0 0
• Truth tables for F and G are identical 1 1 0 1 1
 same function
1 1 1 0 0
• Use G to implement the logic circuit
(less components)

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Combinational Logic Circuit
from Logic Function (cont.)
C

A F

C
B
A G

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Homework
Bài 1:
•Hãy xây dựng một mạch điện từ các phần
tử logic cơ bản thực hiện phép so sánh
tương đương (khi hai đầu vào bằng nhau
đầu ra có giá trị 1, khi hai đầu vào khác nhau
thì đầu ra có giá trị 0).
Homework
Bài 2:
•Hãy xây dựng một mạch điện từ các phần
tử logic cơ bản thực hiện phép so sánh
tương đương khác dấu (khi hai đầu vào
bằng nhau đầu ra có giá trị 0, khi hai đầu vào
khác nhau thì đầu ra có giá trị 1).
Homework
Bài 3:
•Hãy xây dựng một mạch điện từ các phần tử
logic cơ bản thực hiện phép so sánh hai số 1
bit. Phần tử so sánh hai số 1 bít có hai biến
đầu vào là A, B và ba đầu ra F1, F2, và F3.
– F1 = 1 khi A>B
– F2 = 1 khi A=B
– F3 = 1 khi A,B
Homework
Bài 4:
•Hãy xây dựng một mạch điện từ các phần
tử logic cơ bản thực hiện phần tử nửa tổng.
Phần tử này là một mạch logic có 2 biến đầu
vào A, B và 2 đầu ra (S và P) thực hiện hệ
hàm:
–S=A+B
– P = A.B
References
• https://www.electronics-tutorials.ws/bool
ean/bool_5.html
• https://electronicsclub.info/
gates.htm#:~:text=A%20truth%20table
%20is%20a,output%20of%20an%20AND
%20gate.
• https://www.elprocus.com/top-10-simple-
electronic-circuits-for-beginners/
THANK YOU

2023.07.12 Boolean Algebra PJF - 90

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