TRIBHUVAN UNIVERSITY

INSTITUTE OF ENGINEERING
THAPATHALI CAMPUS
Basic Electronics Engineering
BEX,BCT,BEL,BIE,BCE,BME,BAME
Chapter 3: Transistors
Er. Umesh Kanta Ghimire
Department of Electronics & Computer Engineering
IOE ,Thapathali Campus
ukg@tcioe.edu.np
+977-9843082840
16 September , 2020
Chapter 3 Transistor [8hrs]

3.1 BJT configuration and biasing, small and large signal model
3.2 T and model
3.3 Concept of differential amplifier using BJT
3.4 BJT switch and logic circuits
3.5 Construction and working principle of MOSFET and CMOS
3.6 MOSFET as logic circuits

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Transistor
• When the third doped element is added to a crystal diode in such a way that
two PN-junctions are formed, the resulting device is transistor
• A word transistor was derived from the two word combination, transfer-
resistance
• A transfer is a device to transfer a low resistance in to a circuit having high
resistance
 Trans: Signal transfer property of device
 istor: Solid element in the same general family with resistor
• The forward biased junction has a low resistance path whereas reversed
biased junction has high resistance path. The weak signal is introduced in
the low resistance circuit and output is taken from high resistance circuit.
Therefore a transistor transfers a signal from a low resistance to high
resistance
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Transistor types
Transistor
Bipolar junction transistor (BJT)
npn

pnp

Field effect transistor (FET)

Junction field effect transistor (JFET)
Depletion mode
n-channel

p-channel

Metal oxide semiconductor field effect transistor (MOSFET)

Depletion mode
n-channel

p-channel

Enhancement mode
n-channel

p-channel

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Bipolar junction transistor (BJT)
• It is called bipolar because the conduction takes place due to both
electrons as well as holes
• BJT is a three layered semiconductor device which is able to amplify a
signal
• There are two types of BJT
1. npn = consists of two n- and one p-type layers of material
2. pnp = consists of two p- and one n-type layers of material
• There are three terminals in the BJT
1. Base (B)
2. Collector (C)
3. Emitter (E)

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Symbolic Representation

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Transistor current (dc-current)
• npn transistors perform better than the
pnp transistors. The reason is that
current in the npn transistor is due to
electrons while in the pnp transistors, it
is due to holes.
• As the mobility of electrons is more
than the hole, the current is higher in the
npn transistor as compared to the pnp
transistors. Hence, npn transistors are
usually preferred over pnp transistors
• Three different current exist in transistor

• This is true for both npn and pnp

transistor
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Transistor voltage (dc- voltage)
= potential at base B – potential at base E

And

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Doping Levels
• Emitter : Most heavily doped
• Base : Most lightly doped
• Collector : Intermediate doping
• In transistors the foreign material introduced results in the different
regions to become either n-type or p-type material
• In npn: the base is p-type and the collector & emitter n-type
• In pnp: the base is n-type and the collector & emitter is p-type

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Transistor geometry:
• Collector: Largest area
• Base: smallest area
• Transistors can be regarded as two diodes connected back-to-back
• Example: In pnp transistor, there are two diodes with n-type materials
(base) common to both. C

• Since transistors are like diodes, they have potential barrier at their
junction
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BJT configuration
• This is related to investigating a transistor behavior based on its
arrangement
• Configuration simply means arrangement
• This includes analyzing the characteristics of transistor based on
‘where is the input applied ?’ and ‘where is the output taken from ?’
• There are three methods for BJT configuration
a) Common Emitter (CE) Configuration
b) Common Base (CB) Configuration
c) Common Collector (CC) Configuration
• One terminal is always common to both input and output section

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Common Emitter(CE) configuration

• Emitter- Common Terminal to both input and output section

• Resistance connected to base terminal (Input terminal)
• Resistance connected to collector terminal (output terminal)
• Input dc voltage applied to base through
• DC voltage applied to collector through
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Condition (Voltage applied to circuit):
In the above circuit is taken in such a way that
voltage of that BE junction is forward biased.
i.e.
is taken in such a way that CB junction is
reverse biased.
i.e.
In the figure, in the E-region (n-type), there are
large no. of (-) sign. These represents free
electrons.
Base current (): Input current:
Since, the Base emitter junction is forward
biased, i.e. Barrier potential, electrons from
emitter region enter into base region.
The electrons now have two paths to flow.
Either they can flow through the resistor and
into the positive terminal of or, the electrons
can flow into collector.
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Which way will the free electrons
go?
Most will flow into collector. There are
two reasons for this
a) the base is lightly doped - causes
less electron-hole recombination in
the base region, leading to be low.
b) the base area is very thin- this
results the electrons to be very
easily pulled by the positive
terminal of source voltage.
• Both above two reasons favors in very
small current to flow through .
• It can be noted that, about 95% - 99%
electrons flow into collector. Thus giving
rise to collector current
13
Collector current ():
• The electors from the base are pulled by the positive terminal of . The electrons
then flow through the resistor into the +ve terminal of , resulting current .
Conclusion:
In CE configuration, common terminal is Emitter, input terminal B and output
terminal C.
 Input current =
 Output current =
 Output voltage =
The direction of current is opposite
to the electron flow
Hence, the dc current gain is

Here since
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Characteristic curve of CE configuration:
• Input characteristics:
• It is the curve between input current (base
current) and input voltage (base emitter voltage) at
constant collector emitter voltage
• From the characteristics, we observed the
following important points:
• As the input to a transistor in the CE configuration
is between the base to emitter junction, the CE
input characteristics resembles a family of forward
biased diode curves.
• After the cut in voltage the base current increase
rapidly with small increase in base emitter voltage.
• For a fixed value of , decrease as increased. A
larger value of results in a large bias at collector
base PN- junction. This increases the depletion
region and width and reduces the effective width
of the base. Hence, there are fewer recombination
in the base region, reducing the base current

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Output characteristics:
• This characteristics shows the
relation between the collector
current and collector voltage for
various fixed values of , this
characteristics often called collector
characteristics
• From output characteristics we can
see that change in collector emitter
voltage causes the little change in
the collector current for constant
base current
• The output characteristics of CE
configuration consist of three
region: active, saturation and cut-off
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Active region:
The region where the curve are approximately horizontal is the active region. In the
active region, the collector junction is reversed biased. As is increased, reverse bias
increases. This causes depletion region to spread more in base than in collector,
reduction the chances of recombination in the base region. This effect causes
collector current to rise more sharply with increasing in the linear region of the
output characteristics of CE transistor.
Saturation region:
If reduced to a small value such as 0.2V,
then collector base junction becomes
forward biased, since the emitter base
junction is already forward biased by 0.7.
When both the junction are forward biased,
the transistor operates in saturation region,
which is indicated on the output
characteristics. The saturation value of
designated, usually ranges between 0.1V to
0.3V.
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Cutoff region:
• When the input base current is made equal to
zero, the collector current is the reverse leakage
current .The region below = 0 is the cutoff
region of operation for the transistor. In this
region both the junction of the transistor are
reversed biased.
• In the active region, the collector base junction
is reverse biased . For every transistor, there is
limit on the maximum value for this reverse bias
voltage. If this limit is exceeded as shown in
figure, the breakdown occurs in the transistor.
The effect is commonly known as punch
through effect. This large current may damage
the transistor. Hence, in practice, maximum
collector emitter voltage rating should never be
exceeded for the safe operation of the transistor

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 Common base (CB) configuration

and are choosen in such a way that junction BE is forward biased Then current gain,
and BC junction is reversed biased. Here the input terminal is Emitter
and output terminal is collector. And the common terminal is base. Note that
Input current = , and varies from 0.95 to 0.99
Output current =

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Characteristics curve of CB configuration
Input Characteristics
• The input characteristics for the
common base amplifier is as shown
• From this characteristics we observe that
• After the cut in voltage (barrier
potential, normally 0.7 for silicon and
0.3 for Germanium), the emitter current
() increases rapidly with small increase
in the emitter base voltage ().
• It can be observed that there is slight
increase in emitter current () with
increase in this is due to change in the
width of the depletion region in the base
region under reverse biased condition.

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Output characteristics
• The output set will related with output
current () to an output voltage () for various
levels of input current () as shown in figure
• The output characteristic has three basic region:
Active, cutoff and saturation
Active region:
• For the operation in the active region, the
emitter base junction is forward biased while the
collector base junction is reverse biased. In this
region, collector current () is approximately
equal to the emitter current () and transistor
works as an amplifier.
Cut-off region:
• The region below the curve = 0 is known as
cutoff region, where the collector current is
nearly zero and the collector base and emitter
base junction of a transistor are reverse biased.

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Saturation region:
• It is that region of the characteristics which is left of = 0 V and above the = 0. In figure, the
horizontal scale is expanded to clearly show the change in characteristics in the region. Note the
exponential increase in collector current as the voltage increases towards 0V. In this saturation
region, the emitter base and collector base junction are both forward biased.
Punch through effect:
• In the active region, the collector base junction is reverse biased. For every
transistor there is limit on maximum value for this reverse bias voltage.
This maximum reverse bias voltage must be within the maximum safe
limits specified by the manufacture, If this maximum limit is exceeded,
transistor breakdown occurs. Figure below shows the breakdown condition.
• The curves shown in the right side of dotted line is exceeded) represent the
breakdown condition. When collector to base voltage increases, width of
the depletion region at the junction increases. Therefore, when increases
above the , increase in depletion region is such that it penetrates into the
base until it makes contact with emitter base depletion region. This
condition is called 'punch through' or 'reach through' effect. When this
situation occurs, breakdown occurs, i.e. large collector current flows which
destroys the transistor.

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Common collector configuration
• and are chosen in such a way that
BE junction is forward biased and
BC junction is reverse biased
• The input terminal is base
• The output terminal is Emitter
• The common terminal is collector
• Input current = 𝐕 𝐂𝐂
𝐕 𝐁𝐁
• Output current =
• Output voltage = (voltage drop
across )

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Characteristics curve of CC configuration
Input Characteristics
• It is a graph between input base
current () versus input collector
base voltage () at constant
• The common collector input
characteristics are quite different
from either common base or
common emitter input
characteristics. This difference is
due to the fact that the input voltage
is largely determined by the level
of, collector to emitter voltage .
Looking into figure, we can write.
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Input Characteristics
• When collector base junction is reverse
biased and emitter base junction is forward
biased, remains around 0.7V for a silicon
transistor and 0.3V for a germanium
transistor. From the characteristics we can
observed that may be larger then 0 V.
• Consider the characteristics for = 1V.
• At = 100A, = 1.7 V and = 1.7-1 = 0.7V.
• Now suppose is maintained constant at 1V
while the input voltage is decreased to
1.5V, the base emitter voltage then
becomes:
• 1.5-1 =0.5V
• From the characteristics, we can see that as
is reduced from 0.7V to 0.5V, is reduced
from 100A to zero
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Common collector configuration….
Output characteristics
• It is the curve between emitter
current and collector Emitter
voltage at constant base current
• Since is approximately equal to ,
the common collector output
characteristics are practically
similar to those of the common
emitter output characteristics.

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Current amplification factor (): Now we know
The ratio of change in collector current to
the change in emitter current at constant
collector base voltage is known as current
amplification factor.
i.e. at constant Substituting value of ,
Base current amplification factor
():
The ratio of change in collector current () to
the change in base current () is known as ∴and
base current amplification factor It is clear that as approaches unity,
i.e. approaches infinity. In other words, the
Relation between and current gain in common emitter connection
is very high. It is due to this reason that this
A simple relation exists between and . circuit arrangement is used in about 90 to
This can be derived as follows: 95% of all transistor applications.

And
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Comparison of Transistor configuration
Configuration () Common Base (CB) Common Emitter (CE) Common Collector
Characteristics () (CC)
Input Impedance Low about 100 Ω Medium about 800 Ω Very high about 750 KΩ
Output Impedance Very high about 500 KΩ High about 50KΩ High about 50Ω
Current Gain Less than unity but High about 80 High about 100
usually more than 0.9
(about 0.98)
Voltage Gain About 150 About 500 Less than unity
Leakage Current Very small (5A for Ge Very large (500 A for Very Large
and 20A for Si) Ge and 20A for Si)
Output signal Phase In phase with input Reverse In phase with input
Applications For higher frequency For low frequency For impedance
applications applications matching

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Transistor Biasing
• The basic function of transistor is to do amplification.
• The weak signal is given to the base of the transistor and amplified output is obtained in the collector
circuit.
• One important requirement during amplification is that only the magnitude of the signal should increase
and there should be no change in signal shape.
• This increase in magnitude of the signal without any change in shape is known as faithful application.
• In order to achieve this, the base emitter junction (input circuit) of the transistor remains forward biased
and collector base junction (output circuit) always remains reverse biased during all parts of signal. This is
known as Transistor biasing.
• For achieving faithful application following basic conditions must be satisfied
1) Proper zero signal collector current ()
2) Minimum proper base-emitter voltage ()
3) Minimum proper collector emitter voltage ()
• Condition (1) and (2) is for forward biased and condition (3) is for reverse biased condition.
• The proper flow of zero signal collector current and the maintenance of proper collector-emitter voltage
during the passage of signal is known as Transistor biasing

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DC-biasing (BJT- biasing)
• DC-biasing is the application of dc voltage and current to a circuit.
• Transistors are generally used for amplification. These amplification involves two
components in terms of voltage and current
• These component are dc component and ac component
• The dc component can be separately analyzed from ac component only after a certain
dc level is maintained in a circuit containing transistor, ac signal is applied.
• Applying dc sources to any transistor circuit is actually taking the transistor from off
mode to active mode (sleep mode to active mode)
• There are various ways for transistor biasing. This means that there are various ways of
fixing an operating point of transistor
1) Fixed biasing (or base biasing or base resistor) method
2) Emitter biasing method (emitter feedback biasing)
3) Voltage divider biasing method
4) Collector biasing method (collector feedback biasing)
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1. Fixed biasing method + 𝐕 𝐂𝐂 + 𝐕 𝐂𝐂

• is directly connected to and

• For dc- analysis, the network can be isolated +
from the indicated ac levels by replacing the + C
capacitors with an open circuit equivalent B 𝐕 𝐂𝐄
𝐕 𝐁𝐄 E

output signal
Input signal ac

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Fixed biasing method….
• Applying KVL in input loop,
=.
……………………………………....(i)
• Since and are constant then by selecting appropriate vale of ; can be
set
• Applying KVL in output loop,
=.
………………………………(ii)
• The level of determine the magnitude of the
• We also know that in the active region, magnitude of the collector
current is related directly to
i.e. ………………………………………….(iii)
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Graphical analysis (Load line analysis)
From equation (ii),

𝐈𝐁 𝟒
𝐈𝐁 𝟑 Which is similar to equation of straight
𝐈𝐁 𝟐 line Y=mX+C
Y-axis: and X-axis:
𝐈𝐁 𝟏
Slope (m) = and Intercept =

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• since must satisfy equation (i) and
(ii) Hence there will be one fixed
point.
• This is the point where transistor []
operates and is known as Quiscent
point (Q-point) or operating point
or biasing point. 𝐈 𝐂𝐐
• The Q-point depends on which
itself depends on [ from equation
(i) ] and also on . 𝐕 𝐂𝐄𝐐
[]
• The figure shows that by changing ,
and hence Q-point can be change.
• The condition is that and are fixed

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[]
𝐐𝟒
𝐐𝟑 Case I:
𝐐𝟐 then
𝐐𝟏
Q-point shifts Up
Case II:
[] Suppose is taken constant and is
[] varied. The Q-point shifts as:
[]
𝐐𝟑𝐐𝟐𝐐𝟏 Q-point shifts more to left as increases.

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Case III:
If and are held constant and the supply
voltage varied then,
[]
[]
Q-point shift to the left
[]
But slope of equation (ii) remains 𝑸 𝟑𝑸 𝟐𝑸 𝟏
constant.
Slope (m) =
𝐕 𝐂𝐂𝐕 𝐕 𝐂𝐂 𝟏
𝟑 𝐂𝐂 𝟐

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2. Emitter feedback dc biasing method (Emitter biasing)
• The dc bias network of figure below
contains an emitter resistor to improve
the stability level over that of fixed
bias configuration.
𝐈𝐂
• The analysis will be performed by first 𝐈𝐁
examining the base-emitter loop and
then using the results of investigate the
collector-emitter loop

𝐈𝐄

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From base-emitter loop Load Line Analysis:
=.. =
.
Since Choose mA
. ,
Choose Volt ,
……………………(i)
And also we know,
[]
……………………………(ii)
From collector-emitter loop,
=..
= . . since
= ………....………..(iii)
[]
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Comparison between fixed biased and emitter biased

• From above expressions, it is obvious that depends upon . To make less or not
dependent upon , it is necessary to make very large. When becomes very large, it
might take the Q-point to the saturation region which is highly undesirable. Since this
method is also sensitive, Emitter biased method is also not a very good biasing method.
• The fixed biasing method is the simplest and the worst method to bias a transistor for
linear operation because the Q-point is unstable for the temperature change and -
changes when the original transistors are replaced.
• So, we saw that Q-point in fixed bias is not stable and is - dependent.
• It has been found that if we add the emitter resistor to the fixed bias then the Q-point
becomes more stable and the dc bias current (, )and voltage () remains closer to where
they were set by the circuit when outside conditions such as temperature and - Changes.

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 3. Collector feedback dc biasing method (Collector
biasing) or bias with voltage feedback
• The circuit diagram for collector feedback biasing is shown
• The circuit has base resistor connected between transistor’s
collector and base terminals, which significantly improves
bias stability as compared to fixed bias method.
From the circuit we have,

Also, Applying KVL in Collector Emitter loop

• If increases, then the voltage drop across increases , and

hence decreases.
• This decrease in results decrease in and also because .
Thus, the current tends to return towards its original level.
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Now we have, Applying KVL in base From the above relation,
emitter loop depends upon but it is less
sensitive than in emitter-
feedback biasing method.
We know For design we choose

We know,

In terms of

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4. Voltage divider type dc biasing method
• Among the three biasing i.e. fixed biasing, emitter biasing
and voltage divider bias; voltage divider bias circuit is the
most stable for various temperature conditions and of
transistor
• Among them fixed bias has the poorest stability i.e. it(fixed
biasing) is more temperature & dependent
• In the previous bias configuration the bias current and
voltage were a function of the current gain () of the BJT.
• Since is temperature sensitive and the actual value of is
usually not well defined so it would be desirable to develop
a bias circuit that is less dependent or independent of the
BJT
• There are two methods that can be applied to analyze the
voltage divider configuration
a) Exact analysis
b) Approximate analysis

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Inserting the Thevenin equivalent circuit Since , the expression can be reduced to

Which shows that the collector current is almost

Since, so,
independent of
From collector emitter loop,

Since,

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 Using Approximate analysis method

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If then and  The collector to emitter voltage is
determined from KVL,
Since
Where Equivalent resistor between base and
ground for transistor with an emitter resistor since
The condition that will define whether
the approximation approach can be
applied with high accuracay will be

Once is determined, the level of can

be calculated from,
then
also,
Fig: Partial-bias circuit for calculating the approximate base voltage

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 V
BJT as a Switch/inverter
• The application of Transistor is not limited only 𝐑𝐂
to amplification of signal, it can also be used as
switch. 𝐕 𝐨𝐮𝐭
• The areas of operation for a transistor switch are
known as the Saturation Region and the Cut-off
Region
• This means that we can ignore the operating Q-
point biasing and voltage divider circuitry
required for amplification, and use the transistor
as a switch by driving it back and forth between
its “fully-OFF” (cut-off) and “fully-ON”
(saturation) regions
Operating regions:
• The pink shaded area at the bottom of the curves
represents the “Cut-off” region while the blue
area to the left represents the “Saturation” region
of the transistor.
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BJT as a switch-Operating regions:
1. Cut-off Region
 Here the operating conditions of the transistor are zero input base current ( ), zero output collector
current ( ) and maximum collector voltage ( )
 which results in a large depletion layer and no current flowing through the device.
 Therefore the transistor is switched “Fully-OFF”.
 The cut-off characteristics from figure we can define the “cut-off region” or “OFF mode” when
using a bipolar transistor as a switch as being, both junctions reverse biased, 0.7 V and = 0 mA
• The input and Base are grounded ( 0v )
• Base-Emitter voltage VBE < 0.7v
• Base-Emitter junction is reverse biased
• Base-Collector junction is reverse biased
• Transistor is “fully-OFF” ( Cut-off region )
• No Collector current flows ( IC = 0 )
• VOUT = VCE = VCC = ”1″ []
• Transistor operates as an “open switch”

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BJT as a switch-Operating regions:
2. Saturation Region
 Here the transistor will be biased so that the maximum amount of base current is applied, resulting
in maximum collector current resulting in the minimum collector emitter voltage drop which
results in the depletion layer being as small as possible and maximum current flowing through the
transistor. Therefore the transistor is switched “Fully-ON”.
 Then we can define the “saturation region” or “ON mode” when using a bipolar transistor as a
switch as being, both junctions forward biased, 0.7V and = Maximum.

• The input and Base are connected to VCC

• Base-Emitter voltage VBE > 0.7v
• Base-Emitter junction is forward biased
• Base-Collector junction is forward biased
• Transistor is “fully-ON” ( saturation region )
• Max Collector current flows ( IC = )
• VCE = 0 ( ideal saturation )
• VOUT = VCE = ”0″ []
• Transistor operates as a “closed switch”
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BJT as OR gate: V
For low input the circuit can be replaced by open circuit
For High input the circuit can be replaced by closed circuit 𝐑𝟏
 If both transistors A and B have a low (0V) input,
𝐑𝟐
 Transistor OFF state; no current flows ; 𝐐𝟏 𝐐𝟐
 Transistor OFF state; no current flows ;
 Output is low (0V) due to both transistors and YA+B
 If input A is low and B is high
 Transistor OFF state; no current flows; 𝐑𝐄
 Transistor ON state; current flows through ;
 Output is High (5V) due to
 If input A is high and B is low
 Transistor ON state; current flows through ;
 Transistor OFF state; no current flows ;
 Output is High (5V) due to
 If both transistors A and B have a high (5V) input
 Transistor ON state; current flows through ;
 Transistor ON state; current flows through ;
 Output is High (5V) due to both transistors and
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BJT as AND gate:
 If both transistors A and B have a low (0V) input,
 Transistor OFF state; no current flows ;
 Transistor OFF state; no current flows ;
 Output is low (0V) due to both transistors and
 If input A is low and B is high
 Transistor OFF state; no current flows;
 Transistor ON state; active;
 Output is low (0V)
 If input A is high and B is low
 Transistor ON state; active;
 Transistor OFF state; no current flows ;
 Output is low (0V)
 If both transistors A and B have a high (5V) input
 Transistor ON state; active
 Transistor ON state; current flows through ;
 Output is High (5V) due to both transistors and

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 BJT as NOR gate:
NOR = NOT + OR
Inputs output
Remarks

Low (0) Low (0) High (1) Transistor both OFF

Low (0) High (1) Low (0) OFF;
High (1) Low (0) Low (0) ON; FF
High (1) High (1) Low (0) N;

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 BJT as NAND gate:
NAND = NOT + NAND
Inputs output
Remarks

Low (0) Low (0) High (1) Transistor both OFF

Low (0) High (1) Low (0) OFF;
High (1) Low (0) Low (0) ON; FF
High (1) High (1) Low (0) N;

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BJT as NOT gate:
BJT as switch
Inputs Output
Remarks

Low (0) High (1) Transistor OFF mode

High (1) Low (0) Transistor ON mode

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BJT as common emitter amplifier
• The circuit shows that the operation
of BJT as common emitter amplifier
• In using BJT as an amplifier, the
amplifier makes using of active
mode of transistor
• i.e. BE junction forward biased and
CB junction reversed biased. The
proper value of base biasing voltage
and Collector𝐕 biasing
𝐂𝐂 voltage makes
the transistor in active mode
𝐈𝐂
• Let us consider that, the input
voltage is and sinusoidal in nature
𝐕𝐈
𝐈𝐁
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Operation of Common Emitter Amplifier
• When a signal is applied across the emitter-
base junction, the forward bias across this
junction increases during the upper half cycle.
This leads to increase the flow of electrons
from the emitter to a collector through the
base, hence increases the collector current.
The increasing collector current makes more
voltage drops across the collector load
resistor
• The negative half cycle decreases the forward
bias voltage across the emitter-base junction.
The decreasing collector-base voltage
decreases the collector current in the whole
collector resistor . Thus, less voltage drop
across the collector resistor.
• Output voltage
55
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At time t = 0,
When only is applied, then there is some value of
output voltage
At time
For +ve half cycle of input voltage , the output
voltage decreases from its previous constant value to
a lower value
At time
For -ve half cycle of input voltage , the output
voltage increases from its previous constant value to
a higher value
Here voltage amplification ()
The negative sign indicates that for increasing input
voltage, there is decrease in collector voltage
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Differential Amplifier using BJT
• As we can see in the circuit diagram there
are two inputs and two outputs are used.
Here, two separate transistor and are
employed so as to apply separate inputs at
the base of both the transistor.
• The two separate transistors possess
similar characteristics ideally. Common
emitter resistor , common positive supply
and common negative supply is shared
by both the transistors.
• Therefore when two input voltages has
same input, the output voltage is zero
• Now, the thing that comes to our mind is
how can we apply signals at the input and
get the output.
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There are mainly four configurations:
• Dual Input Balanced Output- In this
configuration two inputs are given an
output is taken from both the transistors.
• Dual Input Unbalanced Output- The input
is given to both the transistors but the
output is taken from a single transistor.
• Single Input Balanced Output- Here, by
providing single input we take the output
from two separate transistors.
• Single Input Unbalance Output- It is a
type of configuration in which a single
input is given an output is taken from only
a single transistor.
58
Differential Amplifier
• The most general form of a
differential amplifier is as shown in
the figure
• It has two inputs and
• The output voltage is the voltage
between the collector of the two
transistor
• Ideally the circuit is symmetrical with
identical transistors and collector
resistor
• Therefore when is equal to , the
output voltage is zero
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When >, an output voltage appears with
the polarity as shown
When , an output voltage has the opposite
polarity as shown
In the above figure,

And

A = voltage amplification of the transistor

(Both transistors are assumed to be identical)
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• Say is grounded and has a sinusoidal input,
then • For the –ve half of the input sinusoidal
• For each transistor; signal , output is also negative. Hence is
non inverting terminal
• For the +ve half of the input sinusoidal signal
, the collector voltage decreases below
reference line.

• Here from figure, using the sign convention

• On the other hand terminal is just the
opposite for +ve , the output is –ve , if
is grounded. Hence is inverting terminal
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Field Effect Transistor
• Field effect transistor (FET) is a unipolar device.
• Current conduction takes place only due to one type of carrier electron or
holes.
• This is the major difference between the bipolar junction transistor (BJT) and
field effect transistor (FET).
• BJT takes the conduction in electron and holes.
• The FET is of two types they are junction field effect transistor(JFET) and
metal oxide semiconductor field effect transistor(MOSFET).
• JFET was first introduced by Shockley in 1952.
• JFET is a four terminal device gate, drain and source fourth terminal called as
body terminal always connected to the source.
• JFET is of two types N-channel and P-channel and works only in depletion
mode.
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MOSFET (Metal oxide semiconductor field effect transistor)
• MOSFETs are broken down into depletion type and enhancement type.
• The terms depletion and enhancement define their basic mode of operation, while
the label MOSFET stands for metal-oxide-semiconductor-field-effect-transistor.
• Depending upon the semiconductor used for forming the channel it is named as
‘N-channel' or, 'P-Channel' MOSFET.
MOSFETs

N-Channel
MOSFET

Enhancement type

Depletion type

P-Channel MOSFET

Enhancement type

Depletion type

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MOSFET
• N-Channel MOSFET
The substrate (body) is of P-type
a) enhancement type: Channel has to be created
by the application of gate voltage
b) depletion type : Channel is already present
Fig: Symbol of P-channel
• P-Channel MOSFET
The substrate (body) is of N-type
a) enhancement type : same as above
b) depletion type : Same as above
In short, Enhancement type MOSFET → OFF
until turned ON.
Depletion type MOSFET → ON Until turned
OFF. Fig: Symbol of N-channel
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Enhancement type MOSFET
• We will discuss about the physical structure of a N-
channel enhancement type MOSFET here.
• It is fabricated on a P-type substrate.
• Drain and source regions are highly doped with n-
type material.
• A thin layer of silicon dioxide (S) is grown on the
surface of the substrate covering the area between
the source and drain regions.
• Metal is deposited on top of the oxide layer to form
the gate electrode of the device.
• Four terminals: Gate (G), Drain (D), Source (S) and
body (substrate) (B) are brought out of the device.
• The physical structure of n-channel Enhancement
type MOSFET is shown

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• The substrate forms pn junctions with the source and drain regions
• In normal operation, these pn junctions are kept reversed biased at all times.
• Since, the drain will be at a positive voltage relative to the source, the two pn-junction can
be effectively cut off by simply connecting the substrate terminal to the source terminal.
• For p-channel enhancement MOSFET, the n-type substrate is used and heavily doped p-
type materials are used for Drain and Source.
• Construction of p-channel MOSFET is similar to n-channel enhancement type MOSFET
• In both type of enhancement MOSFET , there is no physical channel between drain and
Source
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Operation with no gate voltage
• With no bias voltage applied to the gate, two back-to-back diodes exist
in series between drain and source.
• One diode is formed by the pn junction between the drain region and
the p-type substrate, and the other diode is formed by the pn junction
between the p-type substrate and the source region.
• These back-to-back diodes prevent current conduction from drain to
source when a voltage is applied.

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Creating a channel for current flow
• In order to create a channel, the drain and source are grounded and a positive voltage
is applied to the gate.
• This gate voltage appears between gate and source which causes holes to be repelled
from the region of the substrate under the gate.
• These holes pushed downward into the substrate, leaving behind a carrier-depletion
region. The depletion region is populated by the bound negative charge associated
with the acceptor atoms.
• The positive gate voltage attracts electrons from the source and drain regions into
the channel region.
• When a sufficient number of electrons accumulate near the surface of the substrate
under the gate, an n region is created, connecting the source and drain regions
• Current flows through the channel if voltage is applied between the source and drain.
• The induced n region thus forms a channel for current flow from drain to source

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Creating a channel for current flow

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Operation with small
• After the creation of a channel, a small positive voltage is applied between drain
and source which causes a current to flow through the induced n-channel.
• Current depends upon the electron density of the channel and the magnitude of .
• Specifically, for , the channel is just induced and the current conducted is still
negligibly small.
• As exceeds , more electrons are attracted into the channel thus the channel depth
is increased.
• The result is a channel of increased conductance or equivalently reduced
resistance.

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Operation with small

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Operation asin increased
• Let be held constant at a value greater than .
• Now the applied voltage appears as a voltage drop across the length of the channel.
• That is, as we travel along the channel from source to drain, the voltage (measured
relative to the source) increases from 0 to .
• Thus the voltage between the gate and points along the channel decreases from at
the source end to () at the drain end.
• Since the channel depth depends on this voltage, we find that the channel is no
longer of uniform depth; rather, the channel will take the tapered form shown in
figure, being deepest at the source end and shallowest a the drain end.
• As is increased, the channel becomes more tapered and its resistance increases
correspondingly.
• Thus the curve does not continue as a straight line but bends as shown

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Operation asin increased

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 curve
• When is increased to the value that reduces the voltage between gate and channel at
the drain end to ,
• i.e., the channel depth at the drain end decreases to almost zero, and the channel is
said to be pinched off.
• Increasing beyond this value has little effect on the channel shape, and the current
through the channel remains constant at the value reached for
• The drain current thus saturates at this value, and the MOSFET is said to have entered
the saturation region of operation.
• For every value of there is a corresponding value of
• The device operates in the saturation region if
• The region of the characteristic obtained for is called the triode region

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 characteristics
Expression for current through Static Characteristics
MOSFET Triode region (Ohmic region)
Here is small
Where i.e. so

Pinch off region (saturation region)

Electron mobility in the induced
channel Here
Oxide capacitance per unit area
Width of the channel (m) At the boundary between triode region
L Length of the channel and pinch off region
Aspect
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Transconductance () of a MOSFET
In field effect transistors, and MOSFETs in Where K is device parameter
particular, transconductance is the change in and given by,
the drain current divided by the small change
in the gate/source voltage with a constant
drain/source voltage.
So Transconductance
Using the Shichman–Hodges model, the
transconductance for the MOSFET can be
expressed as
and
Expression for drain current through
MOSFET

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 characteristics curve
• This curve is also called transfer characteristics curve
• To obtain characteristics we fix the drain to source voltage () and vary the gate to source voltage (). The
characteristics curve is shown
• For enhancement type N MOSFET, when is not sufficiently high there is no channel between Drain and
source
• Hence, no current flows () when .
• At some certain () the channel is created between source & Drain. This voltage is called threshold voltage
or pinch-off voltage (). When is further increased, the drain current () increases for some value of .
• This is tome same for depletion type N-MOSFET except for the fact that threshold voltage is negative for
it.

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Depletion type MOSFET
• It is similar to enhancement in construction but it has a physically implanted
channel between the drain and source for conduction of carriers
• Thus, an n-channel depletion type MOSFET has an n-type silicon region
connecting the source and the drain regions at the top of the p-type substrate.
• Thus, if a voltage is applied between drain and source, a current flows for .
• In other words, there is no need to induce a channel, unlike the case of the
enhancement MOSFET.
• The channel depth and hence, its conductivity can be controlled by in exactly
the same manner as in the enhancement-type device.
• Applying a positive enhances the channel by attracting more electrons into it.
• Here, however, we also can apply a negative , which causes electrons to be
repelled from the channel , and thus , the channel becomes shallower and its
conductivity decreases.
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Depletion type MOSFET….
• The negative is said to deplete the channel of its charge carriers, and
this mode of operation (negative ) is called depletion mode.
• As the magnitude of is increased in the negative direction, a value is
reached at which the channel is completely depleted of charge carriers
and is reduced to zero even though may be still applied.
• This negative value of is the threshold voltage of the n-channel
depletion-type MOSFET and is called pinch-off voltage, or threshold
voltage
• Hence a depletion-type MOSFET can be operated in the enhancement
mode by applying a positive and in the depletion mode by applying
negative .

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Characteristics curve

𝐢 𝐃𝐒𝐒

is the saturation drain source current defined by V and

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• The application of a positive gate-to-source voltage enhances the level
of free carriers in the channel compared to that encountered with V.
• For this reason, the region of positive gate voltages on the drain or
transfer characteristics is often referred to as the “enhancement
region", with the region between cutoff and the saturation level of
referred to as the “depletion region".
Summary
• In depletion type MOSFET, flows for or even negative with variation
in voltage unlike enhancement type
• The voltage applied to the gate terminal to N-MOSFET is negative,
which causes the to decrease and when , becomes zero.

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 MOSFET logic circuit
1. MOSFET as switch
2. MOSFET as NAND gate
3. MOSFET as NOR gate

The terminal on the left The body terminal is The body terminal The circle, which
is the gate, the arrow included between is important in indicates “active-low”
identifies the source, the source and some circuit and input behavior,
and the remaining drain. included between distinguishes PMOS
terminal is the drain. the source and from NMOS
drain.

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MOSFET as switch
• MOSFET as NOT gate
• MOSFET as Inverter
• we will look at using the Enhancement-mode MOSFET as a Switch as these
transistors require a positive gate voltage to turn “ON” and a zero voltage to
turn “OFF” making them easily understood as switches and also easy to
interface with logic gates.
• The operation of the enhancement-mode MOSFET, or e-MOSFET, can best
be described using its I-V characteristics curves shown below.
• When the input voltage, ( ) to the gate of the transistor is zero, the MOSFET
conducts virtually no current and the output voltage ( ) is equal to the supply
voltage .
• So the MOSFET is “OFF” operating within its “cut-off” region.
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MOSFET Characteristics Curve
Cut-off Region
• Here the operating conditions of the transistor are
zero input gate voltage ( VIN ), zero drain
current ID and output voltage VDS = VDD
• Therefore for an enhancement type MOSFET the
conductive channel is closed and the device is
switched “OFF”.
Saturation Region
• In the saturation or linear region, the transistor
will be biased so that the maximum amount of
gate voltage is applied to the device which results
in the channel resistance RDS(on) being as small as
possible with maximum drain current flowing
through the MOSFET switch.
• Therefore for the enhancement type MOSFET the
conductive channel is open and the device is
switched “ON”.
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1. Cut-off Characteristics

 The input and Gate are grounded ( 0V )

 Gate-source voltage less than threshold
voltage VGS < VTH
 MOSFET is “OFF” ( Cut-off region )
 No Drain current flows ( ID = 0 Amps )
 VOUT = VDS = VDD = ”1″
 MOSFET operates as an “open switch”

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2. Saturation Characteristics
The input and Gate are connected to VDD
Gate-source voltage is much greater than
threshold voltage VGS > VTH
MOSFET is “ON” ( saturation region )
Max Drain current flows ( ID = VDD / RL )
VDS = 0V (ideal saturation)
Min channel resistance RDS(on) < 0.1Ω
VOUT = VDS ≅ 0.2V due to RDS(on)
MOSFET operates as a low resistance
“closed switch”

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MOSFET as NAND gate

Inputs output
Remarks

Low (0) Low (0) High (1) ;

D
Low (0) High (1) High (1) OFF;
G
𝐐𝟏
S

High (1) Low (0) High (1) ON; FF D

G
𝐐𝟐
S
High (1) High (1) Low (0) N;

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MOSFET as NOR gate

Inputs output
Remarks

Low (0) Low (0) High (1) OFF

Low (0) High (1) Low (0) OFF; D D

G 𝐐𝟏 G 𝐐𝟐
S S
High (1) Low (0) Low (0) ON; FF

High (1) High (1) Low (0) N;

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Complementary Metal oxide Semiconductor (CMOS)
• The basic building block in CMOS logic
circuits are MOS transistor
• The complementary MOSFET is made by
combining the two MOSFET’S in series.
• The N-MOSFET and the P-MOSFET
• The structure (symbol) for CMOS is
shown
• It has the advantages of a very high input
impedance, fast switching speed, and low
operating power levels, all of which it is
very useful in logic circuits.

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CMOS = NMOS + PMOS
• A MOS is three terminal device that acts like a voltage
controlled resistance.
• An input voltage is applied to one terminal control the
resistance between the remaining two terminals.
• In case of CMOS logic circuits, MOS-transistor is operated
so that its resistance is always eithers very high or very low.
• There are two types of MOS Transistor
1. N-channel (NMOS)
2. P-channel (PMOS)
• As shown in figure MOS transistor has three terminal gate
(G), source (S) & drain (D)
• The terminal on the left is the gate, the arrow identifies the
source, and the remaining terminal is the drain.
• The circle, which indicates “active-low” input behavior,
distinguishes PMOS from NMOS

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• In NMOS transistor, the voltage from gate to source is normally zero or positive.
 If then the resistance from drain to source is very high.
 If the , the is low
• In PMOS transistor is normally zero or negative.
 If then the is very high
 If , the is low
• These characteristics of NMOS & PMOS transistor make then use as a switch in the digital IC
technology
• The gate of the MOS transistor is separated from drain & source by an insulating material with a
very high resistance.
• The voltage applied at the gate terminal creates an electric field that enhances or retards the flow of
current between source & drain. Due to this field effect the MOS transistor is also known as
MOSFET
• Regardless of gate voltage, almost no current flows from the gate to source, or from gate to drain.
The resistance between the gate and the other terminal of the device is extremely high. The small
amount of current that flows across this resistance is very small.
• The NMOS and PMOS transistors are used together in a complementary way to form CMOS logic

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CMOS as switch/inverter circuit (NOT gate)
When input , (Logic 0)
 Both gates are at zero-potential 𝐕 𝐃𝐃
 The input is at relative to the source of the PMOS and at 0V
relative to the source of NMOS
𝐐𝐏 PMOS
 PMOS is turned ON and NMOS is turned OFF
 There is a low impedance path from to the output and very high
impedance path from output to ground
 Output voltage approaches the high level i.e. , which is (Logic
High)
𝐐𝐍 NMOS
When input , (Logic 1)
 Both gates are at potential
 The input is at relative to the source of the NMOS and at 0V
relative to the source of PMOS
 NMOS is turned ON and PMOS is turned OFF
 Output approaches the low level of 0V, i.e. (Logic Low)
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 CMOS as NAND gate
Two NMOS in series & Two PMOS in parallel
Inputs output
Remarks

Low (0) Low (0) High (1) ;

;

Low (0) High (1) High (1) ;

;
( disconnected from )
High (1) Low (0) High (1) ;
;

High (1) High (1) Low (0) ;

;
(disconnected from )

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CMOS as NOR gate
Two PMOS in series & Two NMOS in parallel
Inputs output
Remarks

Low (0) Low (0) High (1) ON

;

Low (0) High (1) Low (0) ON;

OFF;
( disconnected from )
High (1) Low (0) Low (0) OFF;
ON;
( disconnected from )
High (1) High (1) Low (0) ;
ON
(disconnected from )

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