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VLSI Design Flow
• VLSI design flow is nothing but a process to design a chip, it
includes different different steps
DESIGN
IDEA SPECIFICATION RTL CODING &
SIMULAT
ION
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Level of integration Number of active devices
per chip
Small Scale Integration (SSI) Less than 100
Medium Scale Integration (MSI) 100 – 10,000
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Advantages of VLSI
• Reduced size for circuits.
• Increased cost-effectiveness for devices.
• Improved performance in terms of the operating speed.
• Requires less power.
• Higher device reliability.
• Requires less space and promotes miniaturization
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Points Learnt at IIIT
Fabrication Technology
CNC Machine
HDL’s
- Verilog
Simulation
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FABRICATION TECHNOLOGY
• Silicon of extremely high purity
chemically purified then grown into large
crystals Wafers
• crystals are sliced into wafers
• wafer diameter is currently 150mm,
200mm, wafer thickness <1nm
• Wafer is then ready for processing each
wafer will yield many chips
• chip die size varies from about
5mmx5mm to 15mmx15mm
• A whole wafer is processed at a time
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CNC Machine
• Stands for Computer numerical control
• It is a control system in which the data
handling, control sequences, and response to
input is determined by an on-board
computer
• Controlled by G and M codes.
• These are number values and co-ordinates.
• G & M codes are automatically generated
by the computer software.
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What is HDL?
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Types of HDL’S
There are two commonly used HDL’s are:
Verilog –
• Verilog HDL is commonly used in the US industry. Major digital
design companies in INDIA use Verilog HDL as their primary choice.
• most commonly used in the design, verification, and implementation
of digital logic chips.
VHDL-
• VHSIC (Very High Speed Integrated Circuits) hardware description
language.
• Commonly used as a design-entry language for field- programmable
gate arrays. Field-Programmable Gate Array is a type of logic chip
that can be programmed
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A complete Verilog code (Full Adder):
module full_adder_testbench();
reg a,b,c;
wire sum,carry;
full_adder dut(a,b,c,sum,carry);
// Implementation of Full ADDER by using gate level initial begin
Modelling a=0; b=0; c=0;
endmodule
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Thank You
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