SiPhotonics-Talk1 - General - Audience - Ramesh

Light on a Silicon Chip: Opportunity and Applications Dr.
Ramesh Kudalippalliyalil
LIGHT ON A
SILICON CHIP
Opportunities and
Applications
• Dr. Ramesh Kudalippalliyalil

• University of Maryland, College Park-20740
• Maryland, USA
International Online Faculty Development Programme on MICROSYSTEMS DESIGN AND COTROL ENGINEERING | SAINTGITS College of Engineering, Kottayam-686532, Kerala
02/01/2024 1
Light on a Silicon Chip: Opportunity and Applications Dr. Ramesh Kudalippalliyalil
(SILICON) PHOTONICS: What? Why? How?
• Bottlenecks of electronical interconnect

• Will photonics replace electronics?
• Photonics material platforms: Why Silicon?
• Fundamental photonic devices
• Applications
International Online Faculty Development Programme on MICROSYSTEMS DESIGN AND COTROL ENGINEERING | SAINTGITS College of Engineering, Kottayam-686532, Kerala 02/01/2024 2
Covid-19: People Spend More Time in the Digital World
We are working from home. Can the internet handle it?
Increased Traffic: Can Your Device Handle It?
Moor’s law and Beyond

“Number of transistors in an integrated circuit
Gordon Moore
will double in 18 months – 2years, while the
cost of manufacturing them will decrease”
Moor’s law and Beyond

“Number of transistors in an integrated circuit
Gordon Moore
will double in 18 months – 2years, while the
cost of manufacturing them will decrease”
Electrical Interconnect Bottleneck
𝜌𝐿 L Length
𝑅=
𝐻𝑊 W Width
H Hight
S Spacing
ε𝑊 𝐿
𝐶=
𝑆
 Joule heating
 RC time delay
 Bandwidth
 Energy dissipation per bit
Downscaling the minimum

𝜌𝐿 L Length feature size
𝑅=
𝐻𝑊 W Width
H Hight
S Spacing Tighter packaging
ε𝑊 𝐿
𝐶=
𝑆
Parasitic capacitance ↑
Wire resistance ↑
40
Total
30 Signal propagation delay ↑
Delay (ps)
20
Gate
10 Computation delay ↑
0 Interconnect (Al, Cu)
0.7 0.6 0.5 0.4 0.3 0.2 0.1
Line width (μm)
Typical Power Consumption in Data Centers
Datacenter Power Consumption

Lighting (3%)
Power conversion
Network Hardware
(10%)
Server & Storage (26%)

Cooling (50 %)
Optical Interconnects
TRANSMITTER RECEIVER  Very high frequency carrier

 Optics: ~500 THz
Optical Waveguide/ Photo
Laser  Electronics: 10 MHz – 10 GHz
Modulator Optical network detector
 Very short wavelength
 Optics: Visible (~400 – 700 nm)- IR (1.2 – 1.7 μm)
Driver Amplifier  Electronics: 3 cm – 30 m
 Large Photon energy
 Optics: ~2eV
Electrical Electrical
 Electronics: 40 neV- 40 μeV
logic cell logic cell
Electromagnetic Spectrum
TRANSMITTER RECEIVER
Optical Waveguide/ Photo

Laser
Modulator Optical network detector
Driver Amplifier
logic cell logic cell Typical device dimensions
(CMOS, SOI, Glass, Fiber)
Waveguide  Total Internal Reflection
n1
n2<n1 *SOI: Silicon-on-Insulator
Evolution of Optical Interconnects
System
intra/inter-rack Beyond
FIBER OPTICS 2012’s
IC
on-chip
LAN
campus, enterprise
Module
chip-chip
WAN, MAN Since
metro, long-haul 2000’s
Board INTEGRATED OPTICS
module-module
Since Millions of interconnects Billions of interconnects

1990’s (~1m) (< 1 mm)
Since Thousands of interconnects

1980’s (~100 km)
The First Proposed Silicon Based Super Chip in 1993
IBM’s Proposed Ultra-dense Nanophotonics Chip (2008)
R.A, Soref
R.A, Soref, Proceedings of the IEEE , Volume: 81, Issue: 12, Dec 1993
Single-Chip Microprocessor - communicates directly with light !
 70 Million Transistors
 850 Photonic Devices
 Dual Core RISC-V Processor
 1 MB memory bank
 2x11 Electro-optic Transceiver for
Processor and Memory
Chen Sun, et al., Nature Letter, 24 Dec 2015.
Single-Chip Microprocessor - communicates directly with light !
Important Photonic Components

 Lasers (on-chip/off-chip)
 Photodetector (on-chip/off-chip)
 Optical waveguides
 Input/output couplers
 Wavelength filters and (de-)multiplexers
 Optical modulators
 Delay lines
 Optical switches
 Power splitters and combiners
 polarization splitters/rotators and combiners
……
Chen Sun, et al., Nature Letter, 24 Dec 2015.
Dielectric Waveguide – a building block y

-z
x
Basics………
Waveguide core
 Snell’s law, total internal reflection …. Typically < 500 nm (refractive index n1)
Critical angle…. Materials: Si, SiN, Ge, AlN, III-V, ..
¿ 𝜃𝑐 n1
n2<n1
Typically
~ 500 nm - 1 µm
Dielectric Waveguide – a building block Waveguide cladding

(refractive index n2) y
-z
Material: Air/Oxide x
Basics………
Waveguide core
 Maxwell’s equations – modes in a waveguide Materials: Si, SiN, Ge, AlN, III-V, ..
Electric 𝑖 ( 𝑘𝑥 − 𝜔 𝑡 )
Field
𝐸=𝐸0𝑒
2𝜋
𝑘= 𝜔=2 𝜋 𝑓
𝜆/𝑛
2
Wave 21 𝜕
Equation ∇ 𝐸− 2 2
𝐸=0
𝑐 𝜕𝑡
TE and TM Allowed TE , Te modes
mn mn
solutions
Typically
~ 500 nm - 1 µm

-z
Basics………
Waveguide core
 Maxwell’s equations – modes in a waveguide Materials: Si, SiN, Ge, AlN, III-V, ..
TE Mode profiles of a SOI waveguide @ λ=1550 nm

1 um 1 um
500 nm
SiO2 Si SiO2 Si
 Minimum dimension for modal

confinement  λ/2n
 Multiple modes  Intermodal dispersion
 Single mode waveguides are commonly used Typically

~ 500 nm - 1 µm

-z
Basics………
Waveguide core
 Handle substrate is typically Si Typically < 500 nm (refractive index n1)
 Bottom cladding thickness is such that mode Materials: Si, SiN, Ge, AlN, III-V, ..
will not leak into the substrate
tb
Typically
~ 500 nm - 1 µm
Handling base substrate (~ 500 µm )
Material: Si
Waveguide – a building block
Strip waveguide Rib waveguide

Slot waveguide
Silicon
Silicon SiO2
1 um
500 nm
250 nm
SiO2 Si
Waveguide – Basic Fabrication Process Flow
Si (device layer)
SiO2 (bottom cladding)
Si (handle wafer)
Silicon-on-Insulator
Silicon Wafer Production
Graphite/Quartz
Crucible
Direction of pull
+ melted Si
Poly-Silicon
Heater
Raw
Melted Si
material - Si Seed Si single

Sand Crystal Crystal
Graphite/Quartz
Melted Si
Si single Crucible
Crystal
Si Ingot
Si single
Crystal
Waveguide – Basic Fabrication Process Flow

Mask
Si (device layer)
SiO2 (bottom cladding)
Si (handle wafer)
Silicon-on-Insulator Photo-resist coating UV exposure (Patterning)
Resist stripping and cladding Etching Develop the patterns

** Images are not in scale
Why Silicon Photonics
 Si waveguide core
 Availability of the material Si (device layer) nSi ~ 3.5
 High refractive index (n=3.5)
SiO2 (buried oxide) n ~ 1.5
 High Si-SiO2 index contrast
 Smaller footprint devices
Si (handle wafer)
Silicon-on-Insulator
Top cladding (air/oxide)
Waveguide Core
BOX n ~ 1.5
Si (handle wafer)
Typical SOI waveguide

Silicon-on-Insulator Typical SOI waveguide
Top cladding
 Si waveguide core Si (device layer) nSi ~ 3.5 Waveguide Core (air/oxide)
 Availability of the material n ~ 1.5
SiO2 (buried oxide) n ~ 1.5 BOX
 Smaller footprint devices Si (handle wafer) Si (handle wafer)
 Transparent in optical communication window (E g ~ 1.1 eV)

 1.1 μm – 8 μm
Si: absorption spectrum A confined waveguide mode (simulation)
500 nm
500 nm

Silicon-on-Insulator Typical SOI waveguide
Top cladding
 Si waveguide core Si (device layer) nSi ~ 3.5 Waveguide Core (air/oxide)
 Availability of the material n ~ 1.5
SiO2 (buried oxide) n ~ 1.5 BOX
 Smaller footprint devices Si (handle wafer) Si (handle wafer)

 1.1 μm – 8 μm
 CMOS compatible fabrication

 Co-integration with existing CMOS electronic
foundry
 Si, SiN, SiO2, SiGe, Ge can be grown
 Active control of light

 Thermo-optic and Electro-optic
M. Hochber, et. al., ” Nature Photon., vol. 4, pp. 492–494, 2010
 Si waveguide core
 Availability of the material
 Smaller footprint devices

 1.1 μm – 8 μm
 CMOS compatible fabrication

 Co-integration with existing CMOS electronic
foundry
 Si, SiN, SiO2, SiGe, Ge can be grown
 Active control of light

 Thermo-optic and Electro-optic
Effective index can be controlled thermally and
optically M. Hochber, et. al., ” Nature Photon., vol. 4, pp. 492–494, 2010
Fiber – Chip Light Coupling
Edge coupling with cleaved fiber Edge coupling with lensed tip fiber
Edge coupling with tapered fiber
 Fiber core radius~ 10 μm

 Waveguide ~ 200 nm x 500 nm
 Index mismatch (Si ~ 3, Fiber ~ 1.5)
 Loss ~ > 10 dB
Inverse Taper Grating Coupler
Tapered Fiber
Inverse taper + Tapered Fiber Grating Coupler
Fiber @
SiO2 (top oxide)
(B O X)
SiO 2
Si SiO (B
2 O X)
Si
SiO2
160 nm
500 nm Si
100 μm waveguide
Tapered Fiber
Si
Cardenas et. al, IEEE Phot. Tech. Lett, 26 (23), 2014
PN Phase Shifter
Applied bias (V)
𝐧 𝐞𝐟𝐟 ( 𝐕 = 𝟎)=𝐧 𝐞𝐟𝐟 𝟎

Si P N
SiO2 Carrier injection
Si Si
Effective index change
𝑽
+ -
Propagation constant change
P N
SiO2
𝚫 𝜷 =𝟐 𝛑 𝚫 𝐧 𝐞𝐟𝐟 / 𝛌
Si Phase change

𝚫 𝝓 =𝚫 𝜷 𝑳
PN Phase Shifter
Silicon optical modulators, G.T Read, et. al,
Nature Photonics, 4(8), 2010
Figure 1 | Cross-sections of typical device structures implementing the three different mechanisms commonly used to electrically manipulate the
free carrier concentrations in plasma-dispersion-based silicon optical modulators. a, Carrier accumulation; a thin insulating layer of SiO2 is used to
isolate two halves of the waveguide to form a capacitor structure. b, Carrier injection; highly doped p- and n-regions are separated by an ‘intrinsic region’ in
which the waveguide is formed. Forward-biasing the device causes free electrons and holes to be injected into the ‘intrinsic’ waveguide region. c, Carrier
depletion; lightly doped p- and n-type regions abut in the waveguide to form a p–n diode. The depletion area of the diode becomes larger with increasing
reverse bias voltage.
PN Phase Shifter  Mach-Zehnder Modulator
Light out
Vs
Arm1
V
Arm2
Arm1
𝑽
Light in Arm2
+ -
P N
SiO2
Si For more reading Out

Silicon optical modulators, G.T Read, et. al,
Nature Photonics, 4(8), 2010
Ring Resonator
Thermo-Optic Phase Shifter
TRANSMITTER RECEIVER
Optical Photo
Laser Waveguide/Optical network
Modulator detector
Driver Fiber Amplifier
logic cell logic cell
Information input Information output

(eg. voice, video) (eg. speaker, display)
Integrated

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Light on a Silicon Chip: Opportunity and Applications Dr.

• Dr. Ramesh Kudalippalliyalil

(SILICON) PHOTONICS: What? Why? How?

• Bottlenecks of electronical interconnect

Covid-19: People Spend More Time in the Digital World

We are working from home. Can the internet handle it?

Increased Traffic: Can Your Device Handle It?

Moor’s law and Beyond

Moor’s law and Beyond

Electrical Interconnect Bottleneck

Electrical Interconnect Bottleneck

 Energy dissipation per bit

Electrical Interconnect Bottleneck

Downscaling the minimum

Typical Power Consumption in Data Centers

Datacenter Power Consumption

Server & Storage (26%)

TRANSMITTER RECEIVER  Very high frequency carrier

Optical Waveguide/ Photo

Waveguide  Total Internal Reflection

n2<n1 *SOI: Silicon-on-Insulator

Evolution of Optical Interconnects

Since Millions of interconnects Billions of interconnects

Since Thousands of interconnects

The First Proposed Silicon Based Super Chip in 1993

IBM’s Proposed Ultra-dense Nanophotonics Chip (2008)

Single-Chip Microprocessor - communicates directly with light !

Chen Sun, et al., Nature Letter, 24 Dec 2015.

Single-Chip Microprocessor - communicates directly with light !

Important Photonic Components

Chen Sun, et al., Nature Letter, 24 Dec 2015.

Dielectric Waveguide – a building block y

Dielectric Waveguide – a building block Waveguide cladding

Dielectric Waveguide – a building block Waveguide cladding

TE Mode profiles of a SOI waveguide @ λ=1550 nm

 Minimum dimension for modal

 Single mode waveguides are commonly used Typically

Dielectric Waveguide – a building block Waveguide cladding

Waveguide – a building block

Strip waveguide Rib waveguide

Waveguide – Basic Fabrication Process Flow

Silicon Wafer Production

material - Si Seed Si single

Waveguide – Basic Fabrication Process Flow

Silicon-on-Insulator Photo-resist coating UV exposure (Patterning)

Resist stripping and cladding Etching Develop the patterns

Why Silicon Photonics

Top cladding (air/oxide)

Typical SOI waveguide

Why Silicon Photonics

 Transparent in optical communication window (E g ~ 1.1 eV)

Si: absorption spectrum A confined waveguide mode (simulation)

Why Silicon Photonics

 Transparent in optical communication window (E g ~ 1.1 eV)

 CMOS compatible fabrication

 Active control of light

Why Silicon Photonics

 Transparent in optical communication window (E g ~ 1.1 eV)

 CMOS compatible fabrication

 Active control of light

Fiber – Chip Light Coupling

Edge coupling with tapered fiber