Twin-Tub (Twin-Well) CMOS Process

In the conventional p & n-well CMOS process, the doping density of the well region is

typically about one order of magnitude higher than the substrate,

which, among other effects, results in unbalanced drain parasitic. The twin-tub process

avoids this problem.

Twin-Tub
 Twin-Tub technology provides the basis for separate optimization of the nMOS and pMOS

transistors,

thus making it possible for threshold voltage, body effect and the channel

transconductance of both types of transistors to be tuned independently.

Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial

layer on top.
 This epitaxial layer provides the actual substrate on which the n-well and the p-well

are formed

Since two independent doping steps are performed for the creation of the well regions,

the dopant concentrations can be carefully optimized to produce the desired device

characteristics.
 Silicon – On – Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, an insulating substrate to improve

process characteristics such as speed and latch-up susceptibility.

The SOI CMOS technology allows the creation of independent, completely

isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.

 The main advantages of this technology are the higher integration density (because of

the absence of well regions),

complete avoidance of the latch-up problem, and lower parasitic capacitances

compared to the conventional p & n-well or twin-tub CMOS processes.

 A cross-section of nMOS and pMOS devices using SOI process

The SOI CMOS process is considerably more costly than the standard p & n-well CMOS

process.

Yet the improvements of device performance and the absence of latch-up problems can

justify its use, especially for deep-sub-micron devices.

 BiCMOS Technology

Combines Bipolar and CMOS transistors in a single integrated circuit.

 Characteristics of Bipolar Technology

Higher switching speed

Higher current drive per unit area, higher gain

Generally better noise performance and better high frequency characteristics

Improved I/O speed

 Characteristics of CMOS Technology

Lower static power dissipation

Higher noise margins

Higher packing density – lower manufacturing cost per device

High yield with large integrated complex functions

 Combine advantages in BiCMOS Technology

Improved speed over purely

Lower power dissipation (simplifying packaging and board requirements)

Flexible I/Os (i.e., TTL, CMOS or ECL) – BiCMOS technology is well suited for I/O

intensive applications.

High performance

Latch up immunity

Main Disadvantage: Greater Process Complexity

 BiCMOS Inverter

Vdd

Vin T2

T4

Vout

T1

T3
CL

Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor.
 Vin = 0 :

T1 is off. Therefore T3 is non-conducting

T2 ON - supplies current to base of T4

T4 base voltage set to Vdd.

T4 conducts & acts as current source to charge load CL towards Vdd.

Vout rises to Vdd - Vbe (of T4)

 Vin = Vdd :

T2 is off. Therefore T4 is non-conducting.

T1 is on and supplies current to the base of T3

T3 conducts & acts as a current sink to discharge load CL towards 0V.

Vout falls to 0V + VCEsat (of T3)