01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101

1.1.1 Structure & Function of the Processor

01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Specification & Learning Objectives

A Level Specification point description
The arithmetic logic unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory
1.1.1a
Data Register; MDR, Current Instruction Register; CIR). Busses: data, address and control: How this relates to assembly language program.
1.1.1b The fetch-decode-execute cycle, including its effect on registers.
1.1.1c The factors affecting the performance of CPU, clock speed, number of cores, cache.
1.1.1d The use of pipelining in a processors to improve efficiency.
1.1.1e Von Neumann, Harvard and contemporary processor architecture.
 Key question: what are the components of a
01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101
01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110

CPU, and what do they do?

01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Control unit =coordinates all the activities of the cpu and directs the flow of data between the cpu and
other devices. , it also coordinates and communicates with all parts of the cpu
Program counter = holds the address of the next instruction to be executed
Memory address register= holds the address of the current instruction to be fetched
Memory data register= used to temporarily store the data which is read from or written to memory
Current instruction register =holds the current instruction being executed .the cotents of the mdr are copied
to the cir as it is an instruction.
Arithmetic logic unit= this performs the logical and arithmetic operations of the cpu including,AND,OR,NOT
and binary shifts
Accumulator=the results of calculations are temporarily stored here
Busses; address bus = carries memory addresses that identify where the data is being read from or written
to. Data bus:carries the binary 1s and 0s that make up the actual information being transmitted around the
cpu
Control bus:carries command and control signals to and from every other component of the cpu
01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101

Key question: How does a CPU work?

01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Fetch= the program counter is checked ,as it holds the address of the next instruction to be executed.The addressed
store is then copied into the memory address register (mar).the address is then sent along the address bus to main
memory where it waits to receive a signal from the control bus. The control unit then sends a read signal along the
control bus to main memory .The data received by the memory data register from memory data register from
memory now gets copied into the current instruction register. Then the PC is incremented so the address it contains
points to the next instruction points to the next instruction to be executed.

Decode=the instruction held in the current instruction register is now decoded by the decode unit .Th einstruction is
made up of the operand and the opcode the opcode is what to do and the operand is what to do it to.

Execute= the address is sent to the memory address register. The control unit sends a read signal along the control bs
to main memory. The contents stored in memory can now be sent along the data bus to the memory data register
 Key question: How is the performance of a
01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101
01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110

CPU determined?
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Clock speed= this is measured in hertz. It is the number of fetch, decode and execute cycles per second. Modern
processors can process billions of cycles per second this is measured in GHz gigahertz.3.2ghz = 3.2 billion
instructions can be fetched per second

Cache=temporary storage of data and instructions being read to and written from.is faster to access than ram.
Located on or near the cpu. Stores copies of recent instructions and data. We want to avoid getting instructions
and data from memory if we don’t need to as it costs us time.

Number of cores= a core in simple terms is a complete copy of the cpu.Cpus with multiple cores have more power
to run multiple programs at the same time. However doubling the number of cores doesn’t simply double the
overall speed – cpu cores have to communicate with each other which takes time
Many programs are not designed to make use of multiple cores.
 Key question: How can the speed of a
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01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110

processor be increased further?

01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

The speed of a processor can be increased further through pipelining. This is when the cpu is
fetching,decoding,executing different instructions at the same time instead of doing one
instruction at a time. This improves the efficiency however a program with a lot of branching
instructions. May not benefit from pipelining as many instructions will be need to flushed and
removed as they are not needed. Pipelining keeps all portions of the processor occupied and
increases the amount of useful work the processor can do in a given time.
 Key question: Are there other ways to build a
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01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110

processor?
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Von Neumann architecture has a shared memory space for instructions and data .The instructions and
data are stored the same format. It has a single control unit ,processor which follows a linear fetch
decode, execute cycle. Does one instruction at a time. Registers are used as fast access to instructions
and data.

Harvard architecture=instructions and data are stored in separate memory units and each has its own
bus this also means that separate data=instruction buses must also exist.

Contemporary architecture these are more complex than the von Neumann architecture. They are a
mixture of the Harvard and von Neumann architectures as von Neumann is used when working with
data and instructions in main memory but uses Harvard architecture to divide the cache into
instruction cache and data cache
01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101

Typical exam questions

01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Describe the stages of the fetch-decode-execute cycle. [4]

Firstly the address of the next instruction to be executed is copied from the pc to the mar. Then the address is sent along the address
bus to main memory. Then it waits to receive a signal from the control bus. The control unit sends a read signal along the control bus to
main memory ,the data received from the mdr is now copied into the Cir. The pc is incremented .The instruction is now decoded in the
cir then a address is sent to the mar and the contents are sent along the data bus to the mdr.

Increasing the number of cores affects the performance of the CPU. Explain why this increase in performance is not linear. [2]
This increase in performance is not linear because if the cpu doesn’t need to run multiple programs the performance doesn’t change. Some
programs are not designed to make use of multiple cores therefore the multiple cores are not used.

State the purpose of the address bus. [1]

The address bus has a single function to indicate which memory location is being accessed

Name one register other than the PC found in the CPU and describe its purpose. [2]
Alu performs arithmetic and logical operations including AND OR NOT and binary shifts

Explain why the Little Man Computing (LMC) instructions BRA / BRP would cause the contents of the PC to change. [2]
Assessment Target: Overall grade:

Minimum expectations & learning outcomes

 Terms 1-21 from your A Level Key Terminology should be included and underlined.
 You must include at least one diagram which depicts the fetch-decode-execute cycle.
 You must include at least one diagram which shows the direction and connections of the 3 busses.
 You must include at least one diagram which illustrates how the various registers interact during a typical fetch-decode-execute cycle.
 Answer the exam questions.

Feedback
Breadth Depth Presentation Understanding

 All  Link/Create new material  Excellent  Excellent

 Most  Explain/Compare/Contrast  Good  Good

 Some  Describe/Identify  Fair  Fair

 Few  Little shown  Poor  Poor

Comment & action Student response

01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011 01101111 01101101
01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001 01100101 01101110
01100011 01100101 01000001 00101101 01001100 01100101 01110110 01100101 01101100 00100000 01000011
01101111 01101101 01110000 01110101 01110100 01100101 01110010 00100000 01010011 01100011 01101001

Reflection & Revision checklist

Confidence Clarification
Candidates need to have an understanding of the purpose and function of the core components of a processor. Candidates need to understand the role
 and components of the ALU.
 Candidates need to understand the purpose and function or registers within the processor, including the PC, accumulator, MAR, MDR and CIR.
 Candidates need to understand the purpose, function and role of the data, address and control buses in the processor.
 Candidates need to understand how assembly language makes use of registers, and how data and addressed are transferred between registers.
 Candidates need to understand the purpose and stages within the FDE cycle.
Candidates need to understand how and when the registers are used within this cycle, and how and where data and addresses are transmitted to/from
 in each part of this cycle.
Candidates need to understand how the performance of the CPU can be affected by many factors. Candidates need to understand how and why the
 performance is affected by the clock speed, the number of cores and the size and speed of the cache.
Candidates need to have an understanding of the Von Neumann and Harvard architectures. They should be aware of the different approaches the
 architectures take to storing instructions and data in memory and the benefits of each approach.
Candidates will not be asked about specific aspects of “contemporary processor architecture” unless explicitly named in the specification. They may,
 however, be asked to show an awareness of how contemporary processors differ from a pure Von Neumann architecture in more open questions.