AHB PROTOCOL

(Advanced High-performance Bus)

The AHB protocol is a master-slave protocol, which means that there is one
master device and multiple slave devices connected to the bus. The master
device initiates the data transfer by sending a request to the slave device.
The slave device responds to the request by providing the required data.
The AHB protocol supports both burst and non-burst data transfer modes.

FEATURES OF THE AHB PROTOCOL

• Burst transfer
• Addressing modes
• Split transaction
• Error handling
• Single clock edge
• Non tristate implementation
Burst transfer: The AHB protocol supports both burst and non-burst data
transfer modes. The burst transfer mode allows a master device to transfer
multiple data words in a single transfer.

Addressing modes: The AHB protocol supports two addressing modes:

linear and segmented addressing modes. The linear addressing mode is
used for sequential data transfer, while the segmented addressing mode is
used for non-sequential data transfer.

Split transactions: The AHB protocol supports split transactions, which

means that the data transfer can be split into multiple transactions to allow
other master devices to access the bus.
Error handling: The AHB protocol supports error handling, which means
that if an error occurs during the data transfer, the protocol will detect and
report the error.

Non-tristate implementation: The bus master device has full control of

the bus, and the slave devices are responsible for monitoring the bus
ownership signal to determine when they can assert their response signal.

single clock edge: The single clock edge operation is mainly used in
synchronous transfers, where the timing of the data transfer is precisely
controlled by the clock signal. The use of single clock edge operation in
AHB ensures a high-speed and reliable data transfer, making it suitable for
high-performance systems.
AHB BLOCK DIAGRAM
shows a single master AHB system design with the AHB master and three AHB slaves. The
bus interconnect logic consists of one address decoder and a slave-to-master multiplexer.

Decoder
The decoder component decodes the address of each transfer and provides a select signal
for the slave that is involved in the transfer. It also provides a control signal to the
multiplexer. A single centralized decoder is required in all implementations that use two or
more slaves.
Multiplexer
A slave-to-master multiplexer is required to multiplex the read data bus and response
signals from the slaves to the master. The decoder provides control for the multiplexer.
A single centralized multiplexer is required in all implementations that use two or
more slaves.

MASTER INTERFACE:

A master provides address and control information

to initiate read and write operations.
HCLK: This is the system clock signal that provides
the timing reference for all AHB transactions.

HRESETn: This is the active low reset signal that

resets all AHB components to their initial state.

HADDR: This is the address bus that carries the

address of the location being accessed.

HTRANS: This signal specifies the type of transfer

being performed, such as an idle cycle, a burst
transfer, or a single transfer.

HMASTLOCK: This signal indicates that the current

master has locked the bus and will retain ownership
until it releases it.
HSIZE: This signal specifies the size of the transfer.

HBURST: This signal indicates whether the transfer is a single

transfer or a burst transfer.

HPROT: This signal specifies the protection level of the

transaction, such as whether it is a secure or non-secure access.

HREADY: This signal indicates that the slave is ready to

complete the current transaction.

HWRITE: This signal indicates whether the current transfer is

a read or write operation.

HRDATA: This is the data bus that carries the data read from
the addressed location.

HWDATA: This is the data bus that carries the data being
written to the addressed location
SLAVE INTERFACE:

A slave responds to transfers initiated by

masters in the system. The slave uses the
HSELx select signal from the decoder to
control when it responds to a bus transfer.
The completion or extension and the success or
failure of the bus transfer ( slave signals back to
the master).

HRESP: Response signal that indicates the outcome of the transaction .

Bus Interconnection
An interconnect component provides the connection between masters and slaves in a system.
A single master system only requires the use of a Decoder and Multiplexor. A multi-master system requires the use of an
interconnect that provides arbitration and the routing of signals from different masters to the appropriate slaves. This routing
is required for address, control, and write data signaling..

Address decoding
• An address decoder selects which part of a computer receives information on a bus.
• It generates a select signal for each part, or "slave," based on high-order address signals.
• Simplicity and speed are encouraged for address decoding schemes.
• Slaves should only pay attention to signals when a transfer is completing.
• Each slave is assigned a minimum address space of 1KB on a 1KB boundary.
• Masters are designed to avoid crossing these boundaries during a burst transfer to prevent error.
Default slave
If a system design does not contain a filled memory map, then an additional default slave must be implemented
to provide a response when any of the nonexistent address locations are accessed. If a NONSEQUENTIAL or
SEQUENTIAL transfer is attempted to a nonexistent address location, then the default slave provides an
ERROR response. IDLE or BUSY transfers to nonexistent locations result in a zero-wait state OKAY response.

Multiple slave select

A single slave interface is permitted to support multiple slave select, HSELx, signals. Each HSELx signal corresponds to a
different decode of the higher order address bits. This permits a single slave interface to provide multiple logical interfaces,
each with a different location in the system address map. The minimum address space that can be allocated to a
logical interface is 1KB. This approach removes the need for a slave to support the address decode to
differentiate between the logical interfaces. A typical use case for multiple HSELx signals is a peripheral that
has its main data path and control registers at different locations in the address map.
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