Baseband G3.

1 presentation

Product intro
 Digital Unit/Baseband
”G3” ”G3.1”
Streetmacro
6701
”G2”
LTE
DUL 20

Outdoor Radio Processor Radio Processor

DUS 41 6337/6347 6339/6353
Baseband
GSM 6303/6502/
6318
DUG 20
… Baseband RAN
19” 6641/48 Processor
Baseband 5212/16
Baseband 6647/51
WCDMA (GSM/WCDMA/LTE/NR)
6620/30
DUW 30 DUW 41
Baseband
6621/31

Micro
Baseband
2010 2015 6502 2020 2021
RA Baseband Backlog – October 2019
G3.1
KI

Baseband 6641 RAN Processor 6647

BPU 25-50
CBC “G4”

Streetmacro Baseband 6648 Streetmacro RAN Processor 6651

6701 28GHz 6701 39GHz Streetmacro
+ Next Gen
6705 28GHz
802.1x Sup. Streetmacro
802.1x Auth.

2019 2020 2021 2022

19.Q1 19.Q2 19.Q3 19.Q4 20.Q1 20.Q2 20.Q3 20.Q4 21.Q1 21.Q2 21.Q3 21.Q4 22.Q1 22.Q2 22.Q3 22.Q4

KI

Mixed GNSS Sync

Baseband 6621/6631

CBC CBC
Baseband 2/3/4/5G optimized
R638/R608
Radio P. Radio P.
6337 6347 Radio Radio
Processor Processor
4G/5G optimized
6339 6353
RAN Compute portfolio
New New
Baseband Radio
Processor Integrated
6641 solutions
6337

New New Baseband

Baseband Radio
Baseband 6502
5212 / Processor
5216 6648
6347
New Streetmacro
RAN New 6701
Processor Radio Baseband
Processor 6318
6647
6339
Baseband
New
6620 / RAN
6630 Processor New
Radio
6651 Micro
Processor Baseband
Micro
6353 6303 6502
6502
New
Baseband
6631

New
Baseband
6621
 Baseband G3(TTM)

Indoor Baseband 6648 Baseband 6641

Max Throughput: 10-15Gbps/3Gbps Max Throughput: 5-7Gbps DL /2Gbps UL
Mid-band Radio support: 3 sectors 200MHz, 16/8 layers Mid-band Radio support: 3 sectors 100MHz, 16/8 layers
High band support: 3 sectors, 800MHz, 2 layers High band support: 3 sectors, 400MHz, 2 layers

Outdoor Radio Processor 6347 Radio Processor 6337

Max Throughput: 10-15Gbps/3Gbps Max Throughput: 5-7Gbps/2Gbps
Mid-band Radio support: 3 sectors 200MHz, 16/8 layers Mid-band Radio support: 3 sectors 100MHz, 16/8 layers
High band support: 2-3 sectors, 800MHz, 2 layers High band support: 3 sectors, 400MHz, 2 layers
Radio Processor 6353 (MR 105 065-0937/05074) Radio Processor 6339 (MR 105 065-0937/05072)

Outdoor

Radio Processor High Capacity Radio Processor Standard Capacity

Gen 3.1
RAN Compute
HWP requirements, (SW support for this will not be required in G3.1):
Support for 256-bit ciphering och integrity protection.
Throughput: 20Gbps on RAN Processor 6651 and Radio Processor 6353
10Gbps on RAN Processor 6647 and Radio Processor 6339.

Indoor
RAN Processor High Capacity RAN Processor Standard Capacity

RAN Processor 6651 (MR 105 065-0937/05075) RAN Processor 6647 (MR 105 065-0937/05073)
Requirements on G3.1
— HWP requirements, (SW support for this will not be required in G3.1):
— Support for 256-bit ciphering och integrity protection.
— Throughput:
— 20Gbps on RAN Processor 6651 and Radio Processor 6353
— 10Gbps on RAN Processor 6647 and Radio Processor 6339.
— General:
— All six G3.1 HW’s shall have SW support from the same SW release.
— HAL support between G3 and G3.1 is not needed.
— If G3.1 HW shall be Spareparts for G3 HW (in repairflow) will be decided later. G3.1 will however not
support the same SW release.
Baseband G3.1 products
New product names

Old: New:
Baseband 6648 RAN Processor 6651
Baseband 6641 RAN Processor 6647
— Baseband 6621 PRA Q2-21 Radio Processor 6347 Radio Processor 6353
Radio Processor 6337 Radio Processor 6339
— 19” indoor, 15 RI-ports, 1X Lynx 1.1 ASIC
— Baseband 6631 PRA Q2-21
— 19” indoor, 15 RI-ports, 2X Lynx 1.1 ASIC
— RAN Processor 6647
—
PRA Q3-21
19” indoor, 9 RI-ports, 2X Lynx 1.1 ASIC
Kista
— RAN Processor 6651
—
PRA Q3-21
19” indoor, 12 RI-ports, 4X Lynx 1.1 ASIC
CBC
— Radio Processor 6353 PRA Q3-21
— Outdoor, rail mount, 9 RI-ports, 4X Lynx 1.1 ASIC
— Radio Processor 6339 PRA Q3-21
— Outdoor micro BP, pole mount, 8 RI-ports, 2X Lynx 1.1 ASIC
LYNX brief

— LYNX is the next Generation Baseband ASIC

— Successor to the Trinity family
— The Lynx ASIC will be part of Multiple Baseband
Module SAREK:

• 2 Lynx ASIC die

• 1 STRATIX 10 ND4 FPGA die
• 2 “E-tile” Transceiver die
• 22 25G Ethernet links
• 70x55 mm multi-chip package
• 165 W power dissipation
• 3 DDR4 IF on each LYNX
• FIVR voltage regulator on LYNX
What is lynx 1.1

— The purpose of the Lynx 1.1 study is to propose ways of hardening logic originally proposed to reside in the
FPGA part of the Lynx module
— To mitigate design risk and effort
— Reuse as much as possible from Lynx1.0 and Eagle Owl ASIC implementation.
— Reuse large portion of Lynx1.0 physical design.
What is lynx 1.1
E-Tile E-Tile
AIB AIB
ICM

— LYNX with
ND4

FPGA

— Integrated SerDes HBM HBM

BB

— Interconnect (CPRI) ICM ICM

TUA

DLA
— Accelerators BB BB Polar

— DLA Lynx Lynx Lynx1.1

— Polar
— Prepared with interface towards a FPGA (2x25G)
— Possible to use in all products (BB6621/31/41/48 and RP6341/47)
— Monolithic implementation
— TUA integrated inside Lynx1,1
— Arm core inside Lynx1.1
— Lynx1.1 could replace SAREK modules
— BB6641/48 and RP 6341/47 will use SAREK in first release (TTM release).
Baseband 6648 and Radio Processor 6347
Baseline

Radio Processor 6347 Baseband 6648

6*25G
6*25G 3x25G 6*25G

1x1G 4x25G + 1x10G 1x1G 4x25G + 1x10G

3x25G ETH X 4x25G + 1x10G 5x25G 3x25G ETH X 4x25G + 1x10G 5x25G
4x25G 4x25G
2x25 2x25
CPU G CPU G
CPM3 CPM3
E-Tile E-Tile E-Tile E-Tile E-Tile E-Tile E-Tile E-Tile
AIB AIB AIB AIB AIB AIB AIB AIB
ND4 ND4 ND4 ND4

FPGA FPGA FPGA FPGA

HBM HBM HBM HBM HBM HBM HBM HBM

BIM BIM
ICM ICM ICM ICM ICM ICM ICM ICM

BB BB BB BB BB BB BB BB

Lynx Lynx Lynx Lynx Lynx Lynx Lynx Lynx

ETH RI (CPRI/eCPRI)
RAN Processor 6651 and Radio Processor 6353
with Lynx 1.1
Radio Processor 6353
3x25G 6x25G

1x1G
3x25G ETH X
4x25G

2x25G 2x25G 2x25G 2x25G

CPU
1x10G 1x10G 1x10G 1x10G
CPM3

PCIe Gen3x4
ICM ICM ICM ICM
PDCP
Viggen
BB BB BB BB

Lynx1.1 Lynx1.1 Lynx1.1 Lynx1.1

RAN Processor 6651
2x25G 2x25G 2x25G
(4+1) x25G (4+1)x25G (4+1) x25G 6x25G
6x25G
2x10G 2x10G 2x10G 2x10G

1x1G
3x25G ETH X
4x25G

CPU 2x25G 2x25G 2x25G 2x25G

1x10G 1x10G 1x10G 1x10G
CPM3

PCIe Gen3x4
ICM ICM ICM ICM ICM
PDCP
Viggen
PDCP BB BB BB BB BB

TUA ETH RI (CPRI/eCPRI) Lynx1.1 Lynx1.1 Lynx1.1 Lynx1.1

DLA
2x25G 2x25G 2x25G
Polar
BIM (4+1) x25G (4+1)x25G (4+1) x25G
Lynx1.1 2x10G 2x10G 2x10G
2x10G
Baseband 6641 and Radio Processor 6337
Baseline

Radio Processor 6337 Baseband 6641

8*25G 6*25G+3*25G
1x1G (POE)
1x1G
ETH X 2x25G + 1x10G 3x25G ETH X 2x25G + 1x10G
3x25G
4x25G
CPU CPU

CPM3 CPM3
E-Tile E-Tile E-Tile E-Tile
PCIe AIB AIB AIB AIB
PCIe
ND4 xxxxxx
AVst AVst
FPGA FPGA

BIM BIM
HBM HBM HBM HBM

ICM ICM ICM ICM

BB BB BB BB

Lynx Lynx Lynx Lynx

ETH RI (CPRI/eCPRI)
RAN Processor 6647 and Radio Processor 6339
with Lynx 1.1

Radio Processor 6339 RAN Processor 6647

2x25G 6x25G 3x25G 6x25G

1x1G (POE)
1x1G
ETH X 3x25G ETH X
3x25G 4x25G

CPU 1x25G 1x25G CPU 1x25G 1x25G

1x10G 1x10G 1x10G 1x10G
CPM3 CPM3

PCIe Gen3x4 PCIe Gen3x4

ICM ICM ICM ICM
PDCP PDCP
JAS JAS
BB BB BB BB

Lynx1.1 Lynx1.1 Lynx1.1 Lynx1.1

2x25G 2x25G

1x10G 4x25G 1x10G 1x10G 4x25G 1x10G

ICM

PDCP BB
ETH RI (CPRI/eCPRI)
TUA
DLA
Polar
BIM
Lynx1.1
Baseband 6631 and 6621
with Lynx 1.1

Baseband 6621 Baseband 6631

6x25G 9x10G
1x1G 6x25G+ 9x10G
1x1G
3x10G 3x10G
4x10G ETH X 4x10G ETH X

CPU 1x25G CPU 1x25G 1x25G

1x10G 1x10G 1x10G
CPM3 CPM3

PCIe Gen3x2 PCIe Gen3x4

ICM ICM ICM
PDCP PDCP
Flygande JAS
Tunnan BB BB BB

Lynx1.1 Lynx1.1 Lynx1.1

2x25G
1x10G 1x10G 4x25G 1x10G

ICM

PDCP BB
ETH RI (CPRI/eCPRI)
TUA
DLA
Polar
BIM
Lynx1.1
Baseband 6621 block schematic
Baseband 6631 block schematic
RAN Processor 6647 block schematic
RAN Processor 6651/Radio Processor 6353 block schematic
Radio Processor 6339 block schematic
Interfaces
Front panel overview

Baseband 6621

Baseband 6631

Baseband 6641/RAN Processor 6647

Baseband 6648/RAN Processor 6651

Baseband 6630/6620 (for reference)

CPM3

Short introduction in CPM3 as used in BB6648,

BB6641, RP6347, RP6337 and many more…

Fredrik Wildeqvist 2019-04-17

CPM3 vs. CPM2
- Snow Ridge (x86 Atom cores) instead of AXM56xx (ARM)
- SMEM and CMEM merged. Two DDR4 interfaces (MEM0/1)
- LMT 100Mbps Ethernet PHY connected via PCIe instead of SGMII/RGMII
- FPGA Fast Passive Parallel (x8) configuration via GPIOs. CvP is still used via PCIe.
CPM2 used loading via a SPI interface (PS).
- New SerDes for Ethernet; 25G Eth for IDL, TN and internal.
- New debug interfaces. DCI via USB3
- New SPI boot. More memory and higher frequency. Quad mode, 48MHz.
- Dual SPI boot Flash. For update of FW in field with backup boot.
- UART interface to DCDC controller (PM). SPI was used in CPM2.
- SVID interface to power controller
- MTC is implemented in SNR using GPIOs.
- LEDs are controlled via registers in the PM (DCDC).
- USB Type-C at front.
CPM3 block diagram 25MHz
Platform Snow Ridge 8c/12c/16c
reset XTAL JTAG CPU PTC
Reset
RESET JTAG PCH
logic
PTC
SPI Boot SPI-0 USB2 USB3
Flash SPI-1 USB3 Mux TypeC
2/3/4 clusters
PCIe x1 TypeC
LMT PHY/MAC SMB-L ctrl.
RS232 UART-0 x4 cluster VPP *)
Intel Atom Prod. dependant
UART-1
TNT cores x2 PCIe Gen 3*)
DC/DC PCIe x2
x4 PCIe Gen 3*)
PCIe x4 FPGA
SVID *) CvP to AvSt
PCIe x1 x1 PCIe Gen 1 Krypto...
Config. x8
DDR4 x64 CH0 GPIO<X..0>
DDR4ECC
x64 DDR4
PGOOD +8-bit **) - IRQs (DCDC + PM + ...)
+8-bit ECC CH1 MEM.CTRL USB2 eUSB3 - Reset...

CLK_REF_SYNCE USB3 Flash drive

TUM From BBM-0 or BBM-1
TIME_REF TIME_SYNC
To BBM-0 and BBM-1
To FPGA/TUF CLK_SYNCE x2 ONE_PPS
I2C to DCI Debug/USB3@prod
USB3
QSFP&SFP28 PTC
I2C to Retimer USB2
MDIO to PHY RTC 32.768kHz
4x25G Eth ETH X ***)
IDL RT
:Lane :Lane BBM-0
2x25G Eth
PHYx:<> PHYx:<> Lynx
TN RT
25G Eth PHYx:<> 2x25G Eth BBM-0
PHYx:<>

MACsec
25G Eth Lynx
TN RT PHYx:<> BBM-1
PHYx:<> 2x25G Eth
25G Eth PHYx:<> Lynx
TN 2x25G Eth BBM-1
RT PHYx:<> PHYx:<> Lynx
MDIO
:Lane 10G Eth BBM-0
TN PHY
1G Eth PHY1:<> PHY1:<> FPGA
RJ45
10G Eth BBM-1
PHY1:<> PHY1:<>
FPGA
RT=Retimer *)
*) Product dependant PHY0[0:7] (25G, MACsec) 16c/12c | (10G, MACsec) in 8c
**) Not available in SNR 8c PHY1[0:3] (10G) 16c
***) The ETH support and usage is PHY1[4:7] (25G, MACsec) 16c/12c/8c
dependent on type of SNR and DU. PHY2[0:3] (25G, MACsec) 16c
 Snow Ridge
SNR 8c/12c/16c
Number of Cores

North die

South
die

North: CPU & NAC

South: PCH (or CDF; CederFork)

Ericsson Internal | 2018-02-21

RAN P6651 Floorplan

BIM Lynx Lynx

DDR4
SNR
Lynx Lynx

RI ABC RI DEF RI GHJ RI KLM TN BCD

TN A
USB&LMT

SYNC&TN E
Ericsson Internal | 2018-02-21 ALA1&ALA2
BIM

The functions overview

— Fan tray support,
— External Alarms,
— Retimers/SFP+ control for RI ports,
— F-Sync parts from TUF
— TUA backup including SPI, TUF SPI et cetera
— I2C for configuration of Lynx, SWRI
— Generic I/O pins et cetera, SWRI
— PCIe, new design block
— HWP for 256-bit ciphering och integrity protection

Ericsson Internal | 2018-02-21

USB3

We use three USB3 interfaces (USB2 included).

- eUSB3 Drive. NAND Flash storage. 8GB (same as previous products)
- One USB3/2 interface at PTC connector.
- USB Type-C connector at front.

Ericsson Internal | 2018-02-21

LMT interface

— At front of DU. RS232 and 100Mbit Eth. (+FSync)

— Much like previous generation.

New is the i210 LMT PHY for Ethernet.

Attached to PCIe on SNR.
Contains a internal NonVolatile Memory. More like a OTP (One Time Programmable) memory.
I.e. we can only update it a limited number of times. E.g. giving a new MAC address.
25MHz XTAL

Ericsson Internal | 2018-02-21

 Use Case

RP6651 HW requirement Capacity Users1

Bearers2
Total user bit rate DL (Gbps)
10k

50k
6648:10(normal) 15(demo)
6651: 15(normal) 20(demo)

Building
Physical characteristics:
practice Total user bit rate UL (Gbps) 6648: 3 (normal) 0,75 (demo)
Width: max 449 mm (19 inch)
6651: 3 (normal) 1 (demo)
Height: max 44 mm (1U)
Depth: max 352 mm Single user DL peak rate (Gbps) 6648:10(normal) 15(demo)

Weight: ~8kgs 6651: 15(normal) 20(demo)

Note, this is a preliminary weight figure, but the intention

shall be to build as light as possible. Single user UL peak rate (Gbps) 6648: 3 (normal) 0,75 (demo)
6651: 3 (normal) 1 (demo)
Power feed:
-48VDC, DC-C and DC-I power feeding without external
DC/DC converter IPSec single SA capacity (Gbps) 6648: 12/3,6
6651: 18/3,6
Fan unit allowed. If used it shall be possible to replace Packet and radio control processing
at site and during operation
PDCP DL (Mpps) (dimensioning case is “S1+33%Xn”) 6648: 1.3/1.0
6651: 1.9/1.4
Environmental conditions:
PDCP UL (Mpps) (dimensioning case is “S1+33%Xn”) 6648: 0.9/0.1
Indoor operation acc. to ref. [1] 6651: 1.2/0.2

Installation scenarios: TN (DL) (Mpps) (dimensioning case is “full S1, artificial scenario) 6648: 1.8/1.0
6651: 2.6/1.4
19” rack, RBS 6000 cabinet TM space TN (UL) (Mpps) (dimensioning case is “full S1, artificial scenario) 6648: 1.0/0.1
6651: 1.3/0.2
Power consumption:
NR High Band C1 Terminating bandwidth 9600 MHz
Typical: <200W NR Mid Band C2 Terminating bandwidth 96003 MHz
Max: <300W
NR Low Band C1 Terminating bandwidth 4800 MHz
Measured/calculated acc to ref. [2] Mixed Mode Baseband operation NR4+LTE

Interfaces: LTE capacity (Low band C1 Antenna BW and Mid Band C2 Terminating 4800MHz
BW)
Radio I/F: 12x SFP28 electrical or optical LTE Capacity (Mid band C2 Terminating BW) 9600MHz

IDL/TN: 1x QSFP28, electrical or optical Packet processing infrastructure

3x 1/10/25Gbps + 1x 1Gbps
Transport network interfaces / Inter BPU interfaces (IDL)
IDL/TN: 3x SFP28, electrical or optical RJ45 + 4x 10/25Gbps

/TN: 1x RJ45 Radio interfaces (C1 and C2)

Ericsson Internal | 2018-02-21
12 ports total.
C1 support:
12 ports, 2,5, 4,9, 9,8, 10,1 and
Sync: 1x RJ45 Assumption is no C1 forwarding.
24,3Gbps
Assumption is no C2 forwarding. C2 support:
External alarms: 8x alarms to be supported
12 ports 10/25Gbps
LMT: 1x port
Power connector: 2x ports 1 One air interface ciphering SA per user
2 Bearer modification rate = Bearers/600 modifications/s
External I/O: USB-connector, temporarily connected 3 Requires utilization of 25G interfaces which current mmW Radio portfolio doesn’t have
mass storage device 4 NR here implies current variants: Low Band (LB) Mid Band (MB) and High Band (HB)
RP6651 Exploded view

Heat
spreader -
Cu

Ericsson Internal | 2018-02-21

RP6353 Exploded view

Ericsson Internal | 2018-02-21

RP6339 Exploded view

Ericsson Internal | 2018-02-21