Improvement of the Performance of a

Wireless Transmitter Based on Efficient RF

Power Amplifier

PhD Student Firas Mohammed Ali Al-Raie

Supervised by

Assistant Prof. Dr. Mahmuod Hamza Al-Muifraje

1
Introduction
• The RF power amplifier is the final stage of a solid-state radio transmitter.
• The efficiency of the whole transmitter depends on the efficiency of the power
amplifier as it is the most power-hungry stage in the radio system.
• The battery size and life of the transmitter depend, to a large extent, on the
efficiency of the power amplifier.

Block Diagram of a Typical Modern SDR Transmitter

2
 Basic RF Power Amplifier Design Parameters

Pout
DC to RF Efficiency   100%
Pdc
Pout  Pin
Power Added Efficiency ( PAE )   100%
Pdc
Pout
Power Gain (G p ) 
Pin

G p (dB )  Pout (dBm)  Pin (dBm)

Input Re turn Loss (dB)  20 log in

High Efficiency RF Power Amplifiers are designed to maximize DC to RF

efficiency and output saturated power with minimal device power dissipation.

3
 Classification of RF Amplifiers

Performance Circuit
Bandwidth Signal Level
Construction

High Gain
Narrow Band Small Signal Amplifiers
Amplifiers Amplifiers Microstrip
Broadband Low Noise Lines
Large Signal Amplifiers
Amplifiers
Amplifiers Lumped
Elements
High Power
Amplifiers

4
 Block Diagram of the RF Power Amplifier

• The input matching network is used to match the transistor input impedance with
the source impedance to increase power gain and minimize reflected power.

• The output matching network is used present the optimum load impedance at the
transistor output for maximum efficiency and output power.

• The biasing circuit is used to maintain a constant Q-point for the RF transistor and
should be isolated properly from the RF circuit.
5
Differences between Small Signal and Large Signal Power
Amplifiers
Small-Signal RF Transistor
Characterization

Small Signal Linear Circuit

S-Parameters Model

Difficulty of
Ease of Measurements Parameter
Measurements
High Accuracy of Modeling
Lower Accuracy
Useful in Frequency
Domain Simulation Useful in Time
Domain
Simulation

6
 Large Signal RF Transistor
Characterization

Load/Source Pull Non-linear Large

Large-Signal
Measurement Signal Circuit Model
S-Parameters
(Determination of (Contains nonlinear
(Parameters vary with
optimum load and source elements whose
signal power level as well
impedances using values depend on
as with frequency)
input/output tuners) voltage levels)

7
• Small Signal RF Amplifiers operate on a small linear portion of the transistor
characteristic, while Power Amplifiers operate on large and usually nonlinear
portion of the transistor characteristic.

• Small signal high-gain RF amplifiers are usually designed for simultaneous

conjugate matching at input and output ports.

8
Power Amplifier Matching Considerations
• In order to obtain maximum output power, typically the power amplifier is
not conjugately matched. Instead, the load network is designed such that the
amplifier has the correct voltage and current at the transistor output to
deliver the required power.

Comparison between maximum gain matching

and maximum output power matching
9
 RF Power Devices Used in Power Amplifiers
1. Bipolar Junction Transistors (BJTs), Simplest bias circuit design.
2. Laterally Diffused MOSFETs (LDMOSFETs), high thermal conductivity.
3. GaN High-Electron Mobility Transistors (HEMTs), high breakdown voltages due to
high band-gap energy and high power density.

10
GaN RF Power
Transistor
Structure

Small-Signal Equivalent Circuit for HEMT 11

HEMT Large Signal Model

12
 Classification of RF Power Amplifiers

Continuous Switching Harmonically

Mode Mode Tuned

Class A Class AB Class D Class E Class F Class F-1 Class J

Class B Class C

• In continuous mode power amplifiers, the transistor is operating as a

current source.
• In switching mode power amplifiers, the transistor is operating as a switch.
• In harmonic-tuned power amplifiers the transistor is operating as a
possibly saturated (or over-driven) current source.

13
 Class A
Output voltage vin  Vb  Vin cost
i v
- input cosine voltage
2Vcc
V i  I cq  I cos t - output cosine current
v R
Vcc v  Vcc  V cost
vin Vcc - output cosine current
t
0  2 Pdc  I cqVcc- -DC output power
Transfer characteristic
i i
Pout  0.5 IV - fundamental output
power
I
Pout 1 I V 1 I
    
Pdc 2 I cq Vcc 2 I cq
Icq
Vb - collector efficiency
vin t
0 Vp 0  2
  V / Vcc - voltage peak factor
Vin Output current
For ideal condition of zero I / I cq  1

t
saturation voltage when  1
Input voltage   0.5 - maximum collector efficiency in Class A
14
 Class B

Output voltage
vin  Vb  Vin cost
i i1 v - input cosine voltage
2Vcc
c  I cq  I cost ,    t  
V i  
R  0,   t  2  
Vcc
- output current
vin Vcc conduction angle 2
t indicates its duty cycle
0  2
Transfer characteristic
For moment with zero current
i
i i  0  I cq  I cos

I I cq
cos  
I
0 vin
0 2
t

Vin  = 90
Output current
i  I cos t  cos 

t For moment with maximum current

Input voltage
i  I max  I  1  cos 
15
Class-A,-B,-AB, -C operation modes

I cq   I cos - quiescent current as function of half-conduction angle 

• when  > 90  cos  < 0  Icq > 0 - Class AB operation mode

• when  = 90  cos  = 0  Icq = 0 - Class B operation mode

• when  < 90  cos  > 0  Icq < 0 - Class C operation mode

i  I 0  I1cost  I 2 cos 2t  I 3cos 3t   - Fourier series


1
where I0 
2  I cost

 cos  dt  I 0 - dc component

1
I1 
  I cost

 cos  cost dt  I 1 - fundamental component

1 1
where 0  sin   cos , 1    sin cos  - current
  coefficients
P1 1 I1 1 1
      - collector efficiency
P0 2 I0 2 0

When  = 90 and  1  - maximum collector

   0.785
4 efficiency in Class B 16
Over-driven class-B RF Power Amplifier

i Transfer characteristic i Output current

K
Imax

L Imax

M P
0 v
Vcc 2Vcc 0 
t

 = 90

For increased input voltage

Input voltage
amplitude:
• operation in saturation, active, and cut-off
t regions
• load line represents broken line with three sections:
KL- saturation region (depression in collector current waveform)
KM – active region
MP – cut-off region
17
 Class E RF Power Amplifier with shunt capacitance
L L0 C0 In Class-E power amplifiers,
transistor operates as on-to-off
RFC R
switch and ideal shapes of current
C
Vcc
and voltage waveforms do not
vin
Vbe
overlap simultaneously resulting in
100% efficiency
Class-E power amplifiers are analyzed in time domain as their current and
voltage waveforms contain harmonics having specified different phase
delays depending on load network configuration

Basic circuit of Class-E power amplifier with shunt capacitance consists of

series inductance L, capacitor C shunting transistor, series fundamentally tuned
L0C0 resonant circuit, RF choke to supply dc current and load R

Shunt capacitor C can represent intrinsic device output capacitance and

external circuit capacitance
Active device is considered as ideal switch to provide instantaneous device
switching between its on-state and off-state operation conditions

18
 Class E RF Power Amplifier with shunt capacitance
RFC
L L0 C0 Optimum ideal voltage
conditions across switch:
I0 i iC iR
Vcc
v C R vt   t  2  0

dvt 
 0
dt t  2
Idealized assumptions for analysis:
• transistor has zero saturation voltage, zero on-resistance, infinite off-
resistance and its switching action is instantaneous and lossless
• total shunt capacitance is assumed to be linear
• RF choke allows only dc current and has no resistance
• loaded quality factor QL of series fundamentally tuned resonant L0C0 circuit is
infinite to provide pure sinusoidal current flowing into load
• reactive elements in load network are lossless
• for optimum operation 50% duty cycle is used

iR  t   I R sin t    - sinusoidal current flowing into load

19
 Class E RF Power Amplifier with shunt capacitance
RFC
L L0 C0 Optimum ideal voltage
conditions across switch:
I0 i iC iR
Vcc
v C R
vt   t  2  0

dvt 
 0
dt t  2
dvt 
0  t   - switch is on  iC t   C  0
dt
 i t   I 0  I R sin t   or using initial condition i 0   0

when I 0   I R sin  i t   I R  sin t     sin 

  t  2 - switch is off  i t   0  iС t   I 0  I R sin t   

t
1 IR
v t     cost     cos   t   sin  
C 
 i  t d t  
C
С

From first I0  3  
optimum condition: v t    t   cos t  sin t 
C  2 2 
20
 Class E RF Power Amplifier with shunt capacitance
iR/I0 Optimum load-network parameters :
1.5

1 R
Load 0.5 L  1.1525 - series inductance
current 0 
60 120 180 240 300 t
-0.5
1
-1
C  0.1836 - shunt capacitance
-1.5
R
v/Vcc Vcc2
3.5 R  0.5768 - load resistance
3 Pout
Collector 2.5

voltage
2
1.5
Optimum phase angle at fundamental
1 seen by switch :
0.5
0  
 
1  L  CR
0 60 120 180 240 300 t
  tan    tan 1
   35.945
i/I0  R   1  L CR 
 
2.5  R 
I1 IR
Collector 2 L
1.5
current 1

0.5 V1
C R
0

0 60 120 180 240 300 t

21
 Harmonic Tuned RF Power Amplifiers

F. H. Raab, “Class-E, class-C, and class-F power amplifiers based upon a finite number of
harmonics,” IEEE Trans. Microwave Theory & Tech., vol. 49, no. 8, pp. 1462–1468, Aug.
2001. 22
 Class F RF Power Amplifier
• In class F power amplifiers, the device voltage contains only odd harmonics
while the device current contains even harmonics in addition to the fundamental
component. This can be done by using multi-harmonic resonators.

• The device terminal voltage is shaped as a square wave, and the device current
is shaped as half-sinusoidal wave with 180o phase-shift between them to
minimize overlapping and power dissipation. This will maximize efficiency.

23
 Class F PA: Idealized Operation
I max
Ideal current waveform
I1  - fundamental current component
2
4 Vcc
i V1  - fundamental voltage component

Imax I max
I dc  - dc current component

1 V I
Idc Pout  V1 I1  cc max - fundamental output power
2 
0  t
2 Pdc  Vcc I dc - dc supply power
Ideal voltage waveform Pout
   100% - collector/drain efficiency
v Pdc
2Vcc
Harmonic impedance conditions:
Vcc 8 Vcc 8 V
Z 1  R1   2 cc
 I max  I dc
0  2 t Zn  0 for even n
Zn   for odd n
24
 Class F with quarter-wave transmission line

rectangular collector voltage half-sine collector current

consisting of fundamental and consisting of fundamental and even
odd harmonics harmonics
v/Vcc
i/Idc
2.0
3.0
1.5
2.0
1.0

0.5
1.0

0 0
0 60 120 180 240 300 t,  0 60 120 180 240 300 t, 

Vdd

 quarterwave transmission
line as impedance transformer
Z0, /4

Z 02
R 
C0 L0 RL
RL
vin R
 sinusoidal current:
shunt L0C0 circuit
F. H. Raab, “FET Power Amplifier Boosts Transmitter Efficiency,”
tuned to fundamental
Electronics, vol. 49, pp. 122-126, June 1976.
25
 Class F PA with Finite Number of Harmonics
Vcc
Cby Load network
v n = 1, 3

Vdc L2 C2 ImYL(0) = 0
ImYL(20) = 
ImYL(30) = 0
0  2 t L1

i 50 Ω
n = 1, 2 Matching
circuit
Cout with high
YL impedances
at harmonics

Idc
1   2 L2 C 2
ImYL   C out 
L1 1   2 L2 C 2   L2
0  2 t
Circuit parameters
Fourier voltage and current waveforms 1 5 12
with third and second harmonics. L1  L2  L1 C2  Cout
602Cout 3 5
26
 Class F PA with even current and third voltage harmonic peaking
Harmonic impedance conditions at
Vcc collector (drain):
Cby

ImYL(0) = 0
ImYL(2n0) = 
1 3
ImYL(30) = 0
2
Matching
circuit
Cout with high
impedances
50 Ω
YL
at harmonics
Circuit parameters:

 
1  3 
Transmission Line Load Network Design 2 6

1  1 
 2  tan 
1


3  3Z 0 2 C out 

27
 v
i
n = 1, 3, 5
n = 1, 2, 4

Vdc

Idc

0  2 t
0  2 t

Fourier voltage and current waveforms with five harmonics.

Maximum Theoretical Efficiency for Class F PA with Finite No. of Harmonics 28

 Inverse Class F Power Amplifier
• In inverse class F power amplifiers, the device voltage contains only even
harmonics while the device current contains odd harmonics in addition to the
fundamental component. This can be done by using multi-harmonic resonators.

• The device terminal voltage is shaped as a half-sinusoidal wave, and the device
current is shaped as a square wave with 180o phase-shift between them to
minimize overlapping and power dissipation. This will maximize efficiency.

29
 Inverse Class F PA with idealized operation mode

Dual to conventional Class F

4 I dc
with mutually interchanged I1  - fundamental current
current and voltage 
Vmax 
waveforms V1   Vcc - fundamental voltage
2 2
i 1 V I
2Idc Pout  V1 I 1  max dc - fundamental output power
2 
V I
Pdc  Vcc I dc  max dc - dc output power
Idc 
Pout
   100% - ideal collector/drain efficiency
0 2
t Pdc

v Harmonic impedance conditions:

Vmax  Vmax  2 Vcc  Vcc2

2
Z 1  R1   
8 I dc 8 I dc 8 Pout
Vcc
Zn   for even n
t Zn  0 for odd n
0  2
30
 Inverse Class-F with quarterwave transmission line
Vdd
 zero impedances at odd
harmonic components
Z0, /4 L0 C0

 device is driven to operate as

switch
vin RL
R1

 sinusoidal current:
RFC f0 shunt L0C0 circuit tuned to
fundamental
Vdd 3f0 5f0 (2n + 1) f0 RL

 quarter-wave transmission
line as impedance transformer
 quarter-wave transmission line as infinite
set of series resonant circuits Z 02
R1 
RL

Kazimierczuk M. K., “A new concept of class F tuned power amplifier”, Proceedings of

the 27th Midwest Circuits and Systems Symposium, 1984, pp. 425428.
31
Inverse Class F with second harmonic current and third harmonic voltage
components
Load network
Harmonic impedance conditions at collector/drain:
Vdd
Cby
ImYL(0) = 0
ImYL(20) = 0
ImYL(30) = 
1 Zo1 3 Zo3
1 i n = 1, 3

Zo2, 2
Matching
circuit Idc
Cout with high 50 Ω
YL impedances
at harmonics
0  2 t

Circuit parameters: v
n = 1, 2

 
1  3 
3 4
 1  
1 Vdc

1 1 
 2  tan  2 Z 0 2C out   
2  3   0  2 t

32
 Optimum load-network resistances at fundamental
frequency for different classes of operation

Class B : Vcc Vcc2

R ( B)  
I1 2 Pout
4 Vcc 4
Class F : R ( F)   R (B)
 I1 

 Vcc 2 
Inverse Class F : R ( invF)
  R (F)
 R (B)
2 I1 8 2

Load resistance in inverse Class F is the Less impedance

highest (1.6 times greater than in Class B) transformation ratio and
easier matching procedure

33
 Class J RF Power Amplifier

Class J PA is a modified version of class B PA with the device current containing

only two-harmonics and device voltage multiplied by a phase-shift term

Cripps, S. C., RF Power Amplifiers for Wireless Communications, Artech House,

2nd ed., 2006.
34
 - Current and voltage
waveforms for Class B PA

- Current and voltage

waveforms for Class J PA

Fundamental and second harmonic impedances for the Class j PA

35
Device Voltage and Current Waveforms of the Class J PA with different values of α and β

Features:
1- Better Linearity
2- Broader Bandwidth

Limitations:
Efficiency comparable to that of Class-B (Lower than that of Class F)

36
 Classification of RF Power Amplifiers According to the Type
of Modulated Signals

Nonlinear PAs for Linear Pas for variable-

constant-amplitude signals amplitude signals
(GSM, Bluetooth) (WCDMA, QAM, OFDM)

Class AB Class A
Class F -1 Class J
Class E Class F

37
 Research Time Table
• Building solid background about the subject of high efficiency RF/Microwave RF
power amplifiers after reading some textbooks (2 months).
• Literature review to identify the various techniques used in switching mode RF
power amplifiers (3 months).
• Practicing with the computer aided design program ADS 2016 with its full
simulation capabilities (1 month).
• Developing the proposed design technique and deriving the necessary equations
for circuit modeling and technique verification (3 months).
• Applying the proposed technique for some RF power amplifier circuits after
determining the operating frequency, power level, and type of RF power
transistors. The performance parameters of the circuits should be verified using
computer simulation (1 month).
• Assembling the required components and instruments to validate the practical
implementation of the circuits (1 month).
• Practical circuit implementation and testing including circuit tuning and
modification (2 months).
• Writing the thesis and submitting it (3 months).

38
Literature Review

 Many research works are concerned with the mathematical analysis of class F
and inverse class F RF PAs to evaluate the conditions for maximum efficiency and
output power based on some assumptions. This depends mainly on the relative
amplitude of the harmonic components and the fundamental component with
respect to the power supply voltage.

 The variation of amplifier performance with conduction angle of the device’s

current is also demonstrated by several works.

In addition, the effect of improper phase of the harmonics with respect to the
fundament frequency component is also treated by some works.

39
 Many research works have been carried out to study the effect of harmonic
termination and peaking at the input port of the power amplifier. It has been
verified that the suppression of the second harmonic component at the gate of the
MOSFET can significantly increase the efficiency of the class F PA, while the injection
of the source second harmonic can increase the efficiency of the inverse class F PA.

 Input voltage and output current of the

MOSFET for an inverse class F PA with 2nd
harmonic injection of proper phase.

40
 Many works assured that tuning only the 2nd and 3rd harmonics is very
adequate to design practical high efficiency class F and inverse class F power
amplifiers. More harmonics will increase the circuit complexity and matching
network losses without necessarily improving the efficiency.

Typical High Efficiency

PA operating at 3.5 GHz

41
 Many papers present different structures of transmission-line harmonic control and
loading networks that give appropriate performance by computer optimization.
However, there was no systematic and analytic technique to synthesize these
networks from explicit-form equations.

Typical 3.1 GHz Class F PA

42
 Many research works are devoted to the theoretical and practical performance
comparison between class F and inverse class F Pas.
Class F Inverse Class F
1. Usually is biased as class B at the pinch- 1. Usually is biased as class AB with certain
off point of the RF power device. quiescent current.

2. Gives slightly lower efficiency for the 2. Gives slightly higher efficiency for the
same device due to higher peak drain same device due to lower peak drain
current which increased power dissipation current at the ON period.
at the ON period.

3. Gives better power gain due to lower 3. Gives lower power gain due to higher
input drive power requirement. input drive power requirement.

4. Can be considered as a saturated current 4. Can be considered as a switching-mode

source amplifier with the drain current power amplifier with the drain current
being a half-sinusoidal wave. being a square wave.

5. Requires devices with lower breakdown 5. . Requires devices with higher breakdown
voltage due to lower peak drain voltage. voltage due to higher peak drain voltage.

43
 Many papers rely on extracting the optimum load impedances at the fundamental
frequency as well as 2nd and 3rd harmonics through load-pull measurements with
harmonic tuners. This can be performed either by hardware or software using the
non-linear CAD transistor model.

44
 Some works are devoted to illustrate the effects of parasitic
components of the packaged transistor on the shape of the drain
current and voltage and on the output power and efficiency. The
necessary load conditions (short and open circuit harmonic
components) should be applied at the chip reference plane rather than
the extrinsic terminals.

45
 Some papers are concerned with the improvement of the bandwidth of
the class F PA by using Butterworth low-pass filters as part of the output
matching networks.

46
 Some research works use simplified switching device models to approximate
the analysis and design of the Class F and inverse Class F PAs.

 Other works utilize more complicated models for better accuracy.

47
  Some works discussed the effect of selecting the bias point on the performance of
class F and inverse class F PAs. Other works considered the analysis of the class F PA
with truncated sinusoidal current waveform and trapezoidal or clipped waveforms.

Fourier Components for a square wave Fourier Components for a trapezoidal wave
current waveform versus conduction angle current waveform versus conduction angle
48
 Many papers rely on improving the linearity of class F power amplifiers by
incorporating them with linearization sub-systems such a digital pre-distortion,
LINC transmitters and envelope elimination and restoration transmitters. These
types of transmitters are implemented using powerful DSP techniques.

Effect of using digital pre-distortion Effect of using digital pre-distortion on

on the ACPR for a 20 MHz LTE signal the ACPR for a 5 MHz WCDMA signal
amplified with a non-linear RF PA. amplified with a non-linear RF PA.

49
Digital
Predistortion
(DPD)

50
 Pioneers in High Efficiency RF Power Amplifier Development

Frederick Raab Andrei Grebennikov

Coined the term “Class F PA” in 1975. He
developed the theoretical calculations for
maximum efficiency and output power for
class F PA based on any number of
harmonics at device current and voltage
waveforms.
Developed several loading networks
for class F and inverse class F PAs
analytically using both lumped
elements and transmission lines.

51
 Marian Kazimierczuk Steve Cripps

Developer of the inverse Class F PA Inventor of the Class J PA in

in 1984 using λ/4 transmission line 2006.
and series resonant circuit.
Nathan Sokal

Inventor of the Class E PA in 1975

52
 Suggested Developments for the Class F and Inverse Class F
Power Amplifiers in the Current Research Work

 Design of class F and inverse class F Power amplifiers with new load network
topologies taking into account the parasitic elements of the packaged RF power
transistor. A systematic mathematical procedure can be developed for the
synthesis of the harmonic control loading networks for the required harmonic
impedances at the specified frequencies. The RF transistor bare die and packaged
nonlinear models can be used to evaluate the parasitic elements of the transistor
which are necessary to determine the load network parameters.

For class F PA, Z’D1= Ropt For inverse class F PA, Z’D1 = Ropt
Z’D2 = 0, Z’D3 = ∞ Z’D2= ∞, Z’D3 = 0
53
 Development of a reconfigurable dual band high efficiency RF power amplifier.
This can be achieved by using dual matching networks with microwave switches
implemented using PIN diodes and broadband GaN HEMT transistor.

The dual band operation can also be implemented using the same matching
networks but with two modes like the class F and inverse class F with different
center frequencies.

54
 Development of a dual mode power amplifier suitable for two type of RF
modulated signals: Constant envelope and variable envelope. The linear mode
can be implemented using either class AB or class J, while the nonlinear high
efficiency mode can be implemented using either class F or inverse class F. The
tuning of the short circuited and open circuited stubs can be implemented with
the aid of Pin diode switches.

55
 A new approach for the design of high efficiency class F RF
power amplifiers

Simplified block diagram of the power amplifier

• The intrinsic output capacitance of the power device can be found from the bare
die model of the transistor provided by the manufacturer. A signal can be injected
at the output port with a specified sweeping frequency range and the input port is
short circuited to ground. A parallel resonance will occur between the device output
capacitance and the DC feed inductance. This can be implemented with the aid of
an advanced simulator like Keysight ADS.
56
• After estimating the output capacitance of the chip model, the parasitic
inductances and capacitances of the packaged device can be obtained by mean
of optimization to minimize an error function between the S-parameters of the
chip model and the measured S-parameters of the packaged transistor.

• The optimum load impedance at the fundamental frequency that will achieve
maximum efficiency and output power can be can evaluated from a computerized
sweep after terminating the second harmonic component while peaking the third
harmonic component using a harmonic control circuit.

• The required load and source impedance at the fundamental and two first
harmonic frequencies can thus be determined from the parasitic reactances
and the optimum intrinsic impedances at the first three harmonics.

• The parameters of the load network can be determined after writing the
necessary equations of the harmonic impedances in terms of the characteristic
impedance and the electric lengths of the transmission lines comprising the load
network. These simultaneous equations are solved numerically.

57
 Implementation of the procedure for a 900 MHz power amplifier using
the GaN 6 W CGH40006P HEMT

1.6
600
1.4
500
1.2

1.0 400

Gm, mS
ID, A

0.8 300

0.6
200

0.4
100
0.2
0
0.0
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VGS , V
VGS , V

Simulated drain current versus gate- Simulated transconductance versus gate-

source voltage source voltage

58
 VGS =0
1.6

1.4

1.2

1.0

0.8

ID.i, A
0.6

0.4

0.2

0.0

-0.2
0 5 10 15 20 25 30

VDS
12
11
10
9
8
7

VGS = 0
Rds

6
5
4
3
2
1
0
0 1 2 3 4 5

VDS

59
Test setup to estimate the output capacitance of the chip model of the
transistor

V_DC
VDD
Vdc =VDS V
C
Cby2 HARMONIC BALANCE
C=200 pF
L Ha rmonic Ba la nc e
L1 HB1
L=5 nH Fre q[1]=f MHz
R= Orde r[1]=8
V_DC
VGG Vd
C V
Vdc =VGS DC_Fe e d
Cby1 I_P robe P _1Tone
DC_Fe e d1
C=200 pF DC_Bloc k Iin P ORT 1
DC_Bloc k1 Num=1
Meas
Me a s Eqn
E qn
Z=50 Ohm
Me a s 1
P =pola r(dbmtow(10),0)
Zd=Vd[1]/Iin.i[1]
Fre q=f MHz
Vg
C GH60008D

DC_Bloc k
DC_Bloc k2 CGH60008D_r6_CGH60_r6 Var
E qn
VAR
Q1 VAR1
tc a s e =25 RL=50
rth=0.001 VDS =28
VGS =-8.0
f=900

60
 7000
m1
m1
6000
f= 2801.000
m a g(Zd)=6812.372
5000
Ma x

ma g (Zd )
4000

3000

2000

1000

0
800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400

100

50
pha s e (Zd)

0 Cds = 0.64 pF

-50

-100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400

61
 Evaluation of the Optimum Load Resistance
I_P robe
HARMONIC BALANCE
Ibias
HarmonicBalance
HB1
V_DC F req[1]= 900 MHz
VDD O rder[1]= 8
Vdc= VDS V
TLIN
C
TL5
Cby2
Z= 50.0 O hm
C= 200 pF
TLIN E= 30
TL1 F = 0.9 G Hz
Z= 100 O hm
E= 90
F = 0.9 G Hz
V_DC
VG G Vd
C TLIN
Vdc= VG S V I_P robe Vout
Cby1 TL2 TLIN Iout
C= 200 pF Z= 100 O hm I_P robeDC_Block TL3
DC_Block1 Term
E= 90 ID Z= RL TLIN Term2
F = 0.9 G Hz E= 30 TL6 Num= 2
F = 0.9 G Hz Z= 50.0 O hm Z= RL O hm
E= 60
Vg F = 0.9 G Hz
I_P robe CGH60008D
P _1Tone DC_Block Ig
P O RT1
DC_Block2 CG H60008D_r6_CG H60_r6
Num= 1
Z= 50 O hm Q1
P = polar(dbmtow(P in),0) tcas e= 25
F req= 900 MHz rth= 0.001
Va r
Eq n
VAR
VAR1
RL= 50
VDS = 28
VG S = -3
P in= 27

Me a s
Eq n
Meas Eqn
Meas 1 Pt
Idc= mag(Ibias .i[0])
P dc= Idc*VDS P t
eff= (P out/P dc)*100 P out
P out_dBm= 30+ 10*log(P out) P out= pt(Vout,0,Iout.i)
G p= P out_dBm-P in
Zd1= -Vd[1]/ID.i[1]
Zd2= -Vd[2]/ID.i[2]
Zd3= -Vd[3]/ID.i[3]
Zg1= Vg[1]/Ig.i[1]
P s = dbmtow(P in)
P AE= ((P out-P s )/P dc)*100
Zin= Vin[1]/Iin.i[1]
G amma= mag((Zin-50)/(Zin+ 50))
IRL= 20*log(G amma)

62
 1 00

80

60 Pin = 27 dBm (0.5 W)

Efficie ncy
40 f = 900 MHz

20

Selected RL(opt) = 50 Ω to
make compromise 0
0 10 20 30 40 50 60 70 80 90 1 00

between maximum RL

efficiency and output Efficiency versus RL

power 42

40

38

36
P out_dBm

34

32

30

28

26
0 10 20 30 40 50 60 70 80 90 100

RL, ohm

Output Power versus RL 63

 60 1.4

1.2
50

1.0
40
0.8
Vds , V

id, A
30 0.6

20 0.4

0.2
10
0.0
0
-0.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
time , ns e c
time , ns e c

Drain Voltage Waveform Drain current waveform

-2
Vgs , V

-4

-6

-8

-10
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

time , ns e c

Gate Voltage Waveform 64

 Estimation of the Parasitic Elements for the Packaged Model

S -P ARAMETERS

S_Pa ra m
SP1
V_DC Sta rt=600 MHz
VDD
Stop=2000 MHz
DC _Fe e d Vdc =VDS V Ste p=10 MHz
C
Va r
Eq n VAR
C by2 DC _Fe e d2 VAR 1
V_DC C =200 pF R L=50
VGG VDS=28
Vdc =VGS V VGS=-3
f=900

DC _Bloc k
DC _Bloc k1
C DC _Fe e d
DC _Fe e d1 L
C by1
C =200 pF Ld Te rm
L=0.65 nH {o} V_DC
Te rm2
R= VDD1
Num=2
Z=50 Ohm Vdc =VDS V
C
C by4
C
Te rm C ds V_DC C =200 pF
Te rm1 VGG1 DC _Fe e d
DC _Bloc k C =0.6 pF {o} DC _Fe e d3
Num=1 Vdc =VGS V
DC _Bloc k2
Z=50 Ohm L CGH6 0 0 0 8 D

Lg C
L=0.55 nH C gsC GH60008D_r6_C GH60_r6
R= C =0.5
X1 pF
tc a s e =25 C DC _Fe e d
rth=0.001 DC _Fe e d4
C by3 DC _Bloc k
C =200 pF DC _Bloc k3 Te rm
Te rm4
Num=4
Z=50 Ohm

Te rm Cre e CGH4 0 0 0 6 P
O P TIM Te rm3
DC _Bloc k
Num=3
Z=50 Ohm DC _Bloc k4 C GH40006P_r6_C GH40_r6
Optim
Optim1 X2
OptimType =Gra die nt Sa ve C urre ntEF=no tc a s e =25
Ma xIte rs =50 Ena ble C oc kpit=ye s c rth=9
De s ire dError=0.0
Sta tus Le ve l=4
Fina lAna lys is ="None " Me a s
Eq n Me a s Eqn
Norma liz e Goa ls =no
Me a s 1
Se tBe s tVa lue s =ye s
S11e =ma g(S(1,1)-S(3,3))
Sa ve Solns =ye s
S22e =ma g(S(2,2)-S(4,4))
Sa ve Goa ls =ye s
S21e =ma g(S(2,1)-S(4,3))
Sa ve OptimVa rs =no
Upda te Da ta s e t=ye s G O AL
G O AL G O AL
Sa ve Nomina l=no
Sa ve AllIte ra tions =no Goa l
Goa l Goa l
Us e AllOptVa rs =ye s OptimGoa l3
OptimGoa l1 OptimGoa l2 Expr="S21e "
Us e AllGoa ls =ye s Expr="S11e " Expr="S22e "
SimIns ta nc e Na me ="SP1"
SimIns ta nc e Na me ="SP1" SimIns ta nc e Na me ="SP1" We ight=1
We ight=1 We ight=1.5

65
 Comparison between the parameters of the optimized model and
25
the packaged transistor
0

-5
20

-10
dB(S (4,3))
dB(S (2,1))

15

dB(S (3,4))
dB(S (1,2))
-15

10 -20

-25
5
-30

0 -35
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

fre q, GHz fre q, GHz

0 0

-2
-2
dB(S (3,3))
dB(S (1,1))

-4
dB(S (4,4))
dB(S (2,2))
-4

-6
-6

-8
-8

-10
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -10
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
fre q, GHz
fre q, GHz

66
Practical Test Setup

67