UNIT II

VLSI CIRCUIT DESIGN

PROCESSES
 INTRODUCTION

• Objectives:
– To learn the steps of VLSI Design flow
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout and symbolic diagrams

• Outcome:
– At the end of this, will be able draw the stick
diagram, layout and symbolic diagram for simple
MOS circuits
UNIT – II CIRCUIT DESIGN PROCESSES
 Unit II
VLSI CIRCUIT DESIGN PROCESSES
Topics
• VLSI design flow
• MOS layers
• Stick diagrams
• Design Rules and Layout
• 2 um CMOS design rules for wires
• Contacts and Transistors
• Layout diagrams for NMOS and CMOS inverters
and gates
• Scaling of MOS circuits
 VLSI Design of approach of IC

26/038/2
015
 VLSI DESIGN FLOW
 A design flow is a sequence of operations that transform
the IC designers’ intention (usually represented in RTL
format) into layout GDSII (Graphic Design System) data.

 A well-tuned design flow can help designers go through

the chip-creation process relatively smooth and with a
decent chance of error-free implementation.

 A skilful IC implementation engineer can use the design

flow creatively to shorten the design cycle, resulting in a
higher likelihood that the product will catch the market
window.
 MOS Layers
• p-substrate
• n-well
• n+
• p+
• Gate oxide (thin oxide)
• Gate (polycilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation

209
 STICK DIAGRAMS

• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of
stick diagram.
– To learn how to draw stick diagrams for a
given MOS circuit.

• Outcome:
– At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• VLSI design aims to translate circuit concepts

onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick convey layer information
diagrams
through codes (or monochrome
color as an interface between symbolic
• Acts
encoding).
circuit and the actual layout.
UNIT – II CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

• Does show all components/vias.

– Via is used to connect higher level metals from metal
connection

• It shows relative placement of components.

• Goes one step closer to the layout
• Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries
– Any other low level details such as
parasitics

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Notations

Metal 1

poly
ndiff

pdiff
Can also draw
in shades of
gray/line style.
Buried Contact

Contact Cut
UNIT – II CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 1:
When two or more ‘sticks’ of the same type cross or touch
each other that represents electrical contact.

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 2:
When two or more ‘sticks’ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly)

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 3:
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

UNIT – II CIRCUIT DESIGN PROCESSES
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 4:
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.

UNIT – II CIRCUIT DESIGN PROCESSES

NMOS INVERTER STICK
DIAGRAM 5
V V
D
D
De
D
p
S
Vou O
t D U
T
A
En
h GN
D

0
V
25
NMOS-NAND
NMOS-NOR
NMOS EX-OR
NMOS EX-NOR
PMOS-INVERTER
PMOS NAND
PMOS-NOR
CMOS INVERTER STICK
DIAGRAM

VDD

GND

FIG 1 Supply rails

33
CMOS INVERTER STICK
DIAGRAM
VD
D

PMO
S D
S

S D
NMO
S

G
N

D
Fig 2 Drawing Pmos and Nmos
Transistors between Supply rails 34
Department of Electro
 CMOS INVERTER STICK
DIAGRAM

VD
D

PMO
S D
S
A

S D
NM
OS

GND
Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input With
same gate poly silicon metal

35
Department of Electronics and Communication E
CMOS INVERTER STICK
DIAGRAM

VD
D

S D PMO
A S

S D
NM
OS

GND
Fig 4 Combining Drain pf Pmos and Nmos
Transistors to take output with metal 1

VBIT 36
Department of Electronics and Communication Engineering,
CMOS INVERTER STICK
DIAGRAM
VD
D

PMO
S D S
A B

S D NM
OS

GND

Fig 5 Take the output with the

poly silicon metal

37
Department of Electronics and Communication Engineering,
CMOS INVERTER STICK
DIAGRAM
VD
D

PMO
S D S
A B

S D NMO
S

GND

Fig 6 Connect the source of Pmos to

VDD and Nmos to GND

38
Department of Electronics and Comm
CMOS INVERTER STICK
DIAGRAM
CONTA
VD
CT
D

PMO
S D
S
A B

S D NMO
S

GND

Fig 7 Connect the contact cuts where the

different metals are connected

VBIT 39
Department of Electronics and Communication Engineering,
CMOS INVERTER STICK
DIAGRAM
CONTA
CT
VD
D
PMO
S D
S
A B

S D NMO
S

GN
Substrate
D
contact
Fig 8 Final CMOS
Inverter

40
 Sticks design CMOS NAND:
• Start with NAND gate:
 NAND sticks

VDD
a

out

VSS
Stick Diagram - Example

Power

A Out

Ground
Stick Diagram - Example A
OUT
B

NOR Gate

230
2 I/P OR GATE
2 I/P AND
Y=(AB+CD)’
Y=(AB+CD)’ “TICK
Stick diagram
Draw the CMOS circuit & Stick diagrams for
following
• F= [(xy) +z]’

• F=[a(b+c)]

• F=[a.b+c]’

• F=[ab+cd]

• F=[(a+b)(c+d)e]’
 Stick diagram

1) (AB+A’B’)’

2) [A(B+C)+DE]’
 Design Rules for Layout
• Design rules are a set of geometrical
specifications that dictate the design of the layout
masks
• A design rule set provides numerical values
– For minimum dimensions
– For minimum line spacings
• Design rules must be followed to ensure
functional structures on the fabricated chip
• Design rules change with technological advances
(www.mosis.org)
 DESIGN RULES

• Why we use design rules?

– Interface between designer and process engineer

• Historically, the process technology referred to the

length of the silicon channel between the source and
drain terminals in field effect transistors.
• The sizes of other features are generally derived as
a ratio of the channel length, where some may be
larger than the channel size and some smaller.
– For example, in a 90 nm process, the length of the channel may be 90
nm, but the width of the gate terminal may be only 50 nm.

UNIT – II CIRCUIT DESIGN PROCESSES

DESIGN RULES

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Design rules define ranges for features

– Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts

– Measured in microns

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Two major approaches:

– “Micron” rules: stated at micron resolution.
–  rules: simplified micron rules with
limited scaling attributes.
• Design rules represents a tolerance which insures
very high probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

“Micron” rules

• All minimum sizes and spacing specified in

microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ
based rules
• Standard in industry.

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Lambda-based (scalable CMOS) design rules define

scalable rules based on  (which is half of the
minimum channel length)

• Stick diagram is a draft of real layout, it serves as an

abstract view between the schematic and layout.

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
• On the other hand, the process engineer wants design
rules that result in a controllable and reproducible
process.
• Generally we find there has to be a compromise for a
competitive circuit to be produced at a reasonable cost.
• All widths, spacing, and distances are written in
the form
•  = 0.5 X minimum drawn transistor length

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

Lambda-based Design Rules

• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting
out mask
• If design rules are obeyed, masks will produce working
circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of
area to be contacted
UNIT – II CIRCUIT DESIGN PROCESSES
 DESIGN RULES

Advantages of Generalized Design Rules

• Ease of learning because they are scalable, portable,
durable

• Long-levity of designs that are simple, abstract and

minimal clutter

• Increased designer efficiency

• Automatic translation to final layout

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Minimum width of PolySi and diffusion line 2
• Minimum width of Metal line 3 as metal lines run over a
more uneven surface than other conducting layers to ensure
their continuity

Metal

Diffusion


  Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• PolySi – PolySi space 2
• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of
their associated regions overlapping and conducting
current

Metal

Diffusion

  Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• Diffusion – PolySi space  To prevent the lines overlapping
to form unwanted capacitor
• Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal
lines can overlap or cross

Metal

Diffusion

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES
• It is recommended practice to leave  between a metal
edge and a polySi or diffusion line to which it is not
electrically connected.

Metal


Polysilicon

UNIT – II CIRCUIT DESIGN PROCESSES

 DESIGN RULES

• Recall

– poly-poly spacing 2

– diff-diff spacing 3

– metal-metal spacing 2

– diff-poly spacing 

UNIT – II CIRCUIT DESIGN PROCESSES

Lamda Based Design Rules
`
CMOS LAMDA BASED RULES
 CMOS Lamda based rules

(1) Rules for the Active area shown in the Figure 2.9.

1. Minimum width = 3 λ
2. Minimum spacing = 3 λ
3. Source/Drain active to well edge = 5 λ
4. Substrate/well contact active to well edge = 3 λ
Rules for Active area
(2) Rules for poly 1 as shown in the
Figure .

1. Minimum width = 2 λ
2. Minimum spacing = 2 λ
3. Minimum gate extension of active = 2
λ
4. Minimum field poly to active = 1 λ
Rules for poly1
 Rules for contact to poly 1

(3) Rules for contact to poly 1 as shown

in the Figure 2.11.
1. Exact contact size = 2 λ mul 2 λ
2. Minimum poly 1 overlap = 1 λ
3. Minimum contact spacing = 2 λ
Rules for contact to poly 1
(4) Rules for contact to active as shown in the
Figure 2.12.
1. Exact contact size = 2 λ mul 2 λ
2. Minimum active overlap = 1 λ
3. Minimum contact spacing = 2 λ
4. Minimum spacing to the gate of transistor = 2 λ
Rules for contact to active area
(5) Rules for metal 1 as shown in the Figure
2.13
.
1. Minimum width = 3 λ
2. Minimum spacing = 3 λ
3. A minimum overlap of poly contact = 1 λ
4. A minimum overlap of active contact = 1 λ
Rule1s for metal1
(6) Rules for via 1 as shown in the
Figure

1. Minimum size = 2 λ
2. Minimum spacing = 3 λ
3. Minimum overlap by metal 1 = 1 λ
Rules for via 1
(7) Rules for metal 2 as shown in the Figure
2.15.

1. Minimum size = 3 λ
2. Minimum spacing = 4 λ
Figure
Rules for metal 2
(8) Rules for metal 3 as shown in the Figure

1. Minimum width = 6 λ
2. Minimum spacing = 4 λ
Rules for metal 3
 LAYOUTS

• Layer Types
– p-substrate
– n-well
– n+
– p+
– Gate oxide
– Gate (polysilicon)
– Field Oxide
• Insulated glass
• Provide electrical isolation

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS

N+ N+

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
Top view of the FET pattern

NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
General Layout Geometry
Vp

Shared drain/
source

Individual Shared Gates

Transistors

Gnd
UNIT – II CIRCUIT DESIGN PROCESSES
 LAYOUTS
Parallel Connected MOS Patterning
A x B x
A B

X X X
y
y

X X
A B
A B
X X

y y
UNIT – II CIRCUIT DESIGN PROCESSES
 LAYOUTS
The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
x X

X
Gnd

Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 STICK DIAGRAMS

Examples of Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NOT Gate

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NOT Gate
Vp
Vp

X X

x x

X X

Gnd
x Gnd
x

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NAND Gate

Vp Vp

X X X
a .b

Gnd
a .b
a b
X X

a b
Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NAND Gate

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NOR Gate

Vp
Vp

X X

a
b a
b
a b X
Gnd X X
a b
Gnd

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The CMOS NOR Gate

UNIT – II CIRCUIT DESIGN PROCESSES

 LAYOUTS
The Transmission Gate

UNIT – II CIRCUIT DESIGN PROCESSES

 Micron rules

2 μM DOUBLE METAL, DOUBLE POLY,, CMOS/BI-CMOS

RULES.
Scaling of MOS Circuits
 What is scaling ?
• Proportional adjustments of the dimensions
of an electronic device while maintaining
the electrical properties of device.
• The reduction of the size ,i.e , the
dimensions of MOSFET, is commonly
referred to as scaling.
 Scaling
• Microelectronic technology may be
characterized in terms of several
indicators, or figures of merit.
Commonly, the following are used:
• Minimum feature size
• Number of gates on one chip
• Power dissipation
• Maximum operational frequency
• Die size
• Production cost.
 Types of scaling
• Three types of scaling models used in VLSI
• 1) Combined voltage (V) and
Dimension(D) scaling model.
• 2)Constant electric field (E) scaling model.
• 3) Constant voltage (V) scaling model.
 Scaling Factors
• In our discussions we will consider 2
scaling factors, α and β
• 1/ β is the scaling factor for VDD and oxide
thickness D
• 1/ α is scaling factor for all other linear
dimensions
• We will assume electric field is kept
constant
Scaled n Mos transistor
Scaling factors for device
parameters
Summary