Equivalence Example - 2
2
7
4
Fault Dominance
• If all tests of some fault F1 detect another fault F2,
then F2 is said to dominate F1.
• Dominance fault collapsing:
• Eliminate the dominating fault from the fault list. If
fault F2 dominates F1, then F2 is removed from the
fault list.
• If two faults dominate each other then they are
equivalent.
2
Fault Dominance
All tests of F2
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100
s-a-1 Only test of F1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
3
Fault Dominance
• For the 3 input AND gate shown, we will thus
eliminate the s-a-1 fault from the output.
• Also the three-input AND gate with four faults
left after dominance fault collapsing.
• Since the output s-a-0 is equivalent to any
input s-a-0 ,we have moved all faults to inputs
Fault Dominance Rules
• An n-input Boolean gate requires n + 1 single stuck-at
faults to be modeled.
• To collapse faults of a gate, all faults from the output
can be eliminated retaining one type (s-a-1 for AND
and NAND; s-a-0 for OR and NOR) of fault on each
input
and
• the other type (s-a-0 for AND and NAND; s-a-1 for
OR and NOR) on any one of the inputs.
• The output faults of the NOT gate can be removed as
long as both faults on the input are retained.
Dominance Example -1
Dominance Example -2
Checkpoints
• Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
• Checkpoint theorem: A test set that detects all
single (multiple) stuck-at faults on all checkpoints
of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit.
Total fault sites = 16
Checkpoints ( ) = 10
Copyright 2001, Agrawal &
VLSI Test: Lecture 5 8
Bushnell
Glossary of faults
• Initialization fault
• Redundant Fault
• Multiple stuck-at fault
• Delay faults – transition faults, gate-delay
fault, path-delay fault.
• Bridging fault
• Un-testable fault
Initialization fault
• Circuits with memory elements are designed so that
they can be initialized by applying suitable input signals.
• Faults that interfere with such an initialization
procedure are called initialization faults.
• Assume that the initial state of the circuit (i.e., output
Q) is unknown, denoted as X.
• To set Q to 0, we apply A =1, B =0
• After the application of the clock CK, the fault-free
circuit output is initialized to 0, but the faulty circuit
remains in the unknown state.
• Such a fault that prevents the circuit from being
initialized is called an initialization fault.
Initialization fault
Redundant Fault
Redundant Fault
• Such faults can be removed from the circuit without
changing its output function.
• The output function of the circuit is
• If the B input of the NAND gate has a s-a-1 fault,
then the output of the NAND gate will be which is
the same as the fault free circuit.
• The fanout of B where the fault lies is deleted and
the corresponding input of the NAND gate is set to
1.
• The output of the NAND gate is now and it can be
replaced by a NOT gate.
Multiple Stuck-at Faults
• A multiple fault is a condition caused by the
simultaneous presence of a group of single faults.
• Frequently considered multiple faults consist of the
same type of single faults.
• The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3k-1,
which is too large a number even for circuits of
moderate size.
Multiple Stuck-at Faults(MSF)
• Total MSF for a two input NAND gate
• is 33 – 1 = 26 faults
• =(6 single faults+12 double faults+8 triple faults)
• Lines X sa1 and B sa0 are the faults
• Hence a double fault is present in this ckt
