FOURAH BAY COLLEGE

INSTITUTION
ELECTRICAL AND ELECTRONIC
DEPARTMENT ENGINEERING

ADVANCED DIGITAL SYSTEMS DESIGN

MODULE TITLE

EENG424
MODULE CODE

PROF JONAS A S REDWOOD-SAWYERR

MODULE LECTURER
Mobile : +232 76 670904, +232 88 001019,
+232 25 273401
Email : jasredwood@usl.edu.sl,
CONTACTS
abiosehrs@gmail.com,
jredwood_sawyerr@yahoo.com

LECTURE HOURS/LAB. 3-0-3

PRACTICALS/CREDIT HOURS
Examination will account for 70% of the overall
ASSESSMENT
grade whilst continuous assessment will account for
 30%. Question sets at the end of each lecture must
be returned for grading one week after receipt of
lectures and will account for 10% of the continuous
assessment grade.
This module draws from a number of concepts met
in earlier years of the programme and seeks to
show how these engineering tools can be used in
digital systems design. You may wish to revise
Modules in Digital Systems at Year IV so as to
better cope with the discussions as these concepts
OBJECTIVES AND OUTCOMES will be assumed during our lectures.

References have been made to a number of text

books which are listed in the section for Further
Reading, and modifications made for a coherent and
reader-friendly presentation with worked examples
and assignments provided.

Below is a list of the topics to be covered.

 Systems Reliability (R(t) = exp(-λt), where λ is

MODULE DESCRIPTION defined as the Failure Rate
 Mean Time To Repair (MTTR)
 Mean Time Between Failure (MTBF)
 Fault Diagnosis in Combinational circuits
  Review of Shift Register in Digital Systems
Design and the Universal State or DeBruign
Diagram
 Design using PROMS and Programmable Logic
Arrays (PLAs)

References
Kreyszig, Erwin, ‘Advanced Engineering
Mathematics, Wiley Eastern Private Limited, New
Delhi
SUGGESTED Gabel, Robert A and Richard A Roberts, ‘Signals and
READINGREFERENCE Linear Systems,’ John Wiley and Sons. Inc.
Ziemer, R E and W H Tranter, ‘Principles of
TEXTS/MANUALS/WEBSITES Communications, Systems, Modulation and Noise,’
Houghton Miflin Company, Boston.
Ziemer, Rodger E, ‘Signals and Systems: Continuous
and Discrete,’ Prentice Hall. ISBN 9780134964560.
04 – FAULT DIAGNOSIS IN
LECTURE NUMBER COMBINATIONAL CIRCUITS
LECTURE DURATION (HOURS) 02

SPECIFIC INSTRUCTIONAL At the end of this lecture the students should be

OBJECTIVES AND LEARNING able to :
OUTCOMES
1. Identify the different categories of testing
techniques
 2. Model fault occurrences in combinational
logic circuits
3. Generate all fault conditions in a
combinational circuit

2.0 FAULT DIAGNOSIS IN COMBINATIONAL CIRCUITS

With growing miniaturisation of electronic circuits the traditional means of testing for faults
can no longer be used and quite often the maintenance approach becomes one of
replacement of faulty cards rather than identifying individual faulty components. In many
instances this may prove less cumbersome and expensive especially when the fault detection
becomes rather time consuming and the replacement card may be almost as expensive as the
faulty IC. Surface mounting techniques in IC fabrication has largely removed the soldering
iron from the portfolio of tools in the maintenance of a wide range of electronic equipment,
and computer based techniques are increasingly being used for fault diagnosis.

Testing techniques

These can be classified into two categories :

1. Functional testing
2. Structural testing

Functional testing

This is a technique of testing the system or circuit to ensure that it meets the manufacturer’s
specifications. This method can involve applying all possible input logic combinations and
comparing the results with the expected circuit response.

This method while convenient for simple circuits, clearly has limitations, as the number of
input variables increases, the number of possible test inputs increases exponentially as 2n
where n is the number of input variables. However this technique lends itself to
computerisation as an algorithm can be derived for large test conditions.

Structural Testing

This is a technique where tests are carried out at the gate level to ensure that individual
components of the network are working correctly. They are designed to detect, locate and
identify faults in a circuit.

Categories of faults in combinational circuits

a) Logical faults and

b) Non-logical faults

a. Logical Faults

In analysing combinational circuits using this technique the following assumptions are made :

i. Two models are assumed for determining logical faults. These are :
a. Stuck-at-zero (s-a-o) and
b. Stuck-at-one (s-a-1).
ii. The combinational circuit tested should not have redundant paths
iii. Faults considered are non-transient.

b. Non-Logical faults

These are faults such as power supply failures, cross talk in communication systems, solder
float which can present itself as a short circuit due to the shorting of the copper tracks on a
circuit board.
Testability of circuits

The following conditions must be met for a circuit to be testable.

a) Circuits should be designed so as to make them amenable to partition or modular

testing.
b) For circuits with feedback it should be possible for tests to be done with or without
feedback.
c) In cases of circuits having oscillators, it should be possible to use an external oscillator
to carry out tests.
d) It should be possible to set memory elements to zero before tests are carried out.

Redundancy

Let us now briefly consider the effects of redundancy on the fault performance of circuits and
why this condition should be avoided in practice.

Consider the following circuit

g1

g3

g2

The output of the circuit is given by

F = AB’ + A’BC + C
Factorising yields

F = AB’ + C.

i.e. the output of gate 2 is unimportant and redundant as it does not affect the overall output
of the circuit. Hence a fault occurring at the terminals of that gate will not be detected.

Fault conditions of a logic circuit

Let us consider the following circuit.

p
v
q r
x

s w

u
t

Note that the internal wires of the circuit are labelled as p, q, r, s, t, u. v, w, and x.

Fault diagnosis - Functional

In running a test regime for this circuit we shall tabulate all possible input conditions and then
compare the faulty and fault-free outputs. We shall than identify distinct tests or input
conditions that will enable us to detect the possible faults that could arise in the circuit.
Let us refer to the Fault Table. The test inputs are labelled by their decimal equivalent, i.e.
Test input 011 is labelled as Test 3.

Two fault conditions are now discussed:

Case 1: Line q is stuck at 1. Let the corresponding output response of the circuit be f1

Case 2 : Any one of lines p, q, r is held at zero.

Let the corresponding output response be denoted by f2.

Fault Table

Fault Faulty response

Test Inputs free Comments
response
A B C f(A’B’C’+ f1(A’C’+ f2(AB’C)
AB’C) AB’C)
0 0 0 0 1 1 0 f2 detected
1 0 0 1 0 0 0
2 0 1 0 0 1 0 f1 detected
3 0 1 1 0 0 0
4 1 0 0 0 0 0
5 1 0 1 1 1 1
6 1 1 0 0 0 0
7 1 1 1 1 1 1

NB: f1 represents fqs-a-1

f2 represents fps-a-0, qs-a-0, rs-a-0
p
v
q r
x

s w

u
t
Summary

Analysis therefore shows that f1 is detected using Test 2 and f2 is detected using Test 0.

The distinguishing test to detect fault condition of q stuck at 1 is therefore A = C = 0; B = 1.

Similarly, fault f2 is detected for a test input condition A = B = C = 0.

NB. To test for a fault on a wire, the inverse of the stuck-at-value should be
applied to the faulty input

Fault Detection and Location Procedure

Consider the following circuit

p
t
q
v

r u

NB: The wires are once again labelled in red as p, q, r, s, t, u, and v.

We note the fault-free response is given by

f0 = AB + BC’
For s-a-0 and s-a-1 faults in the lines labelled we obtain the following responses of the circuit
where fp0 for example denotes the output response of the circuit when line p is stuck at
zero. This is distinct from variable input A = 0 as the input variable A can take values of zero
or 1 as the case may be while the line p is stuck at zero for all combinations of the inputs.

s-a-0 output responses

fp0 = pB + BC’

Since p is stuck at zero the faulty output becomes

fp0 = BC’. NB. It is not the variable A that is stuck at zero but the line or wire p that is
stuck at zero.

Similar derivations yield

fqo = BC’ ; fro = AB ; fso = AB, fto = 1 ; fu0 = 1 ; fv0 = 0

s-a-1 output responses

fp1 = B; fq1 = A + BC’ ; fr1 = C’ + AB ; fs1 = B ; ft1 = BC’ ; fu1 = AB ; fv1 = 1

It can be seen that some of the faulty responses are identical, making it difficult to isolate
which of these faults may have occurred. We shall now examine the output responses and
group similar ones under the same output function.

Identifying distinguishable output fault responses

Let fp0 = fq0 = ft1 = BC’ = f1

Let fr0 = fs0 = fu1 = AB = f2

Let ft0 = fu0 = fv1 = 1 = f3

Let fv0 = 0 = f4

Let fp1 = fs1 = B = f5

Let fq1 = A + BC’ = f6

Let fr1 = C’ + AB = f7

Fault Summary Table

This table provides a tabulation of all possible inputs into the circuit and the fault-free and
faulty responses, given each of the test inputs. As before the tests are labelled by their
decimal equivalent. Thus test input 110 is labelled as Test 6

Tests A B C f0(AB f1(BC’ f2(AB) f3(1) f4(0) f5(B) f6(A+ f7(AB

+BC’) ) BC’) +C’)
0 0 0 0 0 0 0 1 0 0 0 1
1 0 0 1 0 0 0 1 0 0 0 0
2 0 1 0 1 1 0 1 0 1 1 1
3 0 1 1 0 0 0 1 0 1 0 0
4 1 0 0 0 0 0 1 0 0 1 1
5 1 0 1 0 0 0 1 0 0 1 0
6 1 1 0 1 1 1 1 0 1 1 1
7 1 1 1 1 0 1 1 0 1 1 1

Here fo is the fault-free response of the circuit.

Assignment. None for this lecture

MODE AND DEADLINE FOR SUBMISSION OF
ASSIGNMENT Not Applicable