Experiments on Fault diagnosis in Combinational Circuits

INTRODUCTION

This series of experiments draws from the module Advanced Digital Systems Design
(ADSD) offered at Year 4 during the second semester. Students are advised to make
reference to their notes and information for additional reading provided in the notes.

THEORY

With growing miniaturisation of electronic circuits the traditional means of testing

for faults can no longer be used and quite often the maintenance approach becomes
one of replacement of faulty cards rather than identifying individual faulty
components. In many instances this may prove less cumbersome and expensive
especially when the fault detection becomes rather time consuming and the
replacement card may be almost as expensive as the faulty IC. Surface mounting
techniques in IC fabrication has largely removed the soldering iron from the portfolio
of tools in the maintenance of a wide range of electronic equipment, and computer
based techniques are increasingly being used for fault diagnosis.

Testing techniques

These can be classified into two categories :

1. Functional testing
2. Structural testing

Functional testing

This is a technique of testing the system or circuit to ensure that it meets the
manufacturer’s specifications. This method can involve applying all possible input
logic combinations and comparing the results with the expected circuit response.

This method while convenient for simple circuits, clearly has limitations, as the
number of input variables increases, the number of possible test inputs increases
exponentially as 2n where n is the number of input variables. However this
technique lends itself to computerisation as an algorithm can be derived for large
test conditions.

Structural Testing

This is a technique where tests are carried out at the gate level to ensure that
individual components of the network are working correctly. They are designed to
detect, locate and identify faults in a circuit.

Categories of faults in combinational circuits

a) Logical faults and

b) Non-logical faults

a. Logical Faults
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In analysing combinational circuits using this technique the following assumptions

are made :

i. Two models are assumed for determining logical faults. These are :
a. Stuck-at-zero (s-a-o) and
b. Stuck-at-one (s-a-1).
ii. The combinational circuit tested should not have redundant paths
iii. Faults considered are non-transient.

b. Non-Logical faults

These are faults such as power supply failures, cross talk in communication
systems, solder float which can present itself as a short circuit due to the shorting of
the copper tracks on a circuit board.

EXPERIMENTS

Student Learning outcomes

At the end of this experiment the students should be able to:

1. Explain the nature of faults in combinational circuits.
2. Generate test sets for a given circuits to detect a stuck at one and stuck at
zero faults.
3. Implement a single flow experiment using a minimal test set derived for the
circuit.
4. Validate test sets derived from theory.

Equipment required

Digital probes
Voltmeter
LEDs
Logic gates ( 74LS00 or equivalent)
Veroboard

Exercises

1. i. Construct the Fault summary table and derive the minimal fault detection
tests for the circuit in Fig.Q1 noting that the wires are labelled p, q, r, s, t, u,
v, w, and x.
ii. Design an experiment to locate a single flow fault in the circuit.
iii. Introduce s-a-0 and s-a-1 faults on at least three of the wires labelled and
validate the test set derived.
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P u

w x f

r
s v

Fig. Q1

2. The Chain Rule applied to the circuit in Fig 2 for faults in line i with reference to
line j, is given by

df ( X ) df d X j
= .
Xi dX j d X i

df (x)
Fig.Q2
dXj

Circuit A Circuit B
Xi i Xj j f(X)

df (x)
d Xi

d Xj
d Xi

i. Fig. Q3 shows a logic circuit using simple NAND gates. Using the method of
Boolean differences,
a. Find the Test set for all faults in line p.
b. Using the Chain Rule above, determine the test sets for all faults in line
p making reference to line q and compare with (a)

ii. Introduce s-a-0 and s-a 1 faults on input lines X2 and p and confirm the
validity of the test sets obtained in (a) and (b) by comparing their resulting
outputs with the fault-free outputs of the circuit.
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p r

Fig. Q3

Discussion

Were the learning outcomes fulfilled?

What were the challenges encountered during the experiment?
How were they resolved?

Reporting

A report is required.

Ing Prof J Redwood-Sawyerr

Lecturer in charge of ADSD