CHAPTER 1

Basic VLSI Design

+
DRAIN Vdd
-
n Type
Silicon

SOURCE

Figure 1.1: The beginning of the n-channel JFET

 Figure 1.2

Figure 1.3 : p-channel JFET

 Fig.1.4 Schematic Symbols

Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected

to V DD
p transistor

Polysilicon Gate
SiO2
Insulator L D D
W
Source Drain
G SB G
n+ n+
channel
p substrate S S
substrate connected
n transistor to GND

Figure 1.5 Physical structure of MOS transistors and their schematic icons
 D D

N G
G

S S
Figure 1.6(a): NMOS-transistor

D D

P G
G

S S

Figure 1.6(b): P-transistor

-G

D C S

G
Figure 1.6 (c ): C-switch

.
.

VDD

In Out

Gnd

Inverter

Figure 1.7: Transistor schematic of a static complementary inverter.

vdd

a b

vdd

a o/p

a o/p

b b

vss

a b

vss Fig. 19. NAND gate schematic

Fig 1.8 NOR gate schematic

 F1

D Q1

Cg

F
Figure 1.10: A dynamic latch circuit.

Wire segments

Figure 1.11(a): Wires and wire segments.

n-type p-type

Figure 1.11(b): Schematic symbols for transistors

 VDD

VDD
Pullup
Network
(p-transistors)

Inputs Out In Out

Pulldown
Network
(n-transistors)
Gnd

Gnd Inverter

Figure 1.12: General CMOS Layout structure, Circuit and the Layout diagram of CMOS Inverter.
 VDD

In Out

VSS

Figure 1.13: Stick diagram

Metal
p-diff
n-diff
poly
Figure 1.14: Stick diagram symbols

Table 1.1 Rules for possible interactions between layers.

VDD

Input
voltage
In

CL

t
Gnd

Inverter

Figure 1.15: The inverter circuit used for delay analysis

 VDD

In

CL

t
Gnd

Inverter

Figure 1.16: Circuit used for power consumption analysis

VDD
Id,p

IL
output
Id,n
CL
a b
Gnd

Figure 1.17: A pseudo-nMOS NOR gate

VDD

t1

t2 CL
b a

Figure 1.18: A circuit model for stuck-open faults.

 W1
i1
A
i2
D
i3 O1
B W2 F
i4
i5
E
i6 C
i7
i8 G O2

Figure1.19: Testing for combinational faults.

 Row-based
Symmetrical Array
Interconnect

Interconnect

Logic
Block

Logic
Block

Interconnect
Overlayed on
Logic Blocks
Interconnect

Sea-of-Gates Hierarchical PLD

Fig. 1.20 Commercially available FPGA architectures

1 PO 2 PO 3 PO

4 PI 5 PI 6 7

8 PI 9PI 10PI 11PI

Fig 1.21 Initial 3-restricted DAG

1 2 3
4 5 10 11

8 9

Fig. 1.22 Mapping of the 3-restricted DAG by four 3-LUTs

connection between wire segments in x and y axes and also vias.

Fig.1.23 3-D FPGA architecture

 CHAPTER 2
VLSI CAD

STRUCTURAL System BEHAVIOR

Register transfer Algorithms, flowcharts

Processors, Memories

Registers, flipflops, MUX Logic

Register Transfer

Gates Circuit Boolean expression

Transfer function
Transistors

Cell layout

Modules

Boards

PHYSICAL

Figure 2.1: Y-chart

CHAPTER 3
Partitioning in High Level Synthesis
A_PORT B_PORT
Architecture SHIFT_MULT of MULT is begin
START begin
process
variable A,B,M: BIT_VECTOR
CLK variable COUNT: INTEGER
begin
M_OUT DONE wait until (START =1)
A:= A_PORT; COUNT :=0;
Entity MULT is B:=B_PORT; DONE<=’0 ’
Port (A_PORT, M:=B”0000”;
B_PORT: in bit _ vector(3 down to 0); while (COUNT <4) loop
M_PORT: out bit _vector (7 down to 0); if (A(0)=’1’) then M:=M+B;
CLK: in BIT end if;
START: in BIT A:=SHR(A,M(0));
DONE: out BIT; M:=SHR(M,’ 0’);
); COUNT:=COUNT+1
end MULT; end loop;
M_OUT <=M & A;
DONE <=’ 1’;
End process;
End SHIFT_MULT;

Figure: 3.1 Example: Behavioral description of a 4 bit Shift multiplier

.
 Read START ‘1’ Read A_PORT Read B_PORT ‘0’

Write A Write B Write

0 1 = COUNT

‘0’ B”0000”

Write Write A
B1 DONE

Read COUNT ‘4’

Read
A[0] ‘1’
0 1
<

B4
0 1 Read M Read A
Read M Read B

&
‘1’
+
B2
Write Write
M_OUT DONE
Write M

0 1 Read A Read M[0]

Read SHR
COUNT ‘1’ Read M ‘0’

B3 Write A
SHR
+

Control-flow graph Write COUNT Write M

Figure: 3.2 CDFG for the shift-multiplier example

 START=1
S0
1
0
B1 A=A_PORT; COUNT=0;
0 B=B_PORT; DONE <= 0
M=B” 0000” ;

COUNT <4
S1
B4 0
1

M_OUT <= M & A; DONE <=’1’;

A(0) = ‘1’

1 B2
0
M = M + B;
S2

ENDIF

B3 A=SHR(A,M(0)); COUNT=COUNT + 1; S3
M=SHR(M,’0’);

Figure : 3.3 Scheduled CDFG for the shift multiplier

 A_PORT B_PORT

Mult A_Reg Count_Reg B_Reg

Shift1 Shift2 Compar Adder

START
Concat
enator
CLK
M_OUT
DONE

Figure: 3.4 Initial unit selection for the shift-multiplier design

A= S0 & START=1
B= S0 & ~(START=1) A_PORT
B_PORT
C= S1 & COUNT < 4
D= S1 & ~(COUNT < 4)
E= S2 & A(0)=1
F= S2 & ~ (A(0)=1)
G= S3
Mux1 Mux2

Control Unit A B C D E F G
Mux1 - - - - 1 - 0
Count_Reg
Mux2 1 - - - - - 0 Multiplier

Mux3 - - - - 0 - 0
A_Reg 0001
B_Reg
Mux4 - - - - 0 - 1 0

Load A_Reg 1 - - - - - 1

Load B_Reg 1 - - - - - - Mux3 Mux4

Clear 1 - - - - - -
Count_Reg
Shift1 Shift2
Load - - - - - - 1
Count_Reg
Clear 1 - - - - - - Adder
Multiplier
Load - - - - 1 - 1
Multiplier 0100
Adder - - - - 1 - 1

Shift1 - - - - - - 1

Shift2 - - - - - - 1
Comp
DONE 0 - - 1 - - -

Next State S1 S0 S2 S0 S3 S3 S1

Concat
State Reg
START
A_Reg(0)

CLK Comp LT
M_OUT
DONE

Figure 3.5 Synthesized design for the shift-multiplier example

3.2 PARTITIONING

a b

a FF1 FF2 c
Chip1 c
b
ni nj
d ni nj
REG
e
Chip2
f
g
(a) d e f g
(b)
G1
a v1 v2 v3
c
v
b
Cutline e24 G
ea36
v v
d v4 v5
v
e e25
V6
f
G2
g v

(b)
Figure 3.6 Circuit Partitioning: (a) an example (b) graph and its physical representations
 V1 V1 V2 V3 V4 V5
Graphical
5 Representation
4 Closeness measurement Cluster Tree Representation
V(24)
V1 -- -- -- -- -
V2 -V 5 -- -- -- --
1 V3 2

3 V3 4 1 -- -- -- V1 V2 V4 V3 V5
6
V4 0 6 0 -- --
V5
V5 0 3 0 0 --
V4

(a)

V1 V(241)
V1 V24 V3 V5
5 4 V(24)
V1 -- -- -- --
1 V3 V24 5 -- -- --

3 V3 4 1 -- -- V1 V2 V4 V3 V5
V24
V5 0 3 0 --
V5

(b)

V(2413)

V241 V(241)
V241 V3 V5
V(24)
V241 -- -- --
4 V3
V3 4 -- --
V1 V2 V4 V3 V5
V5 3 0 --
3 V5

(c)

V(24135)

V2413 V(2413)

V(241)
V2413 V5
V(24)
V2413 -- --

V5 3 --
3 V1 V2 V4 V3 V5
V5
3
 (d)

Figure 3.7 : Cluster tree formation

a b c

3 4 1 2 5

d e f

(a) f c a e d b

Criterion B

a b c
3
First cutline

2 1 5 4

c e f b a d
d e f b

(b)

{ f, c} {d}

5 1

2
{ a, e} {b} { a, e} { f,c} {b} { d}

(c)
 4
{ c, e} { a,
d}

5 1

{f } {b} { c, e} {f} {a ,d} {b}

(d)

5
{f, c} {a,e,d}
Second
Cutline
3 2

{ b}
{a,e,d} {f, c} { b}
f c a e d b

(e)

Figure 3.8 Clustering based on a) criterion A only, b) criterion B only, c) Criterion A below the first cut-
line, then criterion B, d) criterion B below the first cut-line, then criterion A e) criterion A below the second
cut-line, then criterion B
 Figure 3.9 Two-way partition
Cutline
Cutline

vj
vi vj
vj
G2
G1
G2
G1

Figure 3.10 Interconnection reduction by node interchanging: a)before interchanging vi and vj, b) after
interchanging vi and vj

40

20

10

1 2 3 4 5 6 7 8 9 10
10

Figure 3.11: Kernigham-Lin Search Strategy

 b c
a

o1 O2
(+) G1 (+)
e13 mult1
add1
G1 G2 e13 e23
e23
O3
(*) G3

Figure 3.12 (a) two cluster partition

b c
a

o1o oO22
1
(+) (+)
(+) (+)
e13 mult1
add1
G1
G3 e13 e23
add2
O3
G2 e23 (*) G3

Figure 3.12 (b) three cluster partition

CHAPTER 4
Scheduling in High level Synthesis

While (x<a) do
{
x1:= x + dx;

u1:= u – (3 * x * u * dx) – (3 * y * dx);

y1:= y + (u * dx);

x:= x1; u:=u1; y:=y1;

Figure 4.1(a) Text description

u dx 3 x u dx x dx

v10
* v1 * * +
v2 v4
e1,5 e2,5 e4,9 y
y
e10,11
* * + v9
u v5 v3 a
e5,7 dx
e3,6
< v11
- * v6
v7
e7,8 e6,8
c
-
v8

Figure 4.1 (b) DFG (Data Flow Graph)

 V1 V2 V3 V4 V10 V1 V2
L=1
* * * * + * *
E=1

E=2 * V5 + V9 < L=2 * V5 * V3

* V6 V11

E=3 V7 L=3 V7 V6 V4 V10

- - * * +

E=4 V8 L=4 V8 V9 V11

- - + <

(a) (b)

Figure 4.2: (a) ASAP schedule, (b) ALAP schedule.

1 2 3 4 5 6 7 8 9 10 11
V1 V2
S1 S1
* *

S2
S2 * V5 * V3 + V10

S3 S3 V7 V6 V4
- * *

S4 V8 V9 V11
S4 - + <
(a) (b)

Figure 4.3: An ILP scheduling example: (a) ranges for operations, (b) final schedule,
 -------------------------------------------------------- ---------------------------------------

S1 1 2 3 4 10 2.83
* *
*

* * +
S2 5 2.33
*
<
S3 7 6 0.83
- +

-
S4 8 9 11 0.00

(a) (b)

S1 2.33
* 1 * 2

S2 + 2.33
* * *
5 3

S3 < 1.33
- 7 * 6 4 10
+
S4 0.00
- 8 9 11

(c) (d)

Figure 4.4: Force-directed scheduling example: (a) probability of scheduling operations

into control steps, (b) operator cost for multiplications in a, (c) probability of scheduling
operations into control steps after operation o3 is scheduled to step s2, (d) operator cost
for multiplications in 4.4c. '
 S1
1 2 3 4 10
S1 1 2 3 4 10
S2 5 6 9 11
S2 5 9 11
S3 6
7
S3
7
S4
8
S4
8
(a) (a) initial schedule where three operations are movable to five control
Figure 4.5: Rescheduling:
steps (dashed arrows), (b) after operation 6 is moved and locked. (b)

* * Plist* = 1<0>, 2<0>,3<1>, 4<2>

<0> <0> <2> * + <2> Plist+ =10<2>
Plist- = NIL
<0> * <1> <2> + < <2> Plist< =NIL
*
(b)
<0> - * <1>
Resources* = 2
Resources+ = 1
-
<0> Resources- = 1
Resources< = 1
(a) (c)

* * - + <

* * +
S1 1 2 10

S2 * * <
5 3 11

S3
* 6 * 4 - 7

S4
- 8 + 9

(d)
Figure 4.6: List scheduling: (a) a DFG with mobility labeling (inside < > ), (b) the list of
ready operations for control state s1, (c) the resource constraints, (d) the scheduled .DFG
 * 2 * 4 * 10 + Node 8 9 11 7 6 4 10 5 3 1 2
1
ALAP 1 1 1 2 2 2 2 3 3 4 4
* * + < ASAP 4 2 2 3 2 1 1 2 1 1 1
5 3 9 11
Priority 1 2 3 4 5 6 7 8 9 10 11
-
7 * 6

-
8
(a) (b)

* 2 * 1 + 10 S1 * 2 * 1 + 10

* * * * <
3 5 S2 3 5 11

* * -
S3
4 6 7
- +
S4 8 9

(c ) (d)
Figure 4.7: Static-list scheduling: (a) a DFG (b) priority list, (c) partial schedule of five nodes, (d) the final
schedule.
 S1 +

S1 +
S2 - * *
S2 -

(a) (b)

S1
*
+ S2
S1 * *
S3
-

(d)
(c)
Figure 4.8: Scheduling with arbitrary-delay units

a:=a+1;

if(a>100) then

b:=a/c;

else

b:=d/c;

endif

c:=c-g;

Figure 4.9: CDFG for a behavioral description with a conditional construct.

 time

b
1 2 3 4 5 6 7 8 9 10 11 12

(a)

1, 2, 3 4, 5, 6 7, 8, 9 10,11, 12

(b)

1 4 7 10

p 2 5 8 11

3 6 9 12

(c)

ALU1 ALU2 ALU3

v1=v2+v3 v4= v2*v3 S1

v5=v1+v4 v6=v4/v1 S2
v2=v4*v5 S3

(a)
ALU1 ALU2 ALU3

v4=v2*v3 v1= v2+v3 S1

v5=v1+v4 v6=v4/v1 S2
v2=v4-v5 S3

(b)
 ALU1 ALU2 ALU3

v4=v2*v3 v1= v2+v3 S1

v5=v1+v4 v2=v4-v5 v6=v4/v1 S2
S3

(c)
Figure 4.11: Scheduling using simulated annealing : (a) an initial schedule, (b) after
swapping two operations, (c) after displacing an operation.
 ipp<=pc
1
1 1
write

2 ipo<=oldpc
2 2

3 outbus,=inbus + 8
3 3
jump
if( jump = ‘1’) i2
4
4 4
5 then pc<= jumppc
5 5
6 endif
6 6

i1
7 wait until (cond=’T’)
7 7
loop
8 oldpc<= pc
8 8

write
9 pc< = pc + 8
9 9

10
10 10

Figure 4.12: Path-based scheduling: (a) an example CDFG, (b) a path in the CDFG with
constraint intervals, (c) scheduled CDFG.

4.5.3 DFG Restructuring

a b c d e f a b c d e f

+ 5 + 5
+ 1 + 1

+ 2 + 2
+ 3

4
+ 3 +

+ ((a + b) + c) + (d + (e + f))
4

(((a + b) + c) + d) + (e + f)
(b)
(a)

Figure 4.13: DFG restructuring : (a) DFG (b) DFG after tree-height reduction
 a b d c a b d c

+ 1 + 1

2 2
+ + 6 +

* *
3 3

+ 4 + 5
+ 4

+ 5

d (a + b + c) + (a+b) + (a+b) d (a + b + c) + 2(a+b)

(c) (d)

Figure 4.13: DFG restructuring: (c) DFG (d) DFG after redundant operation insertion.
CHAPTER 5
Data Path Allocation in High Level Synthesis

a b c d

o1 o2 r1 r2 r3 r4
+ + a b ,e, g c ,f, h d
S1
e f
S2 o3 + o4
+ +1 +3 +2 +4

g h Add1 Add2

Figure 5.1: Mapping of behavioral objects into RT components.

 a b c d

O1 O2
S1 + + r1 r2 r3 r4
e f
a b, e, g c, f, h d

S2 O3 O4
+ +

+1 +4 +2 +3
g h
ADD1 ADD2

(a)
(b)

r1 r2 r3 r4
a ,g b, e c, f d,h

+1 +4 +2 +3

ADD1 ADD2

(c)

r1 r2 r3 r4
a ,g b, e c, f d,h

+1 +3 +2 +4

ADD1 ADD2

(d)
Figure 5.2: Interdependence of functional-unit and storage binding

S1 S2 v2 Edge Common
v1 Neighbor
v2
v1 e11,3 1
e11,4 1
e12,3 0
v3 v4 v5 S3 S4 S5 e12,5 0
v3 v4 v5 e13,4 1
e14,5 0
(a)
(b)
S13 S2 Edge Common
Neighbor
v2 e113,4 0
v1 e12,5 0
e14,5 0
S4 S5

v3 v4 v5

(c)
S134 S2 Edge Common
Neighbor
v2

v1 e12,5 0

S5
v5
v3 v4

(d)
S134 S25 Cliques:

S134 = { V1, V3, V4 }

v1
v2
S25 = { V2, V5}

v3 v4
v5

(e) (f)

Figure 5.3: Clique partitioning example

 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11
V1 V2
R
S1 V6 * V4
V3 W
R
S2 V10 + /
V5 W
V7 R
S3 - - *
W
V11 V8 V9
S4 R
+ -
W
V1 V2
(a) (b)

v8 Cliques:
{v1,v8}=r1
{v2,v3,v9}=r2
v10 {v4,v5,v11}=r3
v1 {v6,v7}=r4
v2 {v10}=r5
v9 v7

v11 (d)
v3 v5

v4
v6

(c)
Figure 5.4: Register allocation using clique partitioning: (a) a scheduled DFG, (b) lifetime intervals of
variables, (c) the graph model for register allocation, (d) a clique-partitioning solution

V1 V10 V4 V6 V2 V3 V5 V7 V8 V9 V11 V1’ V2’ r1 r2 r3 r4 r5

S1 V1 V10 V4 V6 V2

V3
S2

V5 V7
S3

S4 V8 V9 V11

V1 V2

Figure 5.5: Register allocation using the left-edge algorithm: (a) sorted variable lifetime intervals, (b) five-
register allocation result.

V1 V10 V4 V6 V2 V3 V5 V7 V8 V9 V11 V11 V12

S1

S2

S3

S4

Cluster 1 Cluster 2 Cluster 3 Cluster 4

(a)
 r1 v1
v3
v10 r1 = { v1 , v8 , v11}
r2 r2 = { v9 , v10 }
v4 r3 = { v4 , v5 , v11}
v5 r4 = { v6 , v7 }
r3 r5 = { v2 , v3 , v12}
v6
r4
v7
v2
r5

Set R Set V
(b)
Figure 5.6: Weighted bipartite-matching (c) intervals with clusters, (b)
for register allocation: (a) sorted lifetime
bipartite graph for binding of variables in Cluster2 after Cluster1 has been assigned to the registers, (c)
final binding of all variables to the set of registers.
CHAPTER 6
LOGIC SYNTHESIS

10 11

0 1

00
01
(a) (b)

100
m4 110
m6

101 111
m5 m7

000 010
m0 m2

001 011
m1 m3

( c)
Figure 6.1 Cubic representation of a boolean function of (a) one variable (b) two variables and ( c) three
variables.
 A

m4

m7

m0 m2
B

m3
C
FIGURE 6.2 A cubic representation of the function F(A, B, C) = ? m(0, 2, 3, 4, 7).

m4

m7
x00
m0 0x0 m2
B

FIGURE 6.3 A cubic representation of the function G(A, B, C) = A1C1 + B1C1 + ABC.
 A
m6

X1X

m7
m2
B

m3

C
Figure 6.4: A cubic representation of the function H(A, B, C) = B.

F(xi)

xi F= xi F(xi) + x1i F(x1i)

F(x1i)

x1i
(a)
1
F (xi)

x1i F= [x1i + F1(xi)][ xi +F1(x1i)]

F1(x1i)

xi
(b)

Figure 6.5 An expanded function F, represented (a) in NAND-NAND logic, and (b) in NOR-NOR
logic.
 F

A 1
0

B B 1
0
0 1
D
C C
C 0 0 1
1 1
1 0 1 0
D

Figure 6.6: A binary tree representation of the function F = A(BD + B1C1) + A1( BC1 + B1CD).

Y=A+B Y
Y=AB

A 1 A
A
1
1
0 0
0
1
B Y=1 B B
B 1
0 0
Y=0 0 0
Y=1
Y=0 Y=
Y=1 Y=0
Y=0 Y=1

(a) (b)
(c)
Figure 6.7 Binary decision diagram of the functions (a) AB (b) A+B and (c) A(+) B.
 A 1
0
1
3
2 B
B 1
1 0
0 7
5 6
4 C C
C 1 1
C 1 1 0
0 0
0

m0 m1 m2 m3 m4 m5 m6 m7

0 A 1
A 1
0 2 3
B B
1 1 1
3 0
2 B 0
B 1
1 4,7 5,6
0 C C
0 7
5 6 1
4 C C
C 1 1 0 1 0
C 1 1 0
0 0
0
0 1
0 1 1 0 1 0 0 1

(a) (b)

FIGURE 6.9: Realization of the function Y = A (+) B (+) C (a) The binary tree; (b) the tree reduced to the
BDD,
 A 1
0
1
3
2 B
B 1
1 0
0 7
5 6
4 C C
C 1 1
C 1 1 0
0 0
0

1 0 1 0 0 0 1 1

(a)

Y Y Y

A A A
0 0
0
2
B B
1
0 0 1
4 5 4,5
C C C
C 1 1
0 1
0 0

1 0 1 0 1 0
1 0

(b)
 Y

A
0 1

C B

0 1 0 1

1 0 0 1
(c)

Figure 6.10 Realization of the function, Y(A, B, C) = ? m(0, 2, 6, 7) (a) The binary tree (b)
reducing the tree(c) the BDD.

A 1

0 0 B

C
1
1

D
0
1
0

E
1

0 F
0 1

0 (a) 1
 F

C
C

E
E E E

B B
B B

D D

0 (b) 1

Figure 6.11: BDD illustrating (a) Advantages of a good ordering, (b) Drawbacks of a bad ordering

A 1
0
1
3
2 B
B 1
1 0
0 7
5 6
4 D D
D 1 1
D 1 1 0
0 0
0

0 1 0 1 0 1 1 1

(a)
 Y

A 1
0
1
B
B 1
0
0
1
D 1
D 1 1
0
0

0 1 0 1

(b)

Y Y

A A
1 1

0 1
- B - B

0 1 1 1
D D

0 1 2 2 1
1

0 0
(c) (d)
FIGURE 6.12: Realization of the function Y = AB + D. (a) The binary tree; (b) reducing the tree; (c) the
BDD; (d) counting the paths to an output.
 Y Y

A 1
D
0 1
1
3
2 B 1
B A
1 1 1
0
0 7
5 6 0
4 D D
D 1 1
D 1 1 0 B
0 0 0 1
0 0

0 0 0 1 1 1 1 1 1
0

(a)
(b)

FIGURE 6.13: The BDD for the function Y = AB + D, with D the most significant bit. (a) The binary tree;
(b) BDD.

0 A 1
1 A 1

C 0 B
C 1 B
1
2
D 1
D 1
0
1 2
0
2
2

0 1
0 1

(a) (b)
FIGURE 6.14: Realization of the function Y = AB + CD. (a) The BDD; (b) the number of paths to an
out put.
 IF IF IF

A A A
ELSE THEN ELSE THEN ELSE THEN

0 B B 1 B B
FIGURE 6.15: If-then-else diagrams of (a) AB, (b) A + B, and (c) A (+) B.

IF IF

A A IF
ELSE THEN
ELSE
THEN

C B 1 B
THEN
ELSE

0 D

FIGURE 6.16: If-then-else diagrams of (a) AB + A1C and (b) ABD

 F G

a B C THEN a
THEN
ELSE ELSE

1 b c 0
THEN ELSE THEN ELSE

1 0 1 0

I
H

THEN a
b D ELSE
THEN
ELSE

C b
1 d THEN ELSE

THEN ELSE

0 D
1 0

AND OR
plane plane

F1 F2
Register Register

Inputs Outputs
FIGURE 6.18: The basic floor plan of a PLA structure.

VDD VDD

GND GND
VDD
GND
P0

P1

P2

P3
GND

VDD F2 F2

F1 F1
FIGURE 6.19: A stick drawing of an NMOS NOR-NOR PLA realization.

I0 I1 I2 Y0 Y1 Y2
 A A1 B B1 C1 C D1 D Y1 Y2 Y3
P1=A1BC Y1=P1+P2
Y2=P1+P3+P4
P2=AB1D1 Y3=P2+P3
Y4=P4+P5
P3=A1C1D1 Y5=P5+P6
Y6=P4+P6
P4=CD1E

P5=CEF1

P6=E1FG1

E1 E F1 F G1 G D1 D Y4 Y5 Y6
FIGURE 6.20: A column custom-folded PLA. (a) AND-plane column-folding; (b) OR-plane column-
folding.

Inputs Outputs Inputs

I1 I2 I3 Y1 Y2 Y3 Y4 I7 I8 I9 I 10
P1 P5

P2 P6

P3 P7

P4 P8

I1 I4 I5 I6 Y5 Y6 Y2 Y7 Y3 Y8 I11 I12 I9 I 10

AND Plane OR Plane AND Plane

FIGURE 6.21: A row or product-line folded PLA.

. .
 1 2 3 4 5 6 7 8 9 10
P1 AB1

P2 AC

P3 D

P4 A1B

P5 B1C

A1 A B1 B C1 C D1 D Y1 Y2

(a)

A B1 C D

P1 AB1

P2 AC

P3 D

P5 B1C

P4 A1B

A1 B C D Y1 Y2
(b)

Figure 6.22: A simple PLA implemented (a) directly, and (b)optimized

 A
B1 d
? Y
C ß
D ? X
E1 W
V

(a)

VDD

1i

2i 3i

GND

(b)

FIGURE 6.23 (a): Multilevel NOR diagram of the function Y = A’B’ + C’(D + E’) (b) a typical NMOS
NOR gate.
 0/0
0/0

0/0 0/0
1/1
1/1
1/1 0/0 1/1
1/1

0/0
1/0

0/0
0/0
Figure 6.25 An FSM with redundant states and its minimized version.
CHAPTER 7

PHYSICAL SYNTHESIS

Circuit
Design

Partitioning

Floorplanning &
Placement

Routing

Compaction

Extraction &
Verification

Fabrication

Figure 7.1: Physical design cycle

 6 1 7

B
A 8 H I
C 2
3

D E F G

5 4
(a)
1

2 3

4 7
5 6

F G H I D E A

B C
(b)

H H

V V V V

H
F G H I D E A

B C

(c )
 D
d

A c

a
C
b
B

( d)
Figure 7.2: Floorplan with slicing tree and a non— slicing floorplan.

Fig 7.37.3:
Figure (a)Interconnection
Steiner treetopologies.
(b) minimum spanning tree (c) complete graph

(a) Global Routing (b) Detailed Routing

Figure 7.4: Phases of routing.
 6 5 4 3 4 5 6 7
5 4 3 2 3 4 5 6
4 3 2 1 2 3 4 5
5 4 3 2 3 4 5 6
6 5 4 3 4 5 6 7
7 6 5 4 5 6 7 8

8 7 6 5 6 7 8 9
9 8 7 6 7 8 9 10

Figure 7.5: A net routed by Lee’s algorithm.

obstacle

Figure 7.6: A net routed by Mikami-Tabuchi’s Algorithm

obstacle

Figure 7.7: A net routed by Hightower’s Algorithm

 1
3
3
4 2

2
1

(a) (b)

1 Switchbox 1

2 2

(c) (d)

Figure 7.8: Channels and Switchboxes

7.4.2.1 Problem Formulation

(a) (b)

Figure 7.9: (a) Grid-based. (b) Gridless

 Track2 Track 3

Track1 Track 2
Track 1

Layer1

Layer2

Track 1 Layer3

Via

Unreserved Layer Model

Figure 7.10: A comparison between HVH, VHV, and unreserved layer models.

1 4 2 0 2 1 1 0 3 4 0

upper boundary lower boundary Terminal

3 0 1 2 0 3 4 0 0 2 3

Net list: 14202110340

30120340023

Figure 7.11: A channel and its associated net list.

upper boundary terminals via

Tracks

Dogleg

Lower boundary trunks branches

Figure 7.12: Terminology for channel routing problems.

1 5 2 0 2 1 1 0 3 4 0

3 0 1 2 0 3 4 0 0 2 3

(a)

4
3
(b)
Figure 7.13: A routing problem and its HCG .
 1 5 2 0 2 1 1 0 3 4 0

3 0 1 2 0 3 4 0 0 2 3

(a)

4
3
(b)

Figure 7.14: A channel routing problem and its VCG.

.
The figure 7.15 (a) shows a channel routing problem with a vertical constraint
cycle while figure 7.15 (b) shows how a dogleg can be used to break a vertical constraint
cycle. Figure 7.15(c) shows vertical constraint cycle involving four nets. In figure 7.15(d),
we show one possible routing for the example in figure 7.15(c).
1 2 1 2

2 1 2 1
(a) (b)

4 1 2 3

1 2 3 4
(c)
 4 1 2 3

1 2 3 4
(d)

Figure 7.15: A cyclic vertical constraint.

4
3

Figure 7.16: A combined constraint graph (CCG)

7.4.2.5 Left-edge Channel Routing Algorithm

 7.5 Compaction

C
A
A F
F
C

B
E
D
B E
D

Figure 7.17: Constraint graph generation

v3 ?

v2 ?
1
5

? v4
2
v0 ?

4
1
v1 ?

2
? v5 Fig 7.18: Input DAG

Q P1 P2 P3 P4 P5 x1 x2 x3 x4 x5
“not initialized” 1 2 1 2 1 0 0 0 0 0
{v0} 0 1 1 2 1 1 5 0 0 0
{v1} 0 0 1 2 0 1 5 0 0 3
{v2,v5} 0 0 0 1 0 1 5 6 6 3
{v3,v5} 0 0 0 1 0 1 5 6 6 3
{v5} 0 0 0 0 0 1 5 6 7 3
{v4} 0 0 0 0 0 1 5 6 7 3
Table 7.2:Results of Longest Path algorithm
.

v3 ?

v2 ? -1
1
5

? v4
2 -3
v0 ?

4 -4
1
v1 ?

2 v5
?
Fig 7.19: DAG with a few backward edges

Step x1 x2 x3 x4 x5
Initialize -8 -8 -8 -8 -8
Forward 1 1 5 6 7 3
Backward 1 2 5 6 7 3
Forward 2 2 5 6 8 4
Backward 2 2 5 7 8 4
Forward 3 2 5 7 8 4
Backward 3 2 5 7 8 4
Table 7.3:Results of Liao-Wong algorithm
APPENDIX A
VHDL BASICS

A
? Y
?

? B
F
Figure A.1(a)

A
? ? Y

G ? F
? B
A
? Y
? ?
? B
I
A
? Y
?
? ? B
H

(b)
Figure A.1: Example of structural description.
 COUNT2
BIT_0
T_FLIPFLOP Q0
CLK FF0
? CLK Q ?

BIT_1
INV T_FLIPFLOP
Q1
INVERTER INV_FF0 FF1
A Y CLK Q ?

Figure A.2 Structure of count2

.

Graph Theory Basics

A B

C
D E

Fig. B.1 A graph

0 1 0 0 1
1 0 1 1 0
0 1 0 0 1
0 1 0 0 1
1 0 1 1 0

Fig. B.2 Adjacency matrix representation

 A B E NULL

B A C D NULL

C B E NULL

D B E NULL

E A C D NULL

Fig.B.3 Adjacency list representation

V1
V5 V2 V3
V2 V2 V4 V5
V4
V3
V1 V4 V3
V3
V5
(a) (b)
Fig B.4: A directed graph (a) and its adjacency list representation(b).

When this algorithm is applied on graph shown in Fig B.4, the algorithm takes different
steps as shown in table BT.2

Q W Edges processed
(V1) V1 (V1 , V2) ,(V1 , V3)

(V1 , V2) V2 (V2, V4) ,(V2 , V5)

(V3 , V4, V5 ) V3 NULL

(V4, V5 ) V4 (V4 , V3)

(V5) V5 NULL
Table BT.2: The different steps of the breadth-first search algorithm applied to the graph
of figure B.4

V1 2 V6

6 1 3 1
V2 V5
2 1 1
1 V4
V3 5

Fig B.5 : An edge-weighted directed graph.

Iteration T vi .distance, for i =

1 2 3 4 5 6
1 { V1 } 6 8 1 3 8
2 { V1 , V4} 6 6 2 8
3 { V1 , V4, V5} 6 6 3
4 { V1 , V4 ,V5 ,V6} 4 6
5 { V1 ,V4 ,V5 ,V6 ,V2} 5
6 { V1 ,V4 ,V5 ,V6 ,V2 ,V3}

Table BT.3: The evolution of the distance attributes in Dijkstra’s algorithm when applied
to the graph with vs = v1 and vt=v2

.
2 V2 2 V2

1 5 1
V1 4 V3 2 V5 2 V1 V3 2 V5

2 1
1
3 V4 V4
Fig B.6 An edge-weighted undirected graph(a) and its minimum spanning tree (b).
 Iteration U
Vi .distance, vi .via_edge, for i =
1 2 3 4 5
0 V1 2, (V1 ,V2) 4, (V1, V3) 3, (V1, V4 ) +8 ,?
1 V2 1, (V2, V3 ) 2, (V2, V4 ) 5, (V2, V5 )
2 V3 1, (V3, V4 ) 2, (V3, V5 )
3 V4 2, (V3, V5 )
4 V5

Table BT.4: The evolution of Prim’s algorithm when applied to the graph of figure B.6a.