5th CHAPTER

POWER P-i-N DIODES

1
P-N Diode

2
 Power P-i-N Diode - 1
Anode
i
10
P+ 19 -3 microns
N = 10 cm
A
breakdown
v Drift region / layer14 -3 voltage
N- epi N = 10 cm
D dependent

19 -3
N+ substrate N = 10 cm 250
D
microns

Cathode

anode
The drift layer is the
i
trademark of power devices.
v Every power device has a
v

drift layer!
cathode
3
 Power P-i-N Diode - 2
Anode
i
10
P+ 19 -3 microns
N = 10 cm
A
breakdown
v Drift region / layer 14 -3 voltage
N- epi N = 10 cm
D dependent

19 -3
N+ substrate N = 10 cm 250
D
microns

Cathode

• Thousands of Amperes on-state current

• Thousands of Volts breakdown voltage
• Not simultaneously
• LIGHTLY DOPED DRIFT LAYER IS THE ESSENCE OF
POWER DEVICES – it has the role to absorb the depletion layer of
the (P+) – (N-) junction, in off-state
4
POWER P-i-N DIODES
I-V CHARACTERISTICS

5
 Power P-i-N Diode Characteristics

OFF-STATE ON-STATE
OFF-STATE ON-STATE

6
 Nearly Ideal vs Non-Ideal Characteristics
I (V A )

I S 0 = I Sn + I Sp

A – Reverse Breakdown VA
B – Optical &Thermal generation
C - Depletion region recombination / I F
Space charge generation current
D - Ideal forward current / Low-level
E
injection current D
E – High-level injection current
F - Series Resistance C
VA
B
A
7
POWER P-i-N DIODES
ON-STATE

8
 ON-STATE – Conductivity Modulation
• In on-state, holes are injected in the
drift region from P+, while electrons
are attracted in the drift region from
x N+ → double injection →
conductivity modulation
+ DRIFT
P
+ - N+
N - • Diffusion Length: L = Dτ, where D is
the diffusion coefficient (specific to
W every material and type of carrier)
d and τ is lifetime
p(x) = n(x) log scale • If Wd ≤ excess carriers diffusion
16 length La → carrier distributions in
=n =
a 10 drift region is p(x) ≈ n(x) ≈ na

p (x) • For na >> N- (drift region doping),

n p(x) 14 n
n no= 10 the resistance of the drift region
p becomes quite small → conductivity
no modulation
n 6
po p = 10
no
x • On-state power losses are mainly
given by the dissipation in the drift
region. Conductivity modulation
significantly reduces power losses.
9
 Drift Region On-State Voltage Drop

• Current can also be regarded with

DRIFT respect to the drift charge:
W
d
x

• QF is the extra charge stored in the

drift region
+ + -
P N - N+ • Vd is the voltage drop on the drift
IF
region, Vj is the voltage drop on
+ V - + V -
j d the (p+) - (n-) junction
Cross-sectional
area = A

10
 Drift Region On-State Voltage @ Large Currents - 1

• At large na (> 1017cm-3), lifetime starts to decrease due to Auger recombination

(“An electron and a hole recombine, but rather than emitting the energy as heat or as
a photon, the energy is given to a third carrier, called Auger carrier” -
http://www.pveducation.org
• Auger recombination is the opposite effect to the impact ionization effect
• Auger recombination is highly important at high doping levels (> 1017cm-3)

• τ0 is the lifetime at n = nb = 1017cm-3

11
 Drift Region On-State Voltage @ Large Currents - 2

• At large na (> 1017cm-3), the mobility of both electrons and holes starts to decrease
due to carrier-carrier scattering (collision between carriers)

• µ0 is the mobility at low injection level

12
 Drift Region On-State Voltage @ Large Currents - 3

• Since JF is large:

13
 On-State Losses - Conclusions
• For power diodes, on-state losses are largely given by the voltage drop on the drift
region
• If lifetime, τ, is high enough (such as Wd ≤ high level diffusion length La), then the
voltage across the drift region is quite small, and, for injection levels lower than
1017cm-3, is even current independent:

• The price to pay for reduced voltage across drift region is the large amount of charge
stored in the drift region → large turn-off time
• The larger BV, the larger the voltage drop across drift region (since large BV
means large Wd)
• Ex: for µn+µp = 900cm2/Vs, na = 1017cm-3, Ecritical = 2x105V/cm, non-punch through

14
On-State Characteristic

15
 Nearly Ideal vs Non-Ideal Characteristics
I (V A )

I S 0 = I Sn + I Sp

A – Reverse Breakdown VA
B – Optical &Thermal generation
C - Depletion region recombination / I F
Space charge generation current E
D - Ideal forward current / Low-level
injection current D
E – High-level injection current
F - Series Resistance C
VA
B
A
16
 C - Depletion Region Recombination

• This is the same physical process as B, except that it occurs in forward

bias and it is due to recombination rather than generation.

• This manifests itself on the I-V characteristics as a different slope

I F
E
D
C
VA
B
A
17
 E – High Level of Injection

• When high forward biases are applied, the injection level can be very
high – higher than the doping in the lightly doped side.

• This situation is quite complex, but in order to maintain charge

neutrality both minority and majority concentrations are increased.

I F
E
D
C
VA
B
A
18
POWER P-i-N DIODES
OFF-STATE

19
 Nearly Ideal vs Non-Ideal Characteristics
I (V A )

I S 0 = I Sn + I Sp

VA
A – Reverse Breakdown
B – Optical &Thermal generation I F
C - Depletion region recombination E
D - Ideal forward current
E - High Injection region
D
F - Series Resistance C
VA
B
A
20
 B – Optical & Thermal generation

• Carriers generated in depletion region are swept out by high field.

• Optically generated carriers are caused by absorption of photons

• Thermally generated carriers are by thermal ionization

I F
E
D
C
VA
B
A
21
 A - Reverse Breakdown - 1
• For an abrupt 1-D junction, breakdown occurs at VBR - when the electric
field is strong enough to cause impact ionization.

• Impact ionization: for E ≥ EBD, a free electron can acquire, between lattice
collisions (tc ≈ 10-12 sec), from the electric field, sufficient kinetic energy to
break a covalent bond. The newly liberated electron can follow the same
process → cascade (avalanche) of electrons → large current

Si
- -
I
- Si F
-
E
- D
Si
C
Electric field E - VA
B
A 22
 A - Reverse Breakdown - 2

• Eg = band gap (1.1eV for Si)

• m = electron mass = 10-27g
• q = electron charge = 1.6 * 10-19C
• tc = average time between collisions of electrons with lattice = 10-13s
• VBR = BV = breakdown voltage

I F
E
D
C
VA
B
A
23
 Power P-i-N Diode

• A depletion layer, also

Anode Drift Cathode called space-charge
limited area / layer,
n- exists between p+
region and drift region
even when VAK = 0

24
Breakdown Voltage (BV) in a p-(n-) junction
• As the reverse bias (VR) increases:
➢ The depletion region extends
Drift (especially in the n- region)
- ➢ The maximum electric field
(EMAX) increases

• When EMAX = ECRITICAL, VR = BV

and breakdown occurs
• Breakdown occurs when impact
ionisation is triggered
• ECRITICAL is characteristic for each
semiconductor
• ECRITICAL might be also called
breakdown field
• For Si, ECRITICAL = 0.3MV/cm
• For 4H-SiC, ECRITICAL = 2.4MV/cm
• For GaN, ECRITICAL = 5MV/cm
• For diamond, ECRITICAL = 10MV/cm

25
Non-Punch-Through (NPT) Power P-i-N Diode - 1

• NPT means that the

drift layer width, Wd, is
longer the depletion
layer width at
Drift breakdown (VR = BV)

n-
• In other words, NPT
means that the depletion
layer has not punched-
through / reached-
through the drift layer to
the N+ substrate at
breakdown (VR = BV)

• BV depends on drift
doping

26
 Non-Punch-Through (NPT) Power P-i-N Diode - 2
• If the width of the drift layer, Wd, is longer than the depletion layer
width at breakdown, then the structure is called NON-PUNCH-
THROUGH (the depletion layer has not punched-through / reached-
through the drift layer to the N+ substrate)

• For Si:

• In terms of drift layer thickness, Wd:

27
 Non-Punch-Through (NPT) Power P-i-N Diode - 3

• BV depends on drift doping, ONLY

• Large BV means low ND
• Large BV means large Wd
• Example in the case of Si:

• For BV > 1000V, ND needs to maximum 1014cm-3, while Wd needs to

be at least 100µm

28
Punch-Through (PT) Power P-i-N Diode - 1

• PT means that the

Drift
drift layer width,
Wd, is smaller than
the depletion layer
width at
breakdown (VR =
BV)

• In other words, PT
means that the
depletion layer has
punched-through /
reached-through
the drift layer to
the N+ substrate at
breakdown (VR =
BV)
29
Punch-Through (PT) Power P-i-N Diode - 2
- V +

P+ N- Drift N
+

W
d
Electric
E + E2 field
1
V
1
E
2
V2
x

30
 Punch-Through (PT) Power P-i-N Diode - 3
- V +

P+ N- Drift N
+

W
d
Electric
E + E2 field
1
V
1
E
2
V2
x

• BV depends on BOTH drift doping and drift width. 31

 PT vs NPT Power P-i-N Diode

• For Si and BV = 600V

➢ NPT requires Wd = 45µm and ND = 4*1014cm-3
➢ PT requires Wd = 25µm and ND = 5*1013cm-3

• Drift resistance is higher for PT due to reduced doping (which has

a stronger effect on resistance than the increased width)

• For unipolar power devices (Ex: MOSFETs), the NPT

configuration is preferred

• For bipolar power devices (Ex: BJTs, IGBTs, Thyristors), the PT

configuration is preferred

32
 POWER P-i-N DIODES
TURN-ON and TURN-OFF
aka: SWITCHING

33
 Disclaimer

• All the following reasoning on power p-i-n diode switching is made

under the assumption that the diode is part of a circuit and that it is
turned on and off by injecting a forward and a reverse current,
respectively.

• Therefore, the on-state and off-state behavior described in the

previous chapter needs time to get in place. We call these periods of
time:
➢ Turn-on time (t1 + t2)
➢ Turn-off time (t3 + t4 + t5)

34
 Diode Switching Waveforms
Qrr = I t / 2
rr rr

di / dt d i / dt
F I F R 0 .2 5 I
rr

I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4

• Turn-on: Switch from off-state (reverse bias) to on-state (forward

bias): t1 + t2
• Turn-off: Switch from on-state (forward bias) to off-state (reverse
bias): t3 + t4 + t5 35
 Turn-on - 1
• Power diodes are typically used in power
di / dt
F I F

circuits where di/dt is controlled

• During t1: the space-charge located in the drift

region is removed (discharged). The depletion
layer is discharged to its thermal equilibrium
level V on
V
FP

• During t2: diode becomes forward biased,

t interval
2
excess carrier distribution in the drift region t
2
grows towards -the+ steady-state value that can
P+ - + N
- N+
t
1

be supported
i (t)
F
by- I+F, conductivity modulation
occurs
V - 1.0 V
j
P++ DRIFT N++
tim e
tim e
tim e

x
36
 Turn-on - 2
• Why VFP (peak forward voltage) occurs? di / dt

• IF increases → drift region voltage drop

F I F

increases (as it is no conductivity modulation

during t1, until space charge layer is discharged
to its thermal equilibrium level)
• Semiconductor wafer and bonding wires have
their own inductance (the larger di/dt, the larger
the impact of the inductance on VFP)
• When I = IF, the inductive contribution ends and V
FP
V on

conductivity modulation emerges

• Large di/dt minimizes t1
• Large IF and large drift carrier
t interval
2 lifetime increases t2 t
2

• Typically: +t1 – -hundreds

+ of ns; t2 – few µs t
1
P - + - N+
• Lower
i (t) turn-on N
- +time requires low drift carrier
F
lifetime which, in turn, increases on-state losses (VF)
V→ TRADE-OFF
j - 1.0 V

P++ DRIFT N++

tim e
tim e
tim e

x
37
 Turn-off - 1
• di/dt is controlled Q rr = I
rr
t
rr
/ 2

• Excess carriers indi

the drift region have to be
/ dt d i / dt
removed before the two junctions, I(P+)
F
F - R 0 .2 5 I
rr

Drift and Drift – (N+), become reverse biased t

• During t3, excess carriers are removed from
the drift region by means of recombination I
rr
• During t4, excess carriers are removed from
the drift region being swept out due to
negative current t
3
t t
5
4
• During t3 and t4, the voltage stays nearly
constant (small decrease due to Vohmic drops V on t
rr
due to reverse current) FP

• Irr = peak reverse recovery current

t
V
t V R
DRIFTt 2 t
rr

P++ 1 N++ S =
t
5

38
 Turn-off - 2
• During t3 and t4, there still is excess charge Q rr = I
rr
t
rr
/ 2

in the middle of the

di
drift
/ dt
region
d i / dt
• During t5, there is no excess charge atI Feither
F R 0 .2 5 I
rr

of the junctions; thus, they become reverse t

biased, the depletion regions at both junctions
rapidly increase and expand towards each I
other, thus voltage rapidly drops rr

• During t5, the negative current decreases

towards 0.25Irr and, after t5, towards 0. t t t
3 5
• During t5, large current and large voltage
4

exist simultaneously → high power lossesV @ on t

V rr
high frequency operation FP

• t5 ends at I = 0.25Irr
t
V
t V R
DRIFT t 2 t
rr

P++ 1 N++ S =
t
5

39
 Turn-off - 3
• trr = t4 + t5 – reverse-recovery time
• Qrr – reverse-recovery charge = that part of
Q rr = I t / 2
rr rr

QF swept out by the negative current, not by

di
F
/ dt
I F
d i
R
/ dt
0 .2 5 I
rr

internal recombination t
• S = Snappiness / Softness factor = t5 / t4
I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4

40
 Turn-off - 4
• Qrr < QF - there is also recombination
• La – diffusion length of drift excess carrier Q rr = I
rr
t
rr
/ 2

• Wd – drift region
d i length
F
/ dt
I
d i
R
/ dt
0 .2 5 I
F rr

I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4

41
 Turn-off - 5
Q rr = I t / 2
rr rr
• µn+µp = 900cm2/Vs, NPT
di / dt d i / dt
F I F R 0 .2 5 I
rr

I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4

• Formulas in bold are approximations obtained under certain assumptions:

• Abrupt junctions
• Depletion layer width is right below drift region width (NPT limit condition)
• Qrr = QF
42
 Switching – Conclusions - 1

• Most important parameters in turn-off: S, Irr, trr, Qrr

• S (t5 / t4) depends on Wd, diode doping levels (all 3), carrier lifetime
• Irr increases with IF and dIF/dt
• trr (t4 + t5) increases with IF
• trr decreases with dIF/dt
Qrr = I t / 2
rr rr

d i / d t d i / d t
F I F R 0 .2 5 I
r r

I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4 43
 Switching – Conclusions - 2
• For “normal recovery” / “soft recovery” diodes, S (t5 / t4 ) > 1 and trr
is few ms (line frequency rectifiers)
• For “snappy recovery” diodes, S << 1 and trr can be tens of ns (high
frequency rectifiers) – Drawbacks: large Irr and current & voltage
oscillations due to resonant circuit formed by stray circuit inductance
and diode depletion layer capacitance

44
 Switching – Conclusions - 3

• High BV means slower diodes

• Low turn-off time means large Irr

Qrr = I t / 2
rr rr

d i / d t d i / d t
F I F R 0 .2 5 I
r r

I
rr

t t t
3 4 5

V on t
V rr
FP

t
V
t V R
2 rr
t
t 5
1 S =
t
4

45