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UNIT-1

Q.1 Design CMOS transistor circuit for 2-input AND gate With the help of function table
explain the circuit. Nov.-2004, Nov.-2008, Feb.-2008

Q.2 Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGH
outputs.

Nov.-2004, March.-2006, Feb.-2008, Nov.-2008

Q.3 Explain the following terms with reference to CMOS logic

1)Logic levels 2)D.C. noise margin

3)Power supply rails 4)Propagation delay.

Nov.-2004, Feb.-2007, 2008, Feb.-2008, Nov.-2008,

Nov/Dec.-2009

Q.4 Design a CMOS transistor circuit that has the functional behaviour F(Z)= A.(B+C).

Nov.-2004, Nov.-2005

Q.5 Design a 4-input CMOS AND-OR-INVERT gate .Draw the logic diagram and function
table.

Nov.-2004, March.-2006,May/June.-2009, Nov.-2005

Feb.-2007, Nov.-2008,Nov/Dec.-2009

Q.6 Explain the effect of floating inputs on CMOS gate.

Nov.-2004

Q.7 Explain how a CMOS device is destroyed.

Nov.-2004, Nov.-2006, Feb.-2007

Q.8 What is the difference between transition time and propagation delay? Explain these two
parameters with reference to CMOS logic.

Nov.-2004, Nov.-2006, Feb.-2007, Feb.-2008, Feb.-2008

Q.9 Draw the circuit diagram of basic CMOS gate and explain the operation.
Nov.-2004, May.-2005, Nov.-2008, March.-2006

May/June.-2009
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Q.10 Design a CMOS transistor circuit with the functional behavior

F(X)= (A+B)(B+D)(A+D) May.-2005

Q.11 Design a CMOS transistor circuit with the functional behavior

F(X)= (A+B)(C+D). May.-2005

Q.12 Distinguish between static and dynamic power dissipation of CMOS circuit. Derive the
expression for dynamic power dissipation.

May.-2005

Q.13 Compare HC, HCT, VHC and VHCT CMOS logic families with the help of output
specifications with Vcc from 4.5 to 5.5 V.

May.-2005, Nov.-2005

Q.14 A single pull-up resistor to + 5V is used to provide a constant-1 logic source to 15

different 74LS00 inputs. What is the maximum value of this resistor? How much high-state D.C.
noise margin can be provided in this case?

Q.15 Design a CMOS transistor circuit that has the functional behave f(Z)=(A+B)(B+C) or
f(P+Q)(Q+R)

May.-2005, May/June.-2009, Nov.-2005, May/June.-2009

Q.16 Explain how to estimate sinking current for low output and sourcing current for high
output of CMOS gate

Nov.-2005, 2007, 2008, Set-2 March-2006, Set-1 feb.-2008,

Set-4, nov.-2008, Set-3

Q.17 Draw the logic diagram equivalent to the internal structure of an 2-input CMOS NAND
gate. Show the transistor circuit for this gate

and explain the operation with the help of function table

March-2006, Set-2

Q.18 Design CMOS transistor circuit for 3-input AND gate. With the help of function table
explain the circuit. March.-2006, Nov.-2007
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Q.19 What are the parameter that are necessary to define the electrical characteristics of
CMOS circuit? Mention the typical values of a CMOS NAND gate.

May/June.-2009, Nov.-2007

Q.20 Draw the Draw te CMOS circuit diagram of tri-state buffer .explain tge ciecuit with the
help of logic diagram and function table. may/june -2009

Q21 Design a CMOS transistor circuit that has the functional behavior as,f(a)=(P+Q).(Q+R)
Also explain its functional operation nov-2007

Q22 Deasign a CMOS transistor circuit that has the functional behavior
as,f(x)=(a+b)(b+c)(a+c) Also Draw the relavent circuit diagarams

Q23 A single pool-up resister to+5Vis used to provide logic source to15different 74LS00
inputs what is the maximum value of the resister ?how much high state D.C.noise margin can
be provided in this case? Feb(2008)

Q24 Draw the circuit for CMOS OR-AND logic state add explain its functioning clearly with
the help of function table. (feb-2008)

Q25 Explain about terms propagation delay with the help of wave form giving typical values
.using the expression for power consumption ,Explain the same for CMOS logic logic gate nov-
2009

Q26 Explain about the terms

i) Fan-in ii) Fan-out iii) Noise margin iv) propagation delay nov-2009

Q27 Draw the circuit for CMOS NAND and clearly explain about its functioning. (nov-2009)

Q28 Draw the Input-Output transfer characterister ofCMOS inverter and explain about the
various terms associated with the characteristics.Explain the terms noise margin. Nov-2009
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UNIT-2

BIPOLAR LOGIC AND INTERFACING

Q1. Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help of
function table (nov-2009)

Q2. Compare CMOS, TTL and ECL with reference to logic levels, D.C noise margin propagation
delay and fan-out. (Nov-2004)

Q3. Explain the terms with reference to TTL gate.

i) Logic levels ii) D.C.noise margin iii) Low-state unit load iv) High state fan-out raw (nov2008)

Q4. List out TTL families and compare them with reference to propagation delay, power
consumption, and speed-power produce low-level input current. (Nov-2004)

Q5. Design TTL three-state NAND gate and explain the operation with the help of function table.

Q6. What is the necessity of separate interfacing circuit connect CMOS gate to TTLgate? Draw
the interface circuit and explain the operation. (Nov-2004)

Q7. Design three input NAND gate using diode logic and transistor inverter. Analyze the circuit
with the help of transfer characteristics. (May-2005)

Q8. List different categories of characteristics in a TTL data sheet. Discuss electrical and
switching characteristics of 74LS00. (May-2005)

Q9. Mention the D.C noise margin levels of ECL 10k family. (May-2005)

Q10.Draw the transistor logic inverter circuit and analyze the circuit behavior with help of
transfer characteristics.

Q11.Draw the circuit diagram of two input 10K ECL NOR gate and explain the circuit. (Nov-
2005)

Q12. Explain sinking current and sourcing current and sourcing current of TTL output. Which of
the above parameters decide fan-out and how? (Nov-2005)

Q13. Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help
of functional operation. (Nov-2005)

Q14. Explain the behavioral difference between simple transistor logic inverter and schottkey
logic inverter. (March-2006)

Q15. What is necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw
the interface circuit and explain the operation. (Nov-2004)
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Q16. Draw the circuit for two-point LS-TTL NOR gate the explain its operation. Give the function
table, truth table and logic symbol for the same. (Nov-2009)

Q17. Expalin about the salient features of schottky TTL family. Give typical values of various
parameters. Compare this logic family with that of standard TTL family (nov-2009)

Q18. Explain how CMOS-TTL interfacing can be achieved. Give the input and output levels of
voltage and explain the same. (Nov-2009)
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UNIT-3&4

THE VHDL HARDWARE DESCRIPTION LANGUAGE

Q1. Explain data flow design elements of VHDL (nov-2004)

Q2.Explain behavioral design model of VHDL (nov-2004)

Q3. Discuss steps in VHDL design flow (nov-2004)

Q4. What is the importance of time dimension in VHDL and explain its function? (nov-2008)

Q5. Explain with example the syntax and the function of the following VHDL statements

a)Process statement b)If, else and elseif statements c)Case statement d)Loop statement

Q6. Explain the difference in program structure of VHDL and any other procedural language
give aqn example.

Q7. Write VHDL Entity and Architecture for the following function.

F(x)=a b c

Also draw the relevant logic diagram. (Feb-2008)

Q8. Explain the various data types supported by VHDL.Give the necessary examples. (Nov-
2008)

Q9.Explain implicit visibility of a library in VHDL. (May/june-2009)

Q10. Explain the use of packages. Give the syntax and structure of a package in VHDL
(may/june-2009)

Q11. Explain data-flow design elements of VHDL. (May/june 2009)

Q12. With block schematic explain the VHDL programme structure. (Nov-2009)

Q13. Explain about the elements of VHDL given below .with examples.

a) Indentifies b) comments c)compiler directives.

Q14. With examples in VHDL, explain the usage of producer in VHDL.(nov-2009)

Q15. Explain the terms entity, is, port, in, out and end pertaining to VHDL compiler. Write a
VHDL program using all the above terms and explain the same (nov-2009)
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UNIT-5

COMBINATIONAL LOGIC DESIGN

Q1.Write a data flow style VHDL programme for the following functions

F(S) =A B C

Q2. A mechanical disk rotates in different positions. Two successive positions doffer with an
angle of 15.Provide an encoding mechanism for every position of the disk. The disk in the
mechanical system outputs this encoded information to detect the exact position. Design a
decoder with an enable input to identify the position of the disk. (Nov-2004)

Q3. Write a process based VHDL program for the prime number detector of 4-bit input and
explain the flow using logic circuit (nov-2004)

Q4. Using two 74X138 decoders design a 4 to 16 decoder. (Nov-2004)

Q5. Write Data flow style VHDL program for the above design (nov-2004)

Q6. Design combinational logic circuit that counts the number of one¶s in a 24-bit register write a
VHDL program for the above implementation. (Nov-2004)

Q7. Design a logic circuit to detect prime number of a bit input. Write the structural VHDL
program for the above design (nov-2004)

Q8. Design a priority encoder for 16 inputs using two 74X148 encoders. (Nov-2004)

Q9. Write behavioral VHDL program for the above design. (nov-2004)

Q10. Design a full subtracter with logic gates and write VHDL data flow programe for the
implementation of the above subtractor. (Nov-2004)

Q11. Using the above subtracter design a 8-bit ripple subtracter and write the corresponding
VHDL program. (Nov-2004)

Q12. Design a 32 to 1 multiplexer using four 74X151 multiplexes and 74X139 decoder. (Nov-
2004)

Q13. Write a data flow VHDL program for a simple 8-bit multiplexer. (Nov-2004)

Q14. Show the logic diagram of 74X283 binary adder.Expalin the principal of generating sum
and carry at every stage using the logic diagram. (Nov-2004)

Q15. Design a 24-bit group ripple adder using 74X283 ICs. (Nov-2004)

Q16. Design the logic circuit and write data flow style VHDL program for the following function
F(X) = A,B,C,D (3,5,6,7,13)+d(1,2,4,12,15) (may-2005)
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Q17. Design the logic circuit and write a data flow style VHDL program for te following
function.F(X) = A,B,C,D(0,1,3,5,14)+d(8,15) (may-2005)

Q18. Design a 16-bit comparator using 74X85 ICs. (May-2005)

Q19. Draw the logic diagram of 74X283 IC and explain the operation. Write data flow VHDL
program for this IC. (May-2005)

Q20. Give the logic diagram of 74X139.Explain with the help of truth table. Using this device
design a 3 to 8 decoder and provide the truth table. (May-2005)

Q21. Draw the digits created by 74X49 seven-segment decoder for non decimal inputs,1010
through 1111.

Q22.Realize the following expression using 74X151 IC

F(X) =ABC+ABC+ABC (may-2005)

Q23. Realizing the following using 74X151 IC f(Y)=AB+BC+AC. (May-2005)

Q24. With the help of logic diagram explain 74X157 multiplexer. (Nov-2005)

Q25. Design a 16-bit ALU using 74X381 and 74182 ICs. (Nov-2005)

Q26. Design the logic write a data flow style VHDL program for the following functions¶(R) =X
A,B,C,D(1,4,5,7,9,13,15). (Nov-2005)

Q27. Design a logic circuit to detect prime number of a 4-bit input.write the VHDL for the above
design. (March-2006)

Q28. Design the logic circuit and write a data flow style VHDL program for the following
function¶s(P)= A,B,C,D(1,5,6,7,9,13)+d(4,15) (marc-2006)

Q29. Realize the following expression using 74X151 ICs and 74X139 IC

F(Z)-ABCD+ABCD+ABCD+ABDE+ACDE+ABCE+ABCD (march-2006)

Q30. Design a full adder using two half adders. Write VHDL data flow program for the above
implementation. (march2006)

Q31. Using full adders design an 8-bit ripple carry adder and write te corresponding VHDL
program. (March-2006)

Q32. Design a 3 input 5-bit multiplexer. Write the truth table and draw the logic diagram provide
the data flow VHDL program. (March-2006)

Q33.Desing a 4-bit Carry looks added adder using gates and write data flow VHDL program.
(March-2006)
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Q34.It is necessary to identify the position of mechanical disk rotates a step of 45°give the
necessary encoding mechanism and draw the logic circuit. (March-2006)

Q35. Design the logic circuit and write a data-flow style VHDL program for the following
function(x) = ʌA,B,C,D(1,7,9,13,15) (nov-2007)

Q36. Design the logic circuit and write a data-flow style VHDL program forn the following
functions.

F(Y)= A,B,C,D(1,4,5,7,12,14,15)+d(3,11) (nov-2006)

Q37. Design the logic circuit and write a data flow style VHDL prpgram for the following
functions.

a)F(X)= A,B,C,D (0,2,5,7,8,10,13,15)+d(1,6,11)

b)F(Y)=ʌA,B,C,D, (1,4,5,7,9,11,12,13,15). (Nov-2007)

Q38. Design the logic circuit and write data flow style VHDL program for te following function.

F(Q)= A,B,C,D(0,2,5,7,8,10,13,15)+d(11). (Nov-2006)

Q39. Design a 4*4 combinational multiplier and write the corresponding VHDL program. (Nov-
2007)

Q40.Design a 16-bit comparator using 74*85 IC.the relevant circuit diagram. (Nov-2008)

Q41. Write VHDL program for a full adder. (May-2005)

Q42. Draw the truth table implementing a 3-to-8 decoder similar to 74*138 MSI chip. Use one
active low enable input G and active high outputs, Y7 to Yo.convert the truth table into suitable
dataflow model of VHDL code. (Nov-2009)

Q43.Construct the function F(W3,W2,W1)= m(0,1,3,4,6,7)using a 3-to-8 decoder and an OR

gate. Draw the circuit diagram for the function. (Nov-2009)

Q44. Draw the truth table and circuit diagram of a 4-bit comparator using exclusive OR
/Exclusive NOR gates and only other basic gates .Output of the comparator sould be 0 if inputs
are equal and 1 otherwise. (Nov-2009)
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UNIT-6

COMBINATIONAL CIRCUITS DESIGN EXAMPLES

Q1. A 16-bit barrel sifters a combinational logic circuit with 16-data inputs,16-data outputs and
4-co0nrols inputs. The input word is rotated by a number of bit positions specified by control
bits. Write a VHDL program for the above implementation. (Nov-2004)

Q2.Design a barrel sifter for 8-bit using three control inputs. Write a VHDL program for the same
in data flow style. (Nov-2008)

Q3.Draw the diagram of a barrel shifter which can shift 0, 1, 2, and 3 bit positions area as per
the control signals.S1 and S2. (Nov-2009)

Q4. Write a VHDL code for the two basic building blocks of 4-bit barrel shifter .a2-to-4 Decoder
and a 4-to-1 multiplexer. (Nov-2009)
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UNIT-7

Q1. Distinguish between latch and flip-flop. Show the logic diagram for both. Explain the
operation with the help of function table. (Nov-2004)

Q2. Design a conversion circuit to convert a T flip-flop from J-K flip-flop. (Nov-2004)

Q3. Draw the logic diagram of 74X174 IC and explain the operation. Develop the VHDL model
for this IC.

Q4. Write VHDL program to generate a clock with OFF time and ON time equal to 10ns. (Nov-
2004)

Q5. Design a switch debouncer circuit using 74X109 IC.expalin the operation using timing
diagram.

Q6. Draw the circuit diagram, function table of a controlled D latch. (Nov-2009)

Q7.Explain the operation of a D latch through suitable timing diagrams for various possibilities of
input. (Nov-2009)

Q8.Write a VHDL code for simulating a positive edge trigged D flip-flop with µprest¶and µclear¶
input signal, similar to the flip-flop on IC 74*74 (nov-2009)

Q9. Design an excess-3 decimal counter using 74*163and explain the operation with help of
timing wave forms. (Nov-2004)

Q10. Design modulo-100 counter using two 74*163 binary counters. (Nov-2004)

Q11. What is a scan flip-flop? Draw the circuit diagram and its function table of scan flip-flop to
it¶s explaining its operation. (Nov-2009)

Q12. Design a madulo-64 counter using 74X163 ICs. (May-2005)

Q13. Design a 4-bit binary synchronous counter using 74*74.write VHDL program for this logic.
(May-2005)

Q14. Design a modulo-60 counter using 74X163 ICs. (May-2005)

Q15. Design an 8-bit synchronous binary counter with serial enable control. (March-2006)

Q16. Draw the logic diagram of 74X163 binary counters and explain its operation. (March-
2006)

Q17. Write a VHDL entity and architecture for a 3-bit synchronous counter Flip-Flops.
(May/june-2009)
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Q18. Design an 8-bit parallel-in serial-out shift register. Explain the operation of the above shift
register with the help of timing waveforms. (Nov-2004)

Q19. Draw the logic diagram of 74X194 and explain the operation. (Nov-2004)

Q20. Design 8-bit parallel-in and parallel-out shift register and explain the operation. (Nov-
2004)

Q21. What is the difference between ring counter and Johnson ring counter? Design a self-
correcting 4-bit,4-state ring counter with single circulating 0 using74X194. (nov-2004)

Q22. Explain serial data communication is possible using 74X166 as transmitter and 74X164 as
receiver. (Nov-2004)

Q23. Discuss logic circuit of 74X377 register. Write a VGDL program for the above logic. (Nov-
2004)

Q24. Design LSFR counter using 74X194.list out the se3quence assuming that the initial state
is 101. (May-2005)

Q25. . Design LSFR counter using 74X194.list out the se3quence assuming that the initial state
is 001. (Nov-2005)

Q26. . Explain LSFR. Design a 4-bit LFSR flip-flops and associated logic. List out all states with
initial state as 0101. (Nov-2005)

Q27. Design an 8-bit serial-in and parallel-out shift register write the dataflow style VHDL
program for this shift register. (Nov-2005)

Q28. Design 8-bit serial-in and parallel ±out sift register with flip-flop.expain the operation with
the help of timing waveforms. (Marc-2006)

Q29. Write VHDL data flow program for the sift-register. (March-2006)

Q30. Draw the below diagram of an 8-bit bidirectional shift register and write VHDL description
of the same, giving explanation. (Nov-2009)

Q31. Define clock skew. Explain how clock skew leads to incorrect outputs in synchronous
circuit. Design one logic circuit that minimizes clock skew. (Nov-2004)

Q32. Design a serial binary adder. Develop the VHDL program for simulating serial binary
adder. (Nov-2004)
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UNIT-8

Q1. With the help of logic diagram discuss PAL16R8. (Nov-2004)

Q2. With the help of logic diagram explain the function of PAL16R6.Expalin how an 8-bit
synchronous binary counter can be realized with this devise. (May-2005)

Q3.Expalin 4*4 binary multiplier can be designed using 256*8 ROM. (Nov-2008)

Q4. Discuss how PROM, EPROM and EEPROM technologies differ from each other. (Nov-
2004)

Q5. With the help of timing waveform, explain read and write operations of SRAM. (Nov-2004)

Q6. Explain necessity of two-dimensional decoding mechanism in memories. Draw MOS

transistor memory cell in ROM and explain the operation. (Noc-2004)

Q7. Draw the basic cell structure of Dynamic RAM. What is the necessity of refresh cycle?
Expalin the timing requirements of refresh operation. (Nov-2004)

Q8.Discuss in retail ROM access mechanism with the help of timing waveforms. (Nov-2004)

Q9. Explain the internal structure of 64K*1DRAM. With the help of timing waveforms discuss
DRAM access. (Nov-2005)

Q10. Explain the operation of synchronous SRAM with the help of its internal Architecture.
(Mqy-2005)

Q11. Determine the ROM size needed to realize the logic function performed by74X153 and
74X139. (May-2005)

Q12.How many ROM bits are required to build a 16-bit adder/subtracter with mode control,
carry input, carry output and twos complement overflow output? Show the block schematic with
all inputs and outputs. (Nov-2005)

Q22. Design an 8*4 diode ROM using 74X138 for the following data starting from the first
location.B, 2, 4, F, A, D, F, E. (Nov-2005)

Q23. Realizing the logic function performed by 74X381 with ROM. (March-2006)

Q24. Design an 8*4 diode ROM using 74X381 for the following data starting from the first
location.1,4,9,B,A,0,F,C. (March-2006)

Q25. With the help of internal structure of a small SRAM and its timing diagram, describe read
and write operations performed in the SRAM. (Nov/dec-2009)

Q26. Discuss the concept along with the merits of two-dimensional decoding for Read Only
Memory. (nov/dec-2009)
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Q27.List out the advantages and disadvantages of Read Only Memories based on
combinational circuit design. (Nov/dec-2009)
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