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  • 54124-mt - CPLD & Fpga Architecture & Applications

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    SRINIVASA RAO GANTA
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    This document contains 8 questions related to CPLD and FPGA architecture and applications for a M.Tech semester exam. The questions cover topics such as PAL assembler and schematic capture tools, designing counters and combinational logic circuits using programmable logic devices, features and applications of CPLD devices from Altera's MAX 5000 series, design flows for FPGAs including technology mapping, top-down design of state machines, microprogramming, non-registered PLD system designs, one-hot design methods, and case studies for counters and multiplexers using FPGAs. Notes are also requested on FPGA design tools, ASIC design tools, and the Cypress FLASH 370 device technology.

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    54124-mt----cpld & fpga architecture & applications

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    This document contains 8 questions related to CPLD and FPGA architecture and applications for a M.Tech semester exam. The questions cover topics such as PAL assembler and schematic capture tools, designing counters and combinational logic circuits using programmable logic devices, features and applications of CPLD devices from Altera's MAX 5000 series, design flows for FPGAs including technology mapping, top-down design of state machines, microprogramming, non-registered PLD system designs, one-hot design methods, and case studies for counters and multiplexers using FPGAs. Notes are also requested on FPGA design tools, ASIC design tools, and the Cypress FLASH 370 device technology.

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    Download as PDF, TXT or read online from Scribd
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    2K views1 page

    54124-mt - CPLD & Fpga Architecture & Applications

    Uploaded by

    SRINIVASA RAO GANTA
    This document contains 8 questions related to CPLD and FPGA architecture and applications for a M.Tech semester exam. The questions cover topics such as PAL assembler and schematic capture tools, designing counters and combinational logic circuits using programmable logic devices, features and applications of CPLD devices from Altera's MAX 5000 series, design flows for FPGAs including technology mapping, top-down design of state machines, microprogramming, non-registered PLD system designs, one-hot design methods, and case studies for counters and multiplexers using FPGAs. Notes are also requested on FPGA design tools, ASIC design tools, and the Cypress FLASH 370 device technology.

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    of 1

    Code No: 54124/MT

    NR
    M.Tech. – I Semester Supplementary Examinations,
    September, 2008

    CPLD & FPGA ARCHITECTURE & APPLICATIONS


    (VLSI System Design)
    Time: 3hours Max. Marks:60
    Answer any FIVE questions
    All questions carry equal marks
    ---
    1.a) Explain about PAL Assembler (PALASM), Schematic Captures in
    the design process.
    b) Give the block schematic of Mask programmable ROM and explain
    its features.
    2.a) Design a BCD counter using appropriate programmable logic
    elements or devices.
    b) A combinational circuit whose input is a 4-bit number and whose
    output is the 2’ s compliment of the input number is to be
    implemented using a field Programmable Array Device. Show the
    appropriately coded logic diagram of the selected device.

    3. Give the features, programming and any typical application of any


    CPLD device of Altera-Max 5000 series.

    4.a) Give the design flow and Technology mapping for any general
    FPGA.
    b) Give an example for the application of ALTERA’S FLEX 10,000
    series FPGA.

    5.a) Explain about the Top Down design approach of a state machine.
    b) Explain how realization of state machine chart suing
    microprogramming is done.

    6.a) Give an example and explain for a system design of Architectures


    Centered around non-registered PLDS.
    b) Explain about one-Hot design method.
    7. Give design flow using FPGAs, as a case study for
    a) Counters b) Multiplexers.
    8. Write notes on any TWO
    a) Mentor Graphics EDA Tool FPGA Advantage
    b) Digital Design Tools for ASICs
    c) Cypres FLASH 370 Device Technology.
    ^*^*^

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