The current conveyor: history, progress and new
A.S. Sedra
G.W. Roberts
F. Gohh
Indexing terms: History, Reviews of progress, Filters andfiltering
Abstract: With the growing interest in current-
mode analogue circuits, an historical account of
the invention of the current conveyor is given.
Some observations are made on the progress in its
realisation and application over the past two
decades. New results on the monolithic implemen-
tation of the current conveyor are presented.
1 A specific problem and its solution
In the autumn of 1966, the first author began work on a
Master's thesis project under the supervision of Prof.
K.C. Smith at the University of Toronto. The goal of the
project was the design of programmable instruments for
incorporation in a system for computer controlled experi-
ments. Within this framework, the first task was to design
a voltage controlled waveform generator, and he came up
with a circuit that was thought to be novel [l]. Unfor-
tunately (or fortunately, from the point of view of the
present context !), however, the control variable was
current and not voltage as required. To convert voltage
to current, the obvious solution (at that time) was to use
a grounded-base pnp transistor and connect its emitter
via a resistor to the positive control voltage. However,
this simple voltage-to-current convertor introduced a
number of problems, all due to the transistor VE,. Not
only did the finite V, introduce a lateral shift in the
frequency-voltage characteristic of the waveform gener-
ator, but the variation of V', with current also made the
control characteristic nonlinear. Furthermore, the depen-
dence of V,, on temperature considerably reduced the
temperature stability of the entire circuit.
To create a better voltage-to-current convertor it
seemed natural to use another junction, that of a
matched pnp transistor connected as a diode, to compen-
sate for the V, of the current-source pnp transistor.
However, for this compensation to be effective it was
necessary to arrange that the current in the additional
pnp transistor track that in the current-source transistor,
which was supposed to vary over a number of decades.
The solution to this problem was the five-transistor
circuit shown in Fig. 1.
In the circuit of Fig. 1, Q1 is the current source tran-
sistor, its emitter was connected via a resistor R to
Paper 71546 (E10, E1-5). received 30th August 1989
The paper is based in part on an invited presentation made at the 1989
IEEE International Symposium on Circuits and Systems, Portland
Oregon, May 1989
The authors are with the Department of Electrical Engineering, Uni-
versity of Toronto, Toronto, Ontario, Canada M5S 1A4
78
control voltage V , . Transistor Qz is the compensating
diode-connected transistor; its emitter was connected to
ground. Transistors Q3, Q4 and Q 5 form what is now
known as a two-output current mirror. The mirror pro-
vided a current to Q 2equal to that in Q1, thus making
their V,,s equal and making the voltage at the emitter of
Q1 equal to zero. This in turn made the current in Q1
equal to V,/R. The mirror supplied an equal current at
the collector of Q s, at a high impedance level. Since Qs,
Q4 and Q 5 were discrete devices, their matching was not
good and emitter resistors were added to improve the
mirror performance.
Y X
7 7
~
* * * -12
Q4
Q3
"55
Fig. 1 First order bipolar implementation of CCl
= Matched resistors
*, + Matched transistors
The circuit of Fig. 1 provided a nice solution to the
problem of creating a precise voltage-to-current conver-
tor and was incorporated into the circuit for the con-
trolled oscillator with good results [l].
2 Generalisingthe idea: the first current
conveyor
Rather than moving on to the design of another part of
the programmable instrumentation system, the first
author, being a graduate student at the time, had the
luxury of pausing and contemplating, together with his
advisor, the beauty of the circuit of Fig. 1. It should also
be noted that the time was ripe to think of current-mode
circuits. In February 1968 he attended the International
Solid-state Circuit Conference in Philadelphia and was
greatly inspired by two papers: Barrie Gilbert presented
a technique, which has become a classic, for wideband
amplification of current signals [2]. The other paper was
by G. Wilson [3] and contained a novel current-mirror
configuration; now known as the Wilson current mirror.
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990
The idea that much higher speeds of processing signals
are possible if the signals are in current form was gaining
in popularity.
It was observed that in the circuit of Fig. 1, Y need not
be grounded but can be connected to a voltage u y . An
equal voltage then appears at X independent of the
current supplied to X. Thus the circuit exhibits a virtual
short circuit at X. Also a current flows through Y equal
to the current supplied to X and independent of uy . Thus
the circuit exhibits a virtual open circuit at Y.Finally, the
current supplied to X is conoeyed to the output terminal
Z where the impedance level is very high. The circuit
operation is independent of the exact value of the nega-
tive supply Vss.We were thus led to think of the circuit
of Fig. 1 as an implementation of a three-port network
represented by the block diagram of Fig. 2 and described
by
[;I =[' :q[q
O l O U ,
where the variables represent total instantaneous quan-
tities. The resulting three-port network was named
current conveyor [4].
Fig. 2 Black box representation ofthe current conveyor
figure a single ellipse is used to represent the nullator
element and two intersecting ellipses to respresent the
norator element. The nullator element has constitutive
conveyor required that the measured circuit be broken to
insert terminals X and Y of the conveyor, very impressive
results were obtained. Input impedances less than one
ohm and a frequency range of operation extending from
DC to 1 0 0 MHz were measured.
Another early application of the CCI was its use as a
negative impedance converter (NIC). For this application
terminal Z is grounded and the resistor to be converted is
connected either between X and ground or between Y
and ground. If a resistor R is connected between X and
ground, then the input impedance looking into Y is a
negative resistance of R that is short circuit stable
(similar to that observed in a tunnel diode). Alternatively,
if R is connected between Y and ground then the input
resistance at X is - R and is open circuit stable (similar
to that observed in a silicon controlled switch). It is inter-
esting to note that a recently published paper [7]
describes an NIC using a CMOS current conveyor.
It should be obvious that the circuit of Fig. 1 is a first-
order implementation of the CCI. Circuit performance
can be improved through, for instance, using more elabo-
rate current mirrors. Also, the polarity of the output
current at Z can be inverted by using an additional
mirror stage. The entire circuit can of course be inverted
(pnps replaced by npns and vice versa, and the negative
supply replaced by a positive supply). Connecting two
complementary current conveyors as in Fig. 4 results in a
class AB circuit capable of bipolar operation. A number
of variations on this latter circuit have been reported (see
for example Reference 8).
M4] in this circuit can be found as part of the biasing
network of some CMOS op amps[lO]
"ss
Fig. 5 First order CMOS implementation of CCI
4 The second generation current conveyor (CCII)
To increase the versatility of the current conveyor, a
second version in which no current flows in terminal Y,
was introduced in 1968 (at the first IEEE International
Symposium on Circuit Theory, later named ISCAS). Uti-
lising the same block diagram representation of Fig. 2,
the CCII is described by
Thus, terminal Y exhibits an infinite input impedance.
The voltage at X follows that applied to Y, thus X
exhibits a zero input impedance. The current supplied to
X is conveyed to the high impedance output terminal Z
where it is supplied with either positive polarity (in
CCII+) or negative polarity (in CCII-). In terms of a
nullor, the port behavior of the second generation current
conveyor (positive or negative) can be depicted as shown
in Fig. 6a. The similarity and difference between a CCI
and CCII are clearly evident when one compares their
equivalent circuits in Figs. 3 and 6a. In the case of a
CCII -, the dependent current source is redundant;
current flowing into terminal X must flow out of terminal
2. Hence, the equivalent circuit of the CCII - can be rep-
resented with a single nullor element as shown in Fig. 6b.
This representation has important design implications
that will be discussed in the next section.
"7
nv
a bipolar or MOS. To illustrate this point, consider the
b
Fig. 6 Nullator-norator representations of CCIIs
a Positive or negative CCII
b Simplised representationof negative CCII
80
The first widely-available paper on the CCII [ll]
illustrated its application in the realisation of controlled
sources, impedance convertors, impedance inverters,
gyrators, and various analogue computation elements. A
companion paper [12] gave realisations for a number of
nonlinear building blocks that had been postulated by
Chua. Unfortunately, however, no circuit realisations for
the CCII were given at that time. One such realisation
utilising bipolar transistors was known [13], but not
widely available.
The inventors of the current conveyor knew that
although they had a powerful building block it would
have little impact unless it became available in IC form.
They attempted to interest Canada's only semiconductor
manufacturer at that time (Microsystems International
Limited) in the current conveyor with no success. As an
alternative, their attention was directed to devising CCII
realisations utilising the then emerging IC op amp. One
such realisation utilising an IC op amp and an IC tran-
sistor array was reported at that time [14]. It was their
view, however, that the op amp is not the most conve-
nient building block for realising CCII; the op amp is
fundamentally a voltage-mode device, while the current
conveyor is a current-mode device. This view proved not
entirely valid in light of the ingenious schemes suggested
a number of years later [15-171.
By about 1970, the inventors of the current conveyor
abandoned further research on it. Fortunately, however,
other workers picked up the subject, and over the
ensuing two decades over 100 papers have been
published on current conveyors. The limited space avail-
able here will not permit even a listing let alone a review,
of these articles. (A brief review of some of this work was
given in Reference 18).
The CCII has proved to be by far the more useful of
the two current conveyor types. The published literature
provides CCII realisations for almost all known active
network building blocks. A great deal of work has also
been reported on the design of active-RC filters utilising
CCIIS.
Until the past half dozen years or so, few circuit realis-
ations of the CCII have been reported. The situation has
changed dramatically with the appearance of a number
of good implementations; some of these utilise op amps
alone (for example Reference 19); others utilise IC op
amps together with BJT IC arrays [15-171 and others yet
utilise CMOS technology, resulting in fully integrated
conveyors [20, 211. It is also interesting to report that
several monolithic bipolar realisations of the CCII -
have been fabricated, although these have been labelled
as monolithic nullor elements [22, 231. Many of these
realisations can be derived using the rationale outlined in
the following section.
5 Basis for the circuit realisation of CCll
The CCII may be viewed as an ideal transistor, either
nMOS transistor shown in Fig. 7. If the transistor were
D
vq7t-
- Gd{J1n
'X
llS
5
Fig. 7 Comparison of C C I I - and nMOS transistor
IEE PROCEEDINGS, Vol. 137, Pt. G , No. 2, APRIL 1990
ideal, its V,, would approach zero. In such a case a and 4 (or 1 and 3) of the op amp creates a nullor circuit
voltage applied to the gate would result in an equal that is identical to the one used to represent the CCII -
voltage at the source. While the gate terminal would (see Fig. 66). We can therefore equate the CCII- to a
approximate an open circuit (as the conveyor terminal
Y), the source terminal would exhibit a zero input imped-
ance (just as the conveyor terminal X). A current injected
at the source would be conveyed to the drain, where the
impedance level would be infinite (just as terminal 2 in
the conveyor). It follows that an ideal transistor behaves
as a negative current conveyor (CCII-). This equiva-
lence should also be obvious from the fact that the T
nullator-norator equivalent circuit of a transistor is that
in Fig. 66.
To create a more ideal transistor, we place the nMOS
transistor in the negative feedback loop of an op amp, as
shown in Fig. 8. The result is a CCII- with reasonably

Fig. 8 Negative current conveyor using a 'supertransistor'

good performance. In this CCII - realisation, however,

current is restricted to flow out of terminal X.An alterna-
tive CCII- realisation can be obtained by placing a
PMOS transistor in the negative feedback loop of an op

Mplm
amp, in which case current will be restricted to flow into VDD
the X terminal. It follows that a CCII realisation that t
allows bidirectional current flow can be obtained by
placing a complementary pair of MOS transistors in the MPp MP)
op amp feedback path as shown in Fig. 9a. Observe,
however, that this circuit is now a CCII + realisation. To
obtain a CCII- circuit two additional mirrors are pb
required, as shown in Fig. 96.
In the circuits of Fig. 9 the M,-M2 pair of transistors V r \
may be thought of as a class B output stage for the op
amp. This circuit, therefore, is not much different to that
used by Wilson [l5] and Toumazou and Lidgey [16, 171
except that they sense the total supply current of a com-
mercially available op amp (simply because they do not
have access to the output stage of the op amp as would
be available in a fully integrated conveyor realisation).
We have recently fabricated a realisation based on the
circuits of Fig. 9 with Northern Telecom's 5 pm CMOS
process [21]. The design details and the measured per- t
formance of these monolithic current conyeyor circuits vss
will be reported in the following section. Fig. 9 Current conveyors
While current mirrors form an essential part of the a Positive
CCII realisation, the CCII may be thought of as provid- b Negative
ing a current mirror with greatly improved performance.
This ingenious point of view has enabled the application floating differential-input, differential-output op amp as
of current conveyors in the design of a high performance shown in Fig. lob. The significance of this correspon-
algorithmic A/D convertor [24]. dence is that it suggests alternative ways of realising a
Before leaving this section, it is interesting to point out negative current conveyor. For example, a CCII - can be
that, in addition to the similarity between a CCII- and approached quite closely by replacing the fully differen-
an ideal transistor, a similar correspondence can be tial op amp with a floating VCVS of large voltage gain A
drawn between a CCII - and an ideal fully differential op as depicted in Fig. lOc, or alternatively, with a floating
amp. The terminal behavior of a floating differential op VCCS of large transconductance as illustrated in Fig.
amp connected in a negative feedback arrangement can 10d. This approach was outlined by Huijsing and De
be represented by the nullor circuit shown in Fig. loa. It Korte [22] in the context of creating a fully integrated
should be obvious that a connection between terminals 2 nullor circuit (or more appropriately in the present
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990 81
context, a CCII -), however, they realised their nuilor will be avilable in the near future. In the mean time we
circuit in a manner similar to that described for the cir- shall present the experimental results pertaining to a
cuits of Fig. 9, the difference being that they used a 5 pm CMOS implementation of a positive and negative
current steering approach to accomplish the current buf- CCII based on the circuits of Fig. 9.

6 5 pm CMOS CCll implementation

The current conveyor circuit relies upon the ability of the
circuit to act as a voltage buffer between its inputs and
a upon the ability to convey current between two ports at
extremely different impedance levels. Interestingly
enough, these two attributes of a current conveyor can be
realised independent of one another and later be com-
bined to form the current conveyor. It is this approach
that we have used in the design of our monolithic current
I 6
x b
conveyor. Specifically, we have fabricated a high gain op
amp circuit with a class AB output buffer stage and
several different types of current mirrors. Separate pins
Y- provide access to the input/output points of each of these
- YZ building blocks allowing one to investigate various

3"' c
A
X
b circuit. This provides a possible means of sensing the
d
Fig. 10 Correspondence between an ideal op amp and a C U I -
a Nullor reprsssntation of an ideal op amp
b Op amp equivalent circuit of a CCII -
c VCVS representationof a CCII -, A m
d VCCS representationof a CCII - G, m - power supplies of f.5V and is biased externally through
fering between terminals X and Z, in contrast to the
above mentioned current mirroring approach. At the
present time we are investigating the feasibility of using
floating transconductance stages in a negative feedback
arrangement to realise a CCII- and hopefully results
circuit combinations. Invariably the high frequency per-
formance will suffer due to the additional stray capac-
itances at the pins, but this is an acceptable cost when
one considers the flexibility purchased.
The op amp topology is based on the popular two-
stage CMOS op amp configuration [lo] with an addi-
tional low output impedance stage. The circuit schematic
of the CMOS op amp is shown in Fig. 11. The drains of
the transistors that make up the output buffer stage (M,,
and M,,) are not connected directly to the power rails,
but rather connected to external pins of the integrated
current in the output stage, as required in the conveyor
realisations of Fig. 9. In fact, transistors M1 and M, of
the current conveyors depicted in Fig. 9 are actually tran-
sistors M,, and M,, of the CMOS op amp.
The op amp circuit shown in Fig. 11 utilises two
a resistor to obtain a bias current of 25 pA. M, and M,,
with current source M, , form the differential input stage.
M, and M, in the current mirror configuration converts
the ouput differential signal to a single-ended signal.
Transistor M, along with biasing transistor M, form the
second stage. M, and M, provide a bias voltage for the
output stage consisting of MI, and M,, . Devices M,,

VDD

t1

I MS
I 150/10

Ma

402 5/5
5 1pF

95/10
M3 M&
50/10 50/10
___
"ss
Fig. 11 Circuit schematic of the CMOS op amp

82 IEE PROCEEDINGS, Vol 137, Pi G, No. 2, APRIL I990

~~
and M,, along with compensation capacitor C, provide input bias voltage of the p-channel current mirror. Since
the internal compensation of the op amp. MI, with bias the supply lines are limited to + 5 V, the use of current
resistor R,, supply the bias voltage for current sources mirrors with large input bias voltages would severely
M, and M,. In Table 1 we list a typical set of op amp restrict the signal swing at terminal X.
The circuit implementation of the positive current con-
Table 1 : Measured CMOS OD am0 Darameters veyor is as shown in Fig. 9. The dimensions of the PMOS
Parameters Experimental results Units transistors of the current mirror, MP, and MP,, are
U . = 25 uA) 365 pm by 10 pm, while the dimensions of the nMOS
Open loop 72.7 dB transistors, MN, and MN,, are 200 pm by 10 pm. The
gain (50 Hz) larger than minimum lengths of the transistors are used
output 1051 n to provide an improved output impedance at terminal Y,
resistance while the large W / L ratio of the transistors results in
3 dB 400 Hz
smaller input bias voltage requirements.
frequency
6.2 Netagive current conveyor
Unity gain 2.2 MHz
frequency The negative current conveyor circuit can be derived
from the positive current conveyor through the addition
Slew rate (pos) +2.26 V per p e c
of two current mirrors. Unlike the current mirrors of the
Slew rate (neg) -6.87 V per w s positive current conveyor, the additional current mirrors
Power 1.21 mW are not restricted to small input voltages. As such, either
dissipation simple or stacked current mirrors can be used to achieve
Input offset 17.4 mV different current conveyor performances.
voltage A negative current conveyor using simple current
PSRR mirrors was illustrated in Fig. 9b. The dimensions of the
100 Hz 68.3 dB transistors making up the simple current mirrors are
10 KHz 47.8 dB identical to those used in the positive current conveyor.
500 KHz 13.1 dB We depict a negative current conveyor using stacked
current mirrors in Fig. 12. The only difference between
characteristics measured from a small sample set of fabri-
cated op amps.
The requirements on the current mirrors to be used "OD
within the current conveyors are: linear current gain, t
large output impedance, wide output voltage swing, small
input bias voltage and good high frequency response.
The ability to satisfy some of the above requirements
depends upon the type of current mirror chosen. There
are basically five different types of current mirrors in
CMOS technology [lo]: (i) simple current mirror, (ii)

cascode or stacked current mirror, herein referred to as
the stacked current mirror, (iii) Wilson current mirror,
(iv) improved Wilson current mirror and (v) cascode
current mirror with improved biasing, herein referred to
as a modified cascode current mirror. Prior to fabrication
a SPICE investigation was performed to compare the
various attributes of the 5 current mirrors above and
thus we came to the conclusion that one must trade off
output impedance and current conveying accuracy for
larger output voltage swing. The simple and stacked
current mirrors typify this performance tradeoff and will
be the only mirrors considered for implementation in this
work.
6.1 Positive current conveyor
The first circuit implemented is the positive current con-
veyor since the negative current conveyor can be con-
sidered an extension of the positive current conveyor. In
its implementation, simple current mirrors were used,
despite their low output impedance and poor current
gain. The reason behind this choice follows from the
allowable signal swing at the X terminal. The positive
signal swing of the X terminal (refer to Fig. 9 4 is deter-
mined by the state of transistor M, while the negative
signal swing is determined by M, . As long as both tran-
sistors remain saturated, the output stage of the op amp
will perform as expected. Thus the negative signal swing
is restricted to V's,2 above the negative input bias
voltage of the nchannel current mirror, while the positive
signal swing is restricted to Vk,l below the positive
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990
-
I II
--?----
+ "ss
Fig. 12 Negntiue current conueyor design using stacked current
mirrors
Fig. 12 and Fig. 9b is that the second pair of simple
current mirrors have been replaced by a pair of stacked
current mirrors. The stacked current mirrors are con-
structed of 342.5 pm by 5 pm PMOS transistors and
207.5 pm by 5 pm nMOS transistors. Reduction of the
channel length is possible in the stacked current mirrors
due to the high impedance nature of the circuit. The W / L
ratios of the transistors within the stacked current
mirrors were increased, to reduce the input bias voltage,
as well as providing as much output signal swing as pos-
sible.
6.3 Experimental results
The current conveyors were constructed with the appro-
priate building blocks and measurements were taken to
83
 determine the small and large signal characteristics. Due difference i, - iz is displayed as a function of i x . If one
to the building block concept, the positive and negative excludes any offset current error, one can see from these
current conveyors can physically be constructed with the results that the CCII + has the lowest current error, fol-
same op amp and first pair of current mirrors. This pro- lowed by the CCII- (stacked mirrors) and then the
vides the opportunity to compare the effects of using CCII - (simple mirrors).
different current mirrors with additional variables intro-
duced by employing different op amps and first pair of
current mirrors. As anticipated, the voltage transfer char-
acteristics between terminal Y and X are identical for all
current conveyors since they utilise the same op amp.
The large signal voltage transfer characteristic between
terminals Y and X is shown in Fig. 13.
The test points of Fig. 13 were taken with terminal X 5ol -2-
loaded with a 10 MR probe and terminal Z grounded. U

- -4-
0
r
-6-
L-
-8 -
3-
2-
1hO lobo 10600 100000 106 10;
1- frequency, Hz
.' Fig. 14 Measured small-signal magnitude response of the voltage gain
>x 0-
- between terminals X and Y
-1
0 = CCII+
-2- A = CCII - (simplemirrors)
0 = CCII - (stocked mirrors)
-3-

40
- L - 4 - 3 - 2 - 1 o 1 2 3 4

"V." 301
Fig. 13 Measured large signal voltage characteristics between termin- Q, 20-
aJs Y and X for the positive and negative current conveyors N
I

0 = CCII+
A = CCII - (simpk mirrors)
..
L
10-

0 = CCII- (stocked mirrors) gU 0-

E
L
-10-
Under this 'open circuit' test condition, the maximum 2 -20-
voltage difference between Y and X did not exceed 8 mV
over the linear range. For the situation with X loaded, -30-
the large signal voltage gain remains unchanged provided
the current supplied by terminal X does not exceed the A O L '
-300
a
-200
3
-100
a
0
' "
100 200
"
300
I

current supplying capability of the op amp output stage.
Thus, for linear circuit operation, the large-signal voltage
gain between terminals Y and X is 1.0 V/V.
The small-signal magnitude response of the voltage
gain from terminal Y to X as a function of frequency is
shown in Fig. 14. The same open circuit test conditions
were used for this measurement as for the above large-
signal voltage transfer characteristics. As expected, the
bandwidth of this voltage gain response corresponds with
the unity-gain bandwidth of the op amp (see Table 1) and
is the same for all three current conveyors investigated.
Other large-signal parameters related to the input ter-
minals include the input resistance at terminal Y, which
was measured to be greater than 10 MR (the input resist-
ance of the multimeter), while the large-signal input
resistance at terminal X was found to be approximately
0.5 R.
The large-signal current gain between terminal X and
Z (iJi,) was measured by loading X and 2 with 10 kR
resistances while applying a voltage source at terminal Y
(i.e. inverting amplifier configuration). In this manner, i ,
and iz can be controlled and measured with voltage
levels, although these measurements will be affected by
the output resistance at terminal Z. The results of the
measurements are plotted in Fig. 15 where the current
84
.
source current Ix .PA
Fig. 15 Measured large signal current error
= CCII+
A = CCII- (simplemirrors)
0 = CCII - (stocked mirrors)
The small-signal magnitude response of the current
gain from terminal X to Z as a function of frequency can
be estimated from the voltage-gains displayed in Fig. 16
for the above mentioned inverting amplifier test setup.
Here we include only those measured results applicable
to the positive current conveyor and the negative current
conveyor with stacked mirrors. (The frequency response
of the negative current conveyor with simple mirrors was
not measured). It is evident from the various voltage-gain
measurements that the current-gain bandwidth is not as
large as should be expected, in fact it is somewhat less
than the bandwidth of the voltage gain uu/ux as illus-
trated in Fig. 14. We attribute this loss of current-gain
bandwidth to the parasitic poles created by the stray
capacitance at the pins interconnecting the amplifier and
the various current mirrors, and the poles created by the
capacitance shunting the output resistance of the inver-
ting amplifier. This was the price we paid for fabricating
IEE PROCEEDINGS, Vol. 137, Pt. G, N o . 2, APRIL I990
our conveyor circuits in building block form and for
using a voltage gain to estimate a current gain. It is inter-
esting to note that the effective unity-gain-bandwidth
product exhibited by these current conveyors circuits is
larger than the gain-bandwidth product of the op amp.
50-
RX:lOOkQRZ:lOkfl
LO - and a single capacitor. A gyrator can be realised by con-
:- 30-
R X :lkn.RZ ;lOkA
;
0
:7
20
9 10
RX:lOknbRZ=lOkn I -~
o-
-10 '
For example, the effective 3 dB bandwidth of the inver-
ting amplifier with a voltage gain of 100 is 100 kHz,
hence the gain-bandwidth product is 10 MHz. This is 4.5
times greater than the unity-gain-bandwidth of the op
amp. These results corroborate recent results reported by
other researchers [23,25].
The output impedance seen at the Z output of each
current conveyor varies depending upon whether the
current conveyor is sourcing or sinking current. Specifi-
cally, when the current conveyor is sourcing c'urrent, the
output impedance is less than when it is sinking current.
This is attributed to the lower output resistance of p-
channel devices as compared to their n-channel counter-
parts. When sourcing currents of approximately 100 PA,
the output impedance of the positive current conveyor is
approximately 280 kR, the output impedance of the
negative current conveyor with simple current mirrors is
approximately 270 kR and the output impedance of the
negative current conveyor with stacked current mirrors is
approximately 1.0 MR.
6.4 Remark
For the fabricated current conveyors, the voltage buffer-
ing between terminals Y and X was shown to approach
the ideal situation much more closely than the current
transfer ratio from terminal X to terminal Z. The reason
for this lies in the fact that the voltage buffering is accom-
plished via a high gain op amp circuit connected in a
negative feedback loop, whereas the current buffering
relies solely upon the matching properties of several tran-
sistors. Simulations and experiments have shown that
better current buffering and higher output impedance is
possible with stacked current mirrors as opposed to
simple mirrors. But this is obtained at the expense of
reduced signal swing. Even with these circuit non-
idealities. we shall demonstrate in the next Section that
current conveyors can be successfully utilised in the con-
struction of reasonable-precision filter circuits.
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990
7 Filter circuits using current conveyors
7.1 Inductance Simulation
In the area of active filter design, inductor simulation has
attracted considerable interest. The advantage of design-
ing active filters by simulating the inductors of a passive
LCR realisation of the filter include low component sen-
sitivities and the ability to utilise the extensive knowledge
of LCR filter design. One of the methods in which an
inductor can be simulated is through the use of a gyrator
necting together two current conveyors of opposite
polarity [ll] as shown in Fig. 17. By terminating one of
Fig. 17 Grounded gyrator realisation using current conueyors
the ports with a grounded capacitor the impedance seen
looking into the opposite port is made the same as that
of a grounded inductor. Measurements have determined
that the effective inductance seen looking into port 1 is
L,, U 0.85C, R l z RZ1when constructed with our mono-
lithic current conveyor. The deviation from the theoreti-
cal inductance value of c, R,, R,, is due to the nonunity
current gain of each current conveyor.
As an application of this simulated inductance, we
have replaced the grounded inductors in the fifth-order
highpass elliptic LC ladder prototype network displayed
in Fig. 18a with the active circuit shown in Fig. 17. Fre-
quency and impedance scaling were used to give the
highpass filter a passband edge of 10 kHz and a load
impedance of 10 kR. The circuit was designed to have a
passband ripple of 1 dB and a minimum stopband
attenuation of 54 dB. In Fig. 18b the measured and theo-
retical passband response are plotted. It can be seen that
near the passband edge the circuit response closely
matches the ideal response. Also observable is the effect
of the limited frequency response of the gyrator on the
filter. Specifically, for frequencies greater than 100 kHz,
the filter passband response exceeds the 1 dB attenuation
margin indicated with the dotted lines. Fig. 18c shows a
photograph of the frequency response of the filter as dis-
played on an HP3580A Spectrum Analyser. Observable
are the two zeros in the filter stopband located at 4.8 kHz
and 6.8 kHz. These values match reasonably closely to
the locations of the ladder transmission zeros of 4.66 kHz
and 6.85 kHz; however, the difference is enough to
decrease the minimum stop band loss from 54dB to
50 dB.
7.2 Current amplifier-based filter circuits
Recently we have introduced a general method for syn-
thesising active filter circuits that perform signal filtering
exclusively in the current domain with voltage amplifiers
replaced by current amplifiers and all signal variables
represented by currents [26]. We believe that one can
achieve higher signal bandwidths, greater linearity and
larger dynamic range with these current-mode circuits
than with the corresponding voltage amplifier based filter
85
-
circuits. Specific details of how this synthesis is performed nected to the output port. Except for a possible scale
are provided in Reference 26. Here we shall present our factor correction, the voltage transfer function of this
first experimental results pertaining to these current- voltage driven circuit should be equivalent to the current
transfer function lout/linfor the circuit displayed in Fig.
lOkn 092nF 064nF 080nF
19b. To demonstrate the feasiblity of this approach we
constructed this current amplifier based filter circuit to
T 4 T t d 1 *
306nFT

-h-
a

I XI .

Fig. 19 Current-mode implementation of SABfilter

a Voltage amplifierb a d SAB
b Current amplifierbased SAB
5 10 20 50 100 400
frequency, kHz
realise a second order lowpass Butterworth function
b
having a 3 dB passband edge at 1 kHz. The measured
results are displayed in Fig. 20 and are compared to the

6 5
1
10
1
15
1 1
20
frequency, kHz
C

Fig. 18 Applicationfor CCII inductor simulations

(1 Fifth-order high-pass Hter

b Passband frequencyresponse
e Photograph of the measured frequency response illustrating both passband and
stopbaod operation
10 100 1000 10000
frequency.Hz
mode filter circuits. We will realise the current amplifiers
with the monolithic current conveyors described in the Fig. 20 Ideal and measured frequency response of current amplifer
last Section. By simply grounding the Y terminal of the based SAB circuit
current conveyor, a virtual ground is created at terminal 0 = Measured
- = Ideal
X from which current entering terminal X will be con-
veyed to terminal Z, thus realising a current amplifier.
Fig. 19a shows the well known Sallen and Key SAB ideal transfer function. As is evident, the measured results
filter circuit, and Fig. 19b shows the corresponding agree quite closely with the expected results.
current amplifier based filter circuit; see Reference 26. At
the present time, our lab is not equipped with a current 8 Conclusions
source generator or an oscilloscope with an accurate
current probe, so we had to improvise to measure the Although more than twenty years old, the current con-
transfer function of the circuit of Fig. 19b. By exploiting veyor appears to be an 'idea whose time has come'. This
the fact that a virtual ground exists at terminal X, one optimistic view is based on the growing interest in ana-
can inject current into this circuit by simply using a logue current-mode signal processing, the improved fully
voltage source and a series resistance. The output current integrated conveyor realisations and the vast literature
can be derived from the voltage across the resistor con- on the application of current conveyors.
86 IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL I990
9 Acknowledgments
Thanks are due to Kin Chan who has conducted a liter-
ature search that has uncovered over 100 papers on
current conveyors. This work was supported by NSERC
and by the Information Technology Research Centre.
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87