774 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO.

6, DECEMBER 1978

Robert A. Blauschild (S’70-M’74), for a photograph and biography, Richard S. Muller (S’57-M’62-SM’70) received
see this issue, p. 759. the degree of Mechanical Engineer (with high
honor) from Stevens Institute of Technology,
Hoboken, NJ, and the M.S./E.E. and Ph.D.
degrees in electrical engineering and physics
from the California Institute of Technology,
Pasadena.
He is a Professor of Electrical Engineering at
Patrick A. Tucci (M’75) was born in Port
the University of California, Berkeley. He was
Chester, NY, on August 16, 1950. He received
a NATO Fellow in 1968-1969 at the Technical
the B.S. degree in electrical engineering from
University, Munich, Germany. Hk most recent
Syracuse University, Syracuse, NY, in June
1972, and the M.S.E.E. degree from the Uni- area of research concentration has been in” MOS electronics and trans-
versity of California at Berkeley, in December ducer devices. He is the author (with T. I. Kamins) of Device Electron-
ics for Integrated Circuits (Wiley, 197 7).
1973.
He joined Signetics Corporation, Sunnyvale,
CA, in September 1973 as a Circuit Designer
in the Research Department. Since April 1978
he has been a member of the Telecommunica- Robert G. Meyer (S’64 -M’68-SM’74), for a photograph and biography,
tions Group in the Consumer Analog Department at Signetics. seep. 482 of the August 1978 issueof this JOURNAL.

A CMOS Voltage Reference

YANNIS P. TSIVIDIS, MEMBER, IEEE, AND RICHARD W. ULMER

Abstract–A method for developing a referencevoltage in CMOSinte- sented [2] -[1 O] . In most of these systems, a voltage refer-
grated circuits is described. The circuit uses MOS devices operating in ence is required and is implemented off chip. This paper will
the weak inversion region, as well as a bipolar device formed without
describe an on-chip voltage reference which is implemented
process modifications. Results from an integrated prototype are
presented.
with standard metal gate CMOS technology and which can
make possible completely self-sufficient single-chip analog-
digital LSI CMOS systems. Part of the circuit operates in the
I. INTRODUCTION weak inversion region, thus making possible a low power con-

c COMPLETELY
l~d digital
integrated
functions
coming increasingly attractive.
systems which combine analog
on the same chip are recently
Although bipolar technology
be-
sumption.
first
A brief description
be given. Then, the principle
of this region of operation will
of the suggested voltage
reference will be explained and the final implementation will
offers several advantages for analog IC’S, the requirements on be presented. Higher order effects will be discussed, and re-
the analog part of many analog-digital LSI systems are such sults from an integrated prototype will be given.
that implementation using an MOS technology is both possible
and desirable [1] . Of these, CMOS technology, in addition to II. THE WEAK INVERSION REGION OF OPERATION
its well-known advantages for the implementation of logic, The weak inversion region (also called the “subthreshold re-
places complementary devices at the disposal of the analog gion”) of operation for MOS devices has been the subject of
subcircuit designer, and thus makes possible the extension of several papers. In this discussion, we will follow the formula-
several well-established bipolar analog circuit techniques to tion given by Swanson and Meindl [11] . According to this,
CMOS technology. Several analog-digital CMOS LSI systems, the operation of an n-channel MOS transistor in weak inver-
as well as low-power CMOS analog techniques have been pre - sion, with source connected to substrate, is described by the
following equation:

Manuscript received May 1, 1978; revised August 2, 1978. Part of the

material in this paper was presented at the International Solid-State Cir-
cuits Conference, San Francisco, CA, February 1978.
‘=(:)’co(i)(?)’e’p[%
(v..-v.
Y. P. Tsividis is with the Department of Electrical Engineering and (1)
Computer Science, Columbia University, New York, NY 10027. -%71 [’-exn%)l
R. W. Ulrner is with the Integrated Circuit Division, Motorola Semi-
conductor Inc., Austin, TX 78721. where

0018 -9200/78 /1200 -0774$00 .75 @ 1978 IEEE

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TSIVIDIS AND ULMER: CMOS VOLTAGE REFERENCE 775

10FA 1 1 1 1

v~~>> +$-

lPA -

( n- \
100.A - 125°C
(a)
105T
IOVA -

ID
65QC
In& -

‘:Ei4_l 08 10 12 14
vG~(v)
16 18 20

Fig. 1. Current versus voltage for an n-channel transistor with gate con-
22 (b)

Fig. 2. (a) Bipolar transistor structure. (b) Circuit for developing the
nected to drain. Z = 4 roil, L = 0.4 mil (drawn dimensions). negative temperature coefficient voltage.

I is the drain current

VG~ is the gate-to-source voltage
VD~ is the drain-to-source voltage
z is the gate width
L is the gate length
co is the oxide capacitance per unit area Fig. 3. Two MOS transistors biased with constant currents in the weak
inversion region. The difference of their voltages is nearly propor-
v is the effective mobility of carriers in the channel tional to absolute temperature.
VT is the threshold voltage
k is the Boltzmann constant
4 is the electron charge
scribed below a reference voltage which is independent of these
T is the absolute temperature
parameters is obtained.
m and n are process dependent parameters.

The parameters m and n can be defined in terms of the var- III. VOLTAGE REFERENCE PRINCIPLE OF OPERATION
ious capacitances in the device [11] . In the circuits to be dis- The operation of the proposed voltage reference is based on
cussed below, only n will play an important role, and will be adding two voltages with opposite temperature coefficients,
discussed further in Section V. thus resulting in a temperature independent voltage.
If a device is operated with VDS >> kT/q, the last exponen- The circuit principle for developing the negative tempera-
tial in (1) vanishes, since m and n are usually between 1 and 3. ture coefficient voltage is shown in Fig. 2. A bipolar transis-
This condition will be satisfied for a transistor with gate con- tor is formed using the standard CMOS process, as shown in
nected to drain, as long as VGS >> kT/q. The resulting two- Fig. 2(a). The n+ diffusion, normally used for the source and
terminal device should have an ID - VGS characteristic which, drain of the n-channel MOS transistors, is used as the emitter
according to (1), should be represented by a straight line in a of the bipolar device. The p-well, normally used as the iso-
semilogarithmic set of axes. A typical set of measured char- lation region for the n-channel devices, is used as the base.
acteristics is shown in Fig. 1. The deviation from straight line Finally, the n-substrate is used as the collector. As a result,
behavior at high values of VG~ is due to the fact that at these the bipolar transistor formed must have its collector con-
values the transistor is not in weak inversion. The deviation nected to the positive power supply voltage. When the device
from straight line behavior at low values of VGS is due to the is biased by a constant current source, as shown in Fig. 2(b),
fact that the corresponding subthreshold currents are so low, the base-emitter voltage exhibits a nearly constant negative
that they are masked by junction reverse bias currents. The temperature coefficient [13] , and will be represented by the
increase in lD with temperature for constant VGS can be ex- equation:
plained by the temperature dependence exhibited by (l), and
VBE = VK - CT (2)
the fact that the threshold voltage VT in that equation also
decreases with temperature. Some higher order effects will be where VK and C are appropriate constants which will be dis-
discussed in Section V. cussed further in Section V.
It has previously been suggested [12] that it might be pos- The principle for developing the positive temperature coef-
sible to take advantage of the exponential nature of (1) ficient voltage is illustrated in Fig. 3. Two n-channel MOS
in order to implement a reference voltage source. This idea transistors, lfl and J42, each having its gate connected to
was at the time abandoned because most parameters in this drain, are biased at currents II and 12, respectively. Applying
equation are unreliable, especially C’., ~, VT, and the value of (1) for each device, assuming that VG~ >> kT/q, and solving
Z/L [as opposed to ratios of (Z/L) ’s] . In the approach de- for the difference of the voltages across them gives:

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776 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO. 6, DECEMBER 1978

rJ+v’”
TF’+VDD
]M7
Fig. 4. Circuit for developing the positive temperature coefficient
- .v~~

voltage. Fig. 5. Final voltage reference circuit implementation.

VI - VZ=AT (3) shown in Fig. 5, The strings I!4U - Mm - lflc and kfU -
Mm - Mm correspond to Ml and IW2, respectively, in Fig. 4.
where
R ~ and J4s are used to develop a bias current, which is mir-
rored by lf5 in order to bias bipolar transistor Q, A fraction

‘=(%[%%1 (4) of the voltage developed across f143 is obtained

and J4q as a voltage divider. Current mirror
by using R2
MG is used to
Note that many temperature dependent terms of (1) which develop II + 12, whereas the double current mirror M, - Ms -
are difficult to predict have canceled out in (4), notably p and Mg develops 12. It is to be noted that although the currents
VT. The temperature coefficient A of ( VI - Vz) then, as given II and 12 are temperature dependent, their ratio is not.
in (4), is dependent on ratios of currents and (Z/L) ’s, which
V. HIGHER ORDER EFFECTS
can be accurately realized, physical constants k and q, and the
parameter n, which has been found to be reliable. The two A more accurate analysis will now be performed. We begin
voltages in (2) and (3) can be added using the circuit of Fig. with the temperature dependence of VBE. The current of a
4. We have: diode-connected bipolar transistor is given by [14] :

v~ = v~~+(v~ - v*) (5a)

I= BTfi exp&-(VBE - VGO) (7)
= VK + (A - C)T. (5b)
where B and /3 are suitable constants and VGO is the bandgap
The output voltage of that circuit can therefore be made
voltage of Si extrapolated to O K.
temperature independent by adjusting II /Iz or (Z/L)l /(Z/L)z
Assume first that 1 is constant. If (7) is solved for VBE and
so that A = C. It should be noted that the principle is similar
the result is expanded in a Taylor series in T around a refer-
to that of the bipolar bandgap voltage reference [14].
ence temperature T = TO, the second and higher order terms
IV. IMPLEMENTATION will be negligible compared to the effect of parameter n, as
will be seen. If only the first two terms are kept, VBE (T) will
For satisfactory cancellation of the undesired terms of (1) in
be in the form of (2). If V&O represents VBE at T = To, it
developing (3), the two transistors in Fig. 4 must be as nearly
can be shown that the constants in (2) are given by:
identical as possible, and to achieve this one must choose Z1 =
Zz and L ~ = Lz. However, the ratio 11/Iz that will then be
(8)
required in (4) for A = C will have an exceedingly high value
(several thousand). This fact renders the circuit of Fig. 4 im-
practical, since, as seen from Fig. 1, high current ratios will (9)
cause at least one of the two devices to operate outside the
straight-line part of the characteristics at high temperatures. A common mistake is to omit the term 13(lcTo/q) in (8).
The high value of II /Iz can however be avoided by replacing
In a more real situation like that in the circuit of Fig. 5,
each one of transistors Ml and lkf2 by a string of several de-
the bias current of the bipolar transistor will be temperature
vices in series. If each string contains three devices, as in our
dependent. Most of the temperature variation will be due to
final implementation, the output voltage will be given by:
R ~, which is nearly proportional to some power of T. The
Vo = v~~+3(vl - V2) (6a) bias current then can be described with sufficient accuracy for
our purposes by:
= VK “+ (3A - C)T. (6b)
I=DT-7 (lo)
Therefore, the required vahre of II /12 in order that 3A = C
will only be the cube root of the value that would be required where -I is close to 2, and the small weak inversion current of
if single devices were used, as seen from (4). Mu - Mm - Mlc is assumed negligible with respect to the cur-
This idea is used in the implementation of the reference, as rent inM5. If (1 O) is substituted in (7), the result is solved for

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TSIVIDIS AND ULMER: CMOS VOLTAGE REFERENCE 771

VBE, and a Taylor expansion is performed around T = To, it

will again be found that higher order terms can be neglected. J’
VBE will then again be in the form of (2), where now: 3.5 -

kTo
v~=v’’=vi~+(p+~)
()—
q
(11)

n
3.0 - ●
/

~_ V; - VBEO //
(12)
TO “ 2.5 -
/“
_ ..—.

Temperat&e Dependence of n
The major deviation from the first-order behavior described
2.0
t
J,
I
in the previous sections is due to the fact that n is not a con-
stant, as is often assumed, but is instead a function of tem-
perature, as shown in Fig. 6, This effect is associated with the
L >-50
I
0
1
+50
1
+100

o (“c)
variation of space-charge capacitance and the increase of the
Fig. 6. Parametern asa function of temperature.
interface state density towards the band edges [15] . The
values of n in Fig. 6 were derived from the slope of curves
like those in Fig. 1. For the circuit of Fig. 5, we have (Z/L)l =
(Z/L)2. Using (4) and (6) then, we have:

VO(T) = VK + 3Trz(T)~ln
() ~ - CT . (13)

The value of 11/Iz required for zero-temperature coefficient

at T = TO can be found by setting (d VO/dT) IT.TO = O. The
result is:

:=exp{;p(To)+:o#T=Tj}
“4)
If this value is inserted in (13), we get fo~ the output voltage Fig. 7. Chip microphoto~aph.
at the reference temperature To:

VO(TO) = VK - CTO &

where
() (15)

dn
z
~. (16)
n(T)
T T=TO

For the value of (11/12) given in (14), the output voltage as

given in (13) is a curve with a minimum at T = To given by
(15). The behavior of n versus T is sufficiently repeatable,
.9 (“c)
and by adjusting 11/12 so that VO(T) has the value required
Fig. 8. Output voltage versustemperature.
by (15) at T = To, a zero-temperature coefficient is achieved
at that temperature.

VI. EXPERIMENTAL RESULTS necessary for zero-temperature coefficient was found to be

The circuit of Fig. 5 has been implemented as an integrated 1.105 V at 25 ‘C (11/12 = 15). The deviation from this value
circuit, shown in Fig. 7. For transistors MM, Mm, MIC, Mu, at other temperatures for a typical device is plotted in Fig. 8.
M%, Mm we have used Z = 100 pm, L = 10 ~m. The regular Also shown there is the corresponding calculated curve, as well
structure seen on the left is a binary-weighted trarisistor array as a curve for a device made by a special low-threshold process
which has been used to implement various values of II /12 by (1, /12 = 32). The upward trend of the curves on both sides of
adjusting (Z/L) for the current sources. The total current the reference temperature of 25 ‘C is predicted by (13). The
drain is 16 vA, with a total power supply voltage of 10 V. second zero-temperature coefficient point at higher tempera-
For a standard process, the value of the output voltage tures, and the subsequent downward trend are due to the fact

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778 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO. 6, DECEMBER 1978

that at these temperatures the reverse junction currents in- verter,” in Dig. Tech. Papers, Int. Solid-State Circuits Conf.,
Philadelphia, Feb. 1977.
crease and make the equivalent value of 11/12 smaller. If the [6] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based
output voltage is too small for a given application, it can be on weak inversion operation;’ IEEE J. Solid-State Circuits, vol.
converted to a higher voltage by using standard op amp tech- SC-12, pp. 224-231, June, 1977.
[7] G. F. Landsburg, “A charge-balancing monolithic A/D con-
niques, with or without offset cancellation, depending on the verter,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 662-673,
precision required, Dec. 1977.
For a temperature range bounded by Tmin and Tma,, the [8] M. J. Callahan, Jr., and H. L. Davis, “An integrated dual-tone
multi-frequency decoder,” m“ Dig. Tech. Papers, Int. Solid-State
temperature coefficient A is defined by [14]: Circuits Conf., San Francisco, Feb. 1978.
[9] E. Masuda, C. Sate, T. Iida, Y. Suzuki, Y. Agawa, and T. Shims,

1
~= ‘o, max “ ‘O, min 1 “A siugle-chip Cz MOS A/D converter for microprocessor sys-
(17)
Tm ax - Tmin VO(TO) “ tems,” in Dig. Tech. Papers, Int. Solid-State Circuits Conf., San
[ Francisco, Feb. 1978.
Measurements have shown that a temperature coefficient of [10] G. F. Lanctsburg and G. Smarandoiu, “A two-chip CMOS
CODEC,” in Dig. Tech. Papers, Int. Solid-State Circuits Conf.,
100 ppm/°C is achieved for a range of -55 “C to 85°C with San Francisco, Feb. 1978.
satisfactory yield. If the range is extended to 105 ‘C to include [11] R. M. Swanson and J. D. Meindl, “Ion-implanted complementary
the part of the curve due to reverse junction currents, a tem- MOS transistor in low-voltage circuits,” ZEEE J. Solid-State Cir-
cuits, vol. SC-7, pp. 146-153, Apr. 1972.
perature coefficient of 85 ppm/ ‘C is achieved. [12] P. R. Gray, private communication.
[13] E. S. Yang, Fundamentals of Semiconductor Devices. New
VII. CONCLUSIONS York: McGraw-HilJ, 1978.
[14] P. R. Gray and R. G. Meyer, Analysis and Design of Analog
We have presented a principle for developing a reference Integrated Ci~cuits. New York: Wiley, 1977.
voltage on a CMOS chip, using MOS transistors operating in [15] H. C. Card and R. W. Ulmer, “On the temperature dependence
weak inversion as well as a process-compatible bipolar transis- of subthreshold currents in MOS electron inversion layers,” to be
published.
tor. Expressions for the output voltage and for the required
current ratio to achieve zero-temperature coefficient at a
reference temperature have been derived. Experimental re-
sults from an integrated prototype have shown that tempera-
ture coefficients of 85 ppm/°C are achieved in a range from
- 55°C to + I05”C, using one trimming operation.

ACKNOWLEDGMENT
Yannis P. Tsividis (S’71-M’74), for a photograph and biography, see p.
The authors are grateful to Dr. 1, Young for his help. 391 of the June 1978 issue of this JOURNAL.

REFERENCES

[1] D. A, Hodges, P. R. Gray, and R. W. Brodersen, “Potential of

MOS technologies for analog integrated circuits:’ IEEE J Solid-
State Circuits, vol. SC-13, pp. 285-294, June 1978.
[2] F. H. Muss and R. C. Huntiwzton. “A CMOS monolithic 34-
digit A/D converter;’ in Dig.- Tech. Papers, In t. Solid-Stafe Richard W. Ulmer was born in Mishawaka, IN, in 1946. He received the
Circuits Conf., Philadelphia, Feb. 1976. B.S. degree in electrical engineering from John Brown University,
[3] A. G. F. Dingwall and B. D. Rosenthal, “Low-power monolithic Siloam Springs, AR, in 1968.
COS/MOS dual-slope 1l-bit A/D converter~’ in Dig. Tech. Papers, Upon graduation he joined the Texas Instruments Services Group,
Int. Solid-State Circuits Conf,, Philadelphia, Feb. 1976. Dallas, TX. In 1973 he joined Motorola Semiconductor, Inc., Phoenix,
[4] R. H. McCharles, V. A. Saletore, W. C. Black, and D. A. Hodges, AZ, as a CMOS Design Engineer, specializing in A/D converters and the
“An algorithmic analog-todigital converter;’ in Dig. Tech. development of state-of-the-art analog CMOS circuits. In 1976 he
Papers, Int, Solid-State Circuits Conf., Philadelphia, Feb. 1977. relocated with the same group to Austin, TX, where he is presently
[5] G. F. Landsburg, “A charge-balancing monolithic A/D con- working on telecommunications products.

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