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EEN4186_Labsheet_2009_2010

EEN4186_Labsheet_2009_2010

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Published by: Thamilarasan Ramalingam on Jun 28, 2012
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FACULTY OF ENGINEERING
LAB SHEET
EEN4186VLSI SYSTEM DESIGN & MODELING TECHNIQUE
TRIMESTER 1 (2009/2010)VH1 – VHDL Simulation & VerificationVH2 – VHDL Synthesis
*Note: Students are advised to read through this lab sheet and prepare your VHDL codes before doing experiment. Your performance, teamwork effort, and learning attitude will counttowards the marks.
 
EEN4186: VLSI System Design & Modeling TechniqueDesign Laboratory
1.Introduction
In this lab, there are two sections; lab assignments and project. Students are asked to write theVHDL codes for a few circuits for the lab assignments. Students are then required to do theassigned tasks for their project.Basic procedures on how to design a circuit are given at the end of the lab sheet. However,students are encouraged to use their own creativity in exploring the CAD tools to complete thetask(s). This will also sharpen students’ skills, as engineers are not procedure-followers.An introduction session will be held to get students acquaintance to the Quartus II software.
2.List of Equipments
Software:Altera Quartus IIHardware:Altera APEX20K200 FPGA development boards
3.
 Lab Assignments
The students are advised to come to the lab sessions well prepared with the VHDL sourcecodes of the designs. The lab assignments must be done by individuals (no groups). Theassignment titles will be released gradually during the trimester. Some examples of theassignments are as follows:(a)Combinatorial circuits- 2-bit full adder - 4-to-1 multiplexer - 7-segment decoder (b) Sequential circuits- Synchronous decade counter - Asynchronous decade counter - Ascending and descending sorter After mastering the software with the above assignments, the students will be required todesign, simulate and verify the functionalities of a relatively complex digital system usingQuartus II. After that they will synthesize the codes and download it on the Altera Apexdevelopment board provided.
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