Verilog HDL

Compiled from the Web Bil 361 Computer Architecture and Organization

Introduction
Hardware Description Language (HDL) Verilog is a useful and popular language Parallel not serial (Not like C language) Meaningful declaration
parameter, port name, module name,

Case-sensitive Identifies
Even and even are different

 Top-Down Bottom-up

Methodology
Target

Module 1

Module 2

Module 3

Basic Comp.

Basic Comp.

Basic Comp.

Basic Comp.

Basic Comp.

Basic Comp.

Design Flow
What functions are you want to program ? Input and output Specify the Input/Output signals Separate the whole circuit into smaller ones Each block has its own function / purpose Connect all blocks/modules

B1

B2

B3

Verification Scenario
Use test bench file to verify your design
Stimulus & Control Signal Response & Verification

Test-Bench

Module

Monitor Signals

What is a Module
Module is a block of circuit Special function and, or, mux, adder, shifter Most important Input and Output

Module

Verilog - Module

Module Declaration
module module_name (input1, input2, , output1, output2, ); endmodule Example module mux2(a, b, c);
endmodule module adder(x, y, z); endmodule

 Nests
wire [k-1:0] B;

Data types [0:k-1]B

C[1:0] = {a,b}

Registers
reg [n-1:0] A;

Integers
4d3, 4b0100, 6h20

Array
reg [8:0] ram [0:9];

Parameter
parameter size = 16; wire [size-1:0] bus;

Preprocessor Directive
`define BEQ 4b0100

No =

Synthesizable Description
Can be used in your RTL codes
`define parameter wire always if/else `include input reg assign case/casex module/endmodule output begin/end posedge/negedge

Un-synthesizable Description
Can not be used in your RTL codes! Can be used in test bench
Delay forever join deassign primitive initial wait event force Repeat Foke Time Relace

Synthesizable Operator
Binary (2 operands)
& ~& | ~| ^ ~^ AND NAND OR NOR XOR XNOR

Logic (1 or 2 op.)
!A

not A A&&B A and B A || B A or B

Example
assign a= 1; assign b= 0;

Example
a = 4b0010; then &a = 1b0; ^a = 1b1;

then a && b = 0 a || b = 1

Examples
reg [3:0] a; always @() begin a=b & c; end
wire [3:0] a = b | c;

wire [3:0] a; assign a=b & c

b = 4b0011 c = 4b0101 a = 4b0001

wire [3:0] a; assign a=b | c

b = 4b0011 c = 4b0101 a = 4b0111

 Binary Bitwise

Synthesizable Operator (cont.)

Shift
~inverse & and | or ^ XOR ~^ XNOR
<< >>

shift left shift right

Example
a= 4b0010;

Example
assign a= ~b; if b = 4b0010; then a = 4b1101;

a >>1 = 4b0001; a <<2 = 4b1000;

Conditional
A = (condition) ? B : C;

Concatenate
A=2b10; B=3b110;

then {A, B} = 5b10110

Numbers
(size) (base)(number) a = 1b0, 4b0001, 8hFF, 10d700 Negative number -8d34 = (-34)10, 5d-4 (error) Underscore (_) a = 20b00001110110101101010; a = 20b00001_11011_01011_01010;

Logic Gates Level

AND, Inverter, and OR gates
and g(z, x, y);
x y x 0 0 1 1 y 0 1 0 1 z 0 0 0 1 z

not g(y, x);

x y 0 1 z 1 0 y

or g(z, x, y);
x y x 0 0 1 1 y 0 1 0 1 z 0 1 1 1 z

 Purpose

Program 1

A circuit can calculate the addition and subtraction of two 8 bits numbers Three inputs and one output
8

+ Mux
8

If op = 1 then s=a+b s If op = 0 then s=a-b

op

Program 1 (cont.)
comment /* A first program in Verilog */ module adder_or_subtract( a, b, op, s); parameter SIZE = 8; Model declaration parameter ADD = 1b1; input op; input [SIZE-1:0] a,b; add output [SIZE-1:0] s; a + wire add, sub; assign add = a+b; Mux s assign sub = a-b; sub b assign s = (op==ADD)? add : sub; endmodule
op

Program 1 (cont.)
module adder_or_subtract( a, b, op, s); parameter SIZE = 8; parameter ADD = 1b1; add sub input op; input [SIZE-1:0] a,b; output [SIZE-1:0] s; assign s = (op==ADD)? a+b : a-b; aendmodule

Program 2
1-to-2 De-multiplexer
Select y0

D
DMUX 1

y0

y1 y1 Select 0 1 y0 D 0 y1 0 D Select

Program 2 (cont.)
// A deMux program in Verilog Single Col. comment module demux ( D, select, y0, y1); Model declaration input D; input select; D y0 output y0,y1; wire y0,y1; assign y0 = (~select) & D; y1 assign y1 = select & D; endmodule
Select

Program 2 (cont.)
/* A deMux program in Verilog */ module demux ( D, select, y0, y1); input D; input select; D output y0,y1; wire y0,y1,N; and g1(y0, D, N); and g2(y1, D, Select); not g0(N, Select); endmodule comment Model declaration
g1 N g0 g2

y0

y1

Select

Sub Module
Complex circuit Many modules in a circuit Module, sub-module, sub-sub-module,

B1

B2

B3

Example of Call Module

module B1(a, b, c); .. endmodule module B2(a, b, c, d); .. endmodule module B3(x, y, z); .. endmodule

B1 B3

B2

 module function(q, w, e, f); . B1 b1(q, w, a, b, c); B2 b2(a, b, d, e); B3 b3(c, d, f); endmodule

Example of Call Module (cont.)

module B1(a, b, c); .. endmodule module B2(a, b, c, d); .. endmodule module B3(x, y, z); .. endmodule

Port Mapping Between Modules

# of ports Width of each port
module function(a,b,c,d); . B1 b1(w, q, a, c); ........ endmodule
w q a q w e

module B1(q, w, e, f); input q, w; input [3:0] e; output [1:0] f; . endmodule

B1

Port Mapping Between Modules (cont.)

Port name should match the name in sub_module Prot connection
module_name( .port1_m1(w1_or_r1), .port2_m1(w2_or_r2), .port3_m1(w3_or_r3), .port4_m1(w4_or_r4), ) module_name( .port3_m1(w3_or_r3), .port2_m1(w2_or_r2), .port1_m1(w1_or_r1), .port4_m1(w4_or_r4), )

Connection Between Modules (cont.)

Port connection
module function(a,b,c,d); ............................ B1 b1(q, w, a, c); B1 b1(.q(q), .w(w), .e(a), .f(c)); B1 b1(.w(w), .q(q), .e(a), .f(c)); ............................ endmodule module B1(q, w, e, f); input q, w; input [3:0] e; output [1:0] f; . endmodule
q w a q w e

B1

Reuse Module
Using the same module many times Example
Constructing 4-bits adder with four 1-bit adder
b3 a3 b2 a2 b1 a1 b0 a0
a [3:0] b [3:0]

c3

c2

c1

0
Adder

s4

s3

s2

s1

s0

S [4:0]

4-bits Adder
module Adder(x, y, cin, sum, cout); input x, y, c; cout cin A output sum, cout; wire x, y, c, sum, cout; sum assign sum = x ^ y ^ cin; assign cout = (x & y) | (x & cin) | (y & cin); assign {cout, sum} = x + y + cin; endmodule
y x

4-bists Adder (cont.)

module Adder4(x, y, cin, sum); input [3:0]x, y; input cin; output [4:0]sum; wire [3:0] x, y; wire cin; wire [4:0] sum;
b3 a3 b2 a2 b1 a1 b0 a0 A c3 A c2 A c1 cin A

s2 s4 s3 wire c1, c2, c3; Adder A1(x[0], y[0], cin, sum[0], c1); Adder A2(x[1], y[1], c1, sum[1], c2); Adder A3(x[2], y[2], c2, sum[2], c3); Adder A4(x[3], y[3], c3, sum[3], sum[4]);

s1

s0

endmodule

Mistake
module and endmodule begin and end module(); not Module(); Miss ; symbol for the end of every statement Mismatch between the number of port or the number of pins of some buses

 Syntax

always @(event-expression) assignment or block

Always Block

Level type
always @(a or b or c)

Edge type
always @(posedge clock) always @(negedge clock)

if-else and case statement are only in always block wire and reg

Example wire a; reg b; always @(x or y or z) begin a <= x & y; error b <= x | z; correct end

Program 2
Select

1-to-2 De-multiplexer
0

y0

D
DMUX 1

y0

y1 y1 Select 0 1 y0 D 0 y1 0 D Select

Program 2 (cont.)
D

Select

module demux ( D, select, y0, y1); input D, select; output y0,y1; y0 reg y0,y1; always @( D or select ) begin if( select == 1b0) begin y0 = D; y1 = 1b0; y1 end else begin y0 = 1b0; y1 = D; end end endmodule

Blocking and Non-blocking

If-else and case

If (condition 1) begin .................. end else if (condition 2) begin .................. end else begin .................. end reg [1:0] state; case (state) 2b00: ......... 2b01: ......... 2b10: ......... 2b11: ......... default: ......... endcase

if statement
Like C language Only in always block
reg out; always @(sel or a or b) begin if(sel == 1b1) out = a; else out = b; end wire out; assign out = (sel)? a : b;

Using of case and casex

Multiplexer or selection Inside always block All possible condition
a b c d Sel [1:0] out

always @(sel or a or b or c or d) begin case (sel[1:0] ) 2b00 : out <= a; 2b01 : out <= b; 2b10 : out <= c; 2b11 : out <= d; endcase end

Using of case and casex (cont.)

a b c out always @(sel or a or b or c or d) begin case (sel[1:0] ) 2b00, 2b11 : out <= a; 2b01 : out <= b; 2b10 : out <= c; endcase end always @(sel or a or b or c or d) begin casex (sel[2:0] ) 3b011 : out <= a; 3b00x : out <= b; 3b100 : out <= c; default : out <= d; endcasex end All others

Sel [1:0] a b c d Sel [2:0] out

Delay and Critical Path

Each gate and wire may cause delay of circuit Longest path of the circuit is the critical path
Speed of whole circuit

Shorten the critical path can speedup the circuit Input data rate higher than the speed of circuit may cause some problems

 5 inputs adder
a b

Critical Path Example

Z = (a + b) + (c + d) + e
a b + c + Three adders e e + + Z Z d

Z=a+b+c+d+e

c +

d +

Four adders

Test-bench
Input data of the circuit All inputs of original circuit are assigned reg
Store data

All outputs of original circuit are assigned wire Assign inputs in different time Define time scale

Test-bench Example
`timescale 1ns/10ps module Adder_testbench; reg [3:0] x,y; reg cin; wire [4:0] sum; Initialization adder4 add(.x(x), .y(y), .cin(cin), .sum(sum)); initial begin #0 x = 4d0; y = 4d0; cin=1b0; #10 x = 4d3; In 10ns x=3; #5 y = 4d10; y=0; sum=3; #10 x = 4d1; y = 4d5; end In 15ns x=3; y=10; endmodule
module Adder4(x, y, cin, sum); sum=13; In 25ns x=1; y=5; sum=6;

Structural Vs Procedural
Structural textual description of circuit order does not matter Starts with assign statements Harder to code Need to work out logic Procedural Think like C code Order of statements are important Starts with initial or always statement

Easy to code Can use case, if, for

reg c, d; always@ (a or b or c) begin assign c =a & b; assign d = c |b; end
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wire c, d; assign c =a & b; assign d = c |b;

Structural Vs Procedural
Procedural
reg [3:0] Q; wire [1:0] y; always@(y) begin Q=4b0000; case(y) begin 2b00: Q[0]=1; 2b01: Q[1]=1; 2b10: Q[2]=1; 2b11: Q[3]=1; endcase end

Structural
wire [3:0]Q; wire [1:0]y; assign Q[0]=(~y[1])&(~y[0]), Q[1]=(~y[1])&y[0], Q[2]=y[1]&(~y[0]), Q[3]=y[1]&y[0];
Q[0]

Q[1]

Q[2] y[0] y[1]

Q[3]
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Blocking Vs Non-Blocking
Blocking <variable> = <statement> Similar to C code The next assignment waits until the present one is finished Used for combinational logic Non-blocking <variable> <= <statement> The inputs are stored once the procedure is triggered Statements are executed in parallel Used for flip-flops, latches and registers

Do not mix both assignments in one procedure

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Blocking Vs Non-Blocking
Initial begin #1 e=2; #1 b=1; #1 b<=0; e<=b; // grabbed the old b f=e; // used old e=2, did not wait e<=b

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Component Inference

Flip-Flops
always@(posedge clk) begin a<=b; a<=b&c; end
B D Q clk CLK A

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D Flip-Flop with Asynchronous Reset

always@(posedge clk or negedge rst) begin if (!rst) a<=0; else a<=b; end

rst B D clr Q clk CLK A

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D Flip-flop with Synchronous reset and Enable

always@(posedge clk) begin if (rst) a<=0; else if (enable) a<=b; end

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Shift Registers
reg[3:0] Q; always@(posedge clk or posedge rset ) begin if (rset) Q<=0; else begin Q <=Q << 1; Q[0]<=Q[3]; end

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Multiplexers
Method 1 assign a = (select ? b : c); Method 2 always@(select or b or c) begin if(select) a=b; else a=c; end Method 2b case(select) 1b1: a=b; 1b0: a=c; endcase
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0 1
SL

select

Counters
reg [7:0] count; wire enable; always@(posedge clk or negedge rst) begin if (rst) count<=0; else if (enable) count<=count+1; end

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Avoiding Unwanted Latches

Latches are BAD

Rule #1
If the procedure has several paths, every path must evaluate all outputs
Method1: Set all outputs to some value at the start of the procedure. Later on different values can overwrite those values. always @(... begin x=0;y=0;z=0; if (a) x=2; elseif (b) y=3; else z=4; End Method2: Be sure every branch of every if and case generate every output always @(... begin if (a) begin x=2; y=0; z=0; end elseif (b) begin x=0; y=3; z=0; end else begin x=0; y=0; z=4; end end
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Rule #2
All inputs used in the procedure must appear in the trigger list
Right-hand side variables: Except variables both calculated and used in the procedure. always @(a or b or c or x or y) begin x=a; y=b; z=c; w=x+y; end Branch controlling variables: Be sure every branch of every if and case generate every output always @(a or b) begin if (a) begin x=2; y=0; z=0; end elseif (b) begin x=0; y=3; z=0; end else begin x=0; y=0; z=4; end end
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Rule #3
All possible inputs used control statements must be covered End all case statements with the default case whether you need it or not. case(state) ... default: next_state = reset; endcase Do not forget the self loops in your state graph if(a|b&c) next_state=S1; elseif(c&d) next_state=S2; else next_state=reset;
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Finite State Machines

Standard Form for a Verilog FSM

// state flip-flops reg [2:0] state, nxt_st; // state definitions parameter reset=0,S1=1,S2=2,S3=3,..

// NEXT STATE CALCULATIONS always@(state or inputs or ...) begin next_state= ... end

// REGISTER DEFINITION always@(posedge clk) begin state<=next_state; end // OUTPUT CALCULATIONS output= f(state, inputs)

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Example
module myFSM (clk, x, z) input clk, x; output z; // state flip-flops reg [2:0] state, nxt_st; // state definition parameter S0=0,S1=1,S2=2,S3=3,S7=7 // REGISTER DEFINITION always @(posedge clk) begin state<=nxt_st; end // OUTPUTCALCULATIONS assign z = (state==S7); // NEXT STATE CALCULATIONS always @(state or x) begin case (state) S0: if(x) nxt_st=S1; else nxt_st=S0; S1: if(x) nxt_st=S3; else nxt_st=S2; S2: if(x) nxt_st=S0; else nxt_st=S7; S3: if(x) nxt_st=S2; else nxt_st=S7; S7: nxt_st=S0; default: nxt_st = S0; endcase end endmodule
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Test Benches

System tasks
Used to generate input and output during simulation. Start with $ sign. Display Selected Variables:
$display (format_string,par_1,par_2,...); $monitor(format_string,par_1,par_2,...); Example: $display(Output z: %b, z);

Writing to a File:
$fopen, $fdisplay, $fmonitor and $fwrite

Random number generator: $random (seed) Query current simulation time: $time

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Test Benches
Overview 1. Invoke the verilog under design 2. Simulate input vectors 3. Send test vectors 3. Implement the system tasks to view the results 4. Specify when to end the simulation. Approach 1. Initialize all inputs 2. Set the clk signal

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Example
timescale1 ns /100 ps // timeunit =1ns; precision=1/10ns; module my_fsm_tb; reg clk, rst, x; wire z; /**** DESIGN TO SIMULATE (my_fsm) INSTANTIATION ****/ myfsm dut1(clk, rst, x, z); /****RESET AND CLOCK SECTION****/ Initial begin clk=0; rst=0; #1rst=1; /*The delay gives rst a posedge for sure.*/ #200 rst=0; //Deactivate reset after two clock cycles +1ns*/ end always #50clk=~clk; /* 10MHz clock (50*1ns*2) with 50% duty-cycle */ /****SPECIFY THE INPUT WAVEFORM x ****/ Initial begin #1 x=0; #400 x=1;
$display(Output z: %b, z);

#100 x=0; @(posedge clk) x=1; #1000 $finish; //stop simulation //without this, it will not stop end endmodule

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Synthesizable Description
Can be used in your RTL codes
`define parameter wire always if/else `include input reg assign case/casex module/endmodule output begin/end posedge/negedge

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Un-synthesizable Description
Can not be used in your RTL codes! Can be used in test bench
Delay (#) forever join deassign primitive initial wait event force Repeat Foke Time Relace

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Register
Registers represent abstract storage elements. A register holds its value until a new value is assigned to it. Registers are used extensively in behavior modeling and in applying test patterns. Default value is X (unknown)

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Blocking and Non-blocking

Blocking assignments are executed sequentially, much like a program in C language Non-blocking assignments evaluate the right-hand side, and make the assignments when all righthand have been evaluated
Initial values: begin B = A; C = B; end

A = 3, B = 4, C = 5;
begin B <= A; C <= B; end

A = 3; B = 3; C = 3;

A = 3; B = 3; C = 4;

Blocking assignments =

Non-Blocking assignments <=

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4-bits Shift Register Codes

module shifter (in, clock, reset, out); input in, clock, reset; in R[0] output out; reg [3:0] R; assign out = R[3];

R[1]

R[2]

R[3]

out

always @(posedge clock) begin if (!reset) Reg[3:0] <= 4d0; else begin Reg[0] <= in; Reg[1] <= Reg[0]; Reg[2] <= Reg[1]; Reg[3] <= Reg[2]; end end
endmodule

<= non-blocking assignment

Use non-blocking assignments in sequential circuits;

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4-bit Up Counter
input reset, enable, clock; output [3:0] out; reg [3:0] out;

always @(posedge clock) begin if (reset) out[3:0] <= 4d0; else begin if (enable) begin if (out == 4d15) out[3:0] <= 4d0; else out <= out + 1b1; else out <= out; end end end

Synchronous Reset

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4-bit Up-Down Counter

always @(posedge clk) begin if (reset) out[2:0] = 3d0; else begin

if (enable) begin if (select) begin if (out == 4d15) out[3:0]<=4d0; else out <= out + 1b1; end else begin if (out == 4d0) out[3:0]<=4d15; else out <= out - 1b1; end end
end end

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