Introduction to CMOS VLSI Design

Lecture 1: Introduction and Basic Circuits

David Harris

Harvey Mudd College Spring 2004

Outline
q q q q q A Brief History CMOS Gate Design Pass Transistors Basic Combinational Circuits CMOS Latches & Flip-Flops

1: Circuits & Layout

CMOS VLSI Design

Slide 2

A Brief History
q 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments q 2003 Intel Pentium 4 processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) q 53% compound annual growth rate over 45 years No other technology has grown so fast so long q Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
1: Circuits & Layout CMOS VLSI Design Slide 3

Annual Sales
q 1018 transistors manufactured in 2003 100 million for every human on the planet
Global Semiconductor Billings (Billions of US$)
200

150

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50

0 1982

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Year
1: Circuits & Layout CMOS VLSI Design Slide 4

Invention of the Transistor

q Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable q 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire by Riordan, Hoddeson

1: Circuits & Layout

CMOS VLSI Design

Slide 5

Transistor Types
q Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density q Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration
1: Circuits & Layout CMOS VLSI Design Slide 6

MOS Integrated Circuits

q 1970 s processes usually had only nMOS transistors Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

q 1980s-present: CMOS processes for low idle power 7 1: Circuits & Layout CMOS VLSI Design Slide

Moore s Law
q 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months
1,000,000,000 100,000,000 10,000,000 Pentium 4 Pentium III Pentium II Pentium Pro Pentium

Integration Levels SSI: 10 gates

Intel486 80286 8086 Intel386

Transistors

1,000,000 100,000 10,000 1,000 8008 4004

MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates
Slide 8

8080

1970

1975

1980

1985

1990

1995

2000

Year

1: Circuits & Layout

CMOS VLSI Design

Corollaries
q Many other factors grow exponentially Ex: clock frequency, processor performance
10,000 1,000 4004 8008 8080 100 8086 80286 Intel386 10 Intel486 Pentium Pentium Pro/II/III 1 Pentium 4

1: Circuits & Layout

Clock Speed (MHz)

1970

1975

1980

1985

1990

1995

2000

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Year

CMOS VLSI Design

Slide 9

Transistors as Switches
q We can view MOS transistors as electrically controlled switches q Voltage at gate controls path from source to drain
g=0 d nMOS g s d pMOS g s s
CMOS VLSI Design

g=1 d

d OFF s d ON

ON s d OFF s

0: Introduction

Slide 10

CMOS Inverter
A 0 1 Y

VDD A Y

A
0: Introduction

GND
CMOS VLSI Design Slide 11

CMOS Inverter
A 0 1 0 Y

VDD OFF
A=1 Y=0

ON
A
0: Introduction

GND
CMOS VLSI Design Slide 12

CMOS Inverter
A 0 1 Y 1 0

VDD ON
A=0 Y=1

OFF
A
0: Introduction

GND
CMOS VLSI Design Slide 13

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y

Y A B

0: Introduction

CMOS VLSI Design

Slide 14

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1

ON A=0 B=0

ON Y=1 OFF OFF

0: Introduction

CMOS VLSI Design

Slide 15

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1

OFF A=0 B=1

ON Y=1 OFF ON

0: Introduction

CMOS VLSI Design

Slide 16

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1

ON A=1 B=0

OFF Y=1 ON OFF

0: Introduction

CMOS VLSI Design

Slide 17

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0

OFF A=1 B=1

OFF Y=0 ON ON

0: Introduction

CMOS VLSI Design

Slide 18

CMOS NOR Gate

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0

A B Y

0: Introduction

CMOS VLSI Design

Slide 19

3-input NAND Gate

q Y pulls low if ALL inputs are 1 q Y pulls high if ANY input is 0

0: Introduction

CMOS VLSI Design

Slide 20

3-input NAND Gate

q Y pulls low if ALL inputs are 1 q Y pulls high if ANY input is 0

A B C
0: Introduction CMOS VLSI Design

Slide 21

CMOS Gate Design

q Activity: Sketch a 4-input CMOS NOR gate

1: Circuits & Layout

CMOS VLSI Design

Slide 22

CMOS Gate Design

q Activity: Sketch a 4-input CMOS NOR gate

A B C D Y

1: Circuits & Layout

CMOS VLSI Design

Slide 23

Complementary CMOS
q Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network inputs a.k.a. static CMOS
pMOS pull-up network

output
nMOS pull-down network

Pull-up OFF Pull-down OFF Z (float) Pull-down ON 0

Pull-up ON 1 X (crowbar)

1: Circuits & Layout

CMOS VLSI Design

Slide 24

Series and Parallel

q q q q nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
a g1 g2 b (a) a g1 g2 b (b) 0 0 b ON 0 0 b OFF a 0 1 b OFF a 0 1 b OFF a 1 0 b OFF a 1 0 b OFF a 1 1 b OFF a 1 1 b ON a a

a g1 b (c) g2 0

a 0 b OFF 0

a 1 b ON 1

a 0 b ON 1

a 1 b ON

a g1 b (d) g2 0

a 0 b ON 0

a 1 b ON 1

a 0 b ON 1

a 1 b OFF

1: Circuits & Layout

CMOS VLSI Design

Slide 25

Conduction Complement
q Complementary CMOS gates always produce 0 or 1 q Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Y Requires parallel pMOS
A

q Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

1: Circuits & Layout

CMOS VLSI Design

Slide 26

Compound Gates
q Compound gates can do any inverting function q Ex: Y = AgB + CgD (AND-AND-OR-INVERT, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D

A (c) C A

B C

1: Circuits & Layout

CMOS VLSI Design

Slide 27

Example: O3AI
q Y = ( A + B + C )gD

1: Circuits & Layout

CMOS VLSI Design

Slide 28

Example: O3AI
q Y = ( A + B + C )gD

A B C D Y D A B C

1: Circuits & Layout

CMOS VLSI Design

Slide 29

Signal Strength
q Strength of signal How close it approximates ideal voltage source q VDD and GND rails are strongest 1 and 0 q nMOS pass strong 0 But degraded or weak 1 q pMOS pass strong 1 But degraded or weak 0 q Thus nMOS are best for pull-down network

1: Circuits & Layout

CMOS VLSI Design

Slide 30

Pass Transistors
q Transistors can be used as switches
g s d

g s d

1: Circuits & Layout

CMOS VLSI Design

Slide 31

Pass Transistors
q Transistors can be used as switches
g s d s g=1 s g s d s g=1 s d g=0 d d 1 Input 0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0 strong 1

g=0 g=0

1: Circuits & Layout

CMOS VLSI Design

Slide 32

Transmission Gates
q Pass transistors produce degraded outputs q Transmission gates pass both 0 and 1 well

1: Circuits & Layout

CMOS VLSI Design

Slide 33

Transmission Gates
q Pass transistors produce degraded outputs q Transmission gates pass both 0 and 1 well
Input g a gb g a gb
1: Circuits & Layout

Output

g = 0, gb = 1 a b b g = 1, gb = 0 a b g b a gb b a gb
CMOS VLSI Design

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

g b

Slide 34

Tristates
q Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y

EN A EN A EN Y Y

1: Circuits & Layout

CMOS VLSI Design

Slide 35

Tristates
q Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1

EN A EN A EN Y Y

1: Circuits & Layout

CMOS VLSI Design

Slide 36

Nonrestoring Tristate
q Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

EN A EN
1: Circuits & Layout CMOS VLSI Design Slide 37

Tristate Inverter
q Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A EN EN Y

1: Circuits & Layout

CMOS VLSI Design

Slide 38

Tristate Inverter
q Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A A EN EN Y Y Y A

EN = 0 Y = 'Z'
1: Circuits & Layout

EN = 1 Y=A
Slide 39

CMOS VLSI Design

Multiplexers
q 2:1 multiplexer chooses between two inputs
S D0 D1 0 1 Y

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

1: Circuits & Layout

CMOS VLSI Design

Slide 40

Multiplexers
q 2:1 multiplexer chooses between two inputs
S D0 D1 0 1 Y

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

Y 0 1 0 1

1: Circuits & Layout

CMOS VLSI Design

Slide 41

Gate-Level Mux Design

q Y = SD1 + SD0 (too many transistors) q How many transistors are needed?

1: Circuits & Layout

CMOS VLSI Design

Slide 42

Gate-Level Mux Design

q Y = SD1 + SD0 (too many transistors) q How many transistors are needed? 20

D1 S D0

D1 S D0
1: Circuits & Layout

4 2 4

2 4 2 2

CMOS VLSI Design

Slide 43

Transmission Gate Mux

q Nonrestoring mux uses two transmission gates

1: Circuits & Layout

CMOS VLSI Design

Slide 44

Transmission Gate Mux

q Nonrestoring mux uses two transmission gates Only 4 transistors

S D0 S D1 S
1: Circuits & Layout CMOS VLSI Design Slide 45

Inverting Mux
q Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing q Noninverting multiplexer adds an inverter
D0 S S S D1 Y S S S D0 S D1 S Y D0 D1 0 1 Y S

1: Circuits & Layout

CMOS VLSI Design

Slide 46

4:1 Multiplexer
q 4:1 mux chooses one of 4 inputs using two selects

1: Circuits & Layout

CMOS VLSI Design

Slide 47

4:1 Multiplexer
q 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0 Or four tristates
D0 S0 D0 D1 D2 D3 0 1 0 1 D3 0 1 S1 D1 Y D2 Y

1: Circuits & Layout

CMOS VLSI Design

Slide 48

D Latch
q When CLK = 1, latch is transparent D flows through to Q like a buffer q When CLK = 0, the latch is opaque Q holds its old value independent of D q a.k.a. transparent latch or level-sensitive latch

CLK D
Latch

CLK D

Q
Q

1: Circuits & Layout

CMOS VLSI Design

Slide 49

D Latch Design
q Multiplexer chooses D or old Q
CLK D 1 0 Q Q D CLK CLK CLK

Q Q

CLK

1: Circuits & Layout

CMOS VLSI Design

Slide 50

D Latch Operation
Q D CLK = 1 Q D CLK = 0 Q Q

CLK D Q
1: Circuits & Layout CMOS VLSI Design Slide 51

D Flip-flop
q When CLK rises, D is copied to Q q At all other times, Q holds its value q a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK

CLK
D

Flop

Q
Q

1: Circuits & Layout

CMOS VLSI Design

Slide 52

D Flip-flop Design
q Built from master and slave D latches
CLK CLK CLK
Latch

CLK QM Q CLK CLK

D CLK CLK

QM

Latch

Q CLK CLK

1: Circuits & Layout

CMOS VLSI Design

Slide 53

D Flip-flop Operation
D QM Q CLK = 0

QM

CLK = 1

CLK D Q

1: Circuits & Layout

CMOS VLSI Design

Slide 54

Race Condition
q Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition
CLK1 CLK1
Flop

CLK2
Flop

CLK2 Q2 Q1 Q2
CMOS VLSI Design Slide 55

Q1

1: Circuits & Layout

Nonoverlapping Clocks
q Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew q We will use them in this class for safe design Industry manages skew more carefully instead
2 D 2 2 QM 1 1 1 Q

2 1 2

1: Circuits & Layout

CMOS VLSI Design

Slide 56