Digital Systems

DI GI TAL SYSTEMS: Cour se Obj ect i ves and Lect ur e Pl an
Ai m: At t he end of t he course t he st udent will be able t o analyze, design, and

evaluat e digit al circuit s, of medium complexit y, t hat are based on SSI s, MSI s, and
programmable logic devices.
Modul e 1: Number Sy st ems and Codes ( 3)
Number syst ems: Binary, oct al, and hexadecimal number syst ems, binary
arit hmet ic. Codes: Binary code, excess- 3 code, gray code, and error det ect ion and
correct ion codes.
Modul e 2: Bool ean Al gebr a and Logi c Funct i ons ( 5)
Boolean algebra: Post ulat es and t heorems. Logic funct ions, minimizat ion of Boolean
funct ions using algebraic, Karnaugh map and Quine McClausky met hods.
Realizat ion using logic gat es
Modul e 3: Logi c Fami l i es ( 4)
Logic families: Charact erist ics of logic families. TTL, CMOS, and ECL families.
Modul e 4: Combi nat i onal Funct i ons ( 8)
Realizing logical expressions using different logic gat es and comparing t heir
performance. Hardware aspect s logic gat es and combinat ional I Cs: delays and
hazards. Design of combinat ional circuit s using combinat ional I Cs: Combinat ional
funct ions: code conversion, decoding, comparison, mult iplexing, demult iplexing,
addit ion, and subt ract ion.
Modul e 5: Anal y si s of Sequent i al Ci r cui t s ( 5)
St ruct ure of sequent ial circuit s: Moore and Melay machines. Flip- flops, excit at ion
t ables, conversions, pract ical clocking aspect s concerning flip- flops, t iming and
t riggering considerat ions. Analysis of sequent ial circuit s: St at e t ables, st at e diagrams
and t iming diagrams.
Modul e 6: Desi gni ng w i t h Sequent i al MSI s ( 6)
Realizat ion of sequent ial funct ions using sequent ial MSI s: count ing, shift ing,
sequence generat ion, and sequence det ect ion.
Modul e 7: PLDs ( 3)
Programmable Logic Devices: Archit ect ure and charact erist ics of PLDs,
Modul e 8: Desi gn of Di gi t al Sy st ems ( 6)
St at e diagrams and t heir feat ures. Design flow: funct ional part it ioning, t iming
relat ionships, st at e assignment , out put racing. Examples of design of digit al syst ems
using PLDs

Lect ur e Pl an

Modul es Lear ni ng Uni t s Hour s
per
t opi c
Tot al
Hour s
1. Binary, oct al and hexadecimal number
syst ems, and conversion of number wit h
one radix t o anot her
1. 5 1. Number
Syst ems and
Codes
2. Different binary codes 1. 5

3
3. Boolean algebra and Boolean operat ors 1. 5
4. Logic Funct ions 1
5. Minimizat ion of logic funct ions using
Karnaugh - map
1. 5
2. Logic
Funct ions
6. Quine- McClausky met hod of minimizat ion of
logic funct ions
1

5
7. I nt roduct ion t o Logic families 0. 5
8. TTL family 1
9. CMOS family 1. 5
3. Logic Families
10. Elect rical charact erist ics of logic families 1

4
11. I nt roduct ion t o combinat ional circuit s, logic
convent ion, and realizat ion of simple
combinat ional funct ions using gat es
2
12. I mplicat ions of delay and hazard 1
13. Realizat ion of adders and subt ract ors 2
14. Design of code convert ers, comparat ors,
and decoders
2
4. Combinat ional
Circuit s

15. Design of mult iplexers, demult iplexers, 1

8

16. I nt roduct ion t o sequent ial circuit s: Moore
and Mealy machines
1
17. I nt roduct ion t o flip- flops like SR, JK, D & T
wit h t rut h t ables, logic diagrams, and
t iming relat ionships
1
18. Conversion of Flip- Flops, Excit at ion t able 1
5. Analysis of
Sequent ial
Circuit s
19. St at e t ables, and realizat ion of st at e st ables 2

5
20. Design of shift regist ers and count ers 2
21. Design of count ers 2
6. Design wit h
Sequent ial MSI s
22. Design of sequence generat ors and
det ect ors
2

6
23. I nt roduct ion t o Programmable Devices 1 7. PLDs
24. Archit ect ure of PLDs 2

3
25. St at e diagrams and t heir feat ures 2
26. Design flow 1
8. Design of
Digit al Syst ems
27. Design of digit al syst ems using PLDs 3

6

Lear ni ng Obj ect i ves of t he Cour se
1. Recal l
1.1 List different crit eria t hat could be used for opt imizat ion of a digit al circuit .
1.2 List and describe different problems of digit al circuit s int roduced by t he hardware
limit at ions.
2. Compr ehensi on
2.1 Describe t he significance of different crit eria for design of digit al circuit s.
2.2 Describe t he significance of different hardware relat ed problems encount ered in
digit al circuit s.
2.3 Draw t he t iming diagrams for ident ified signals in a digit al circuit .
3. Appl i cat i on
3.1 Det ermine t he out put and performance of given combinat ional and sequent ial
circuit s.
3.2 Det ermine t he performance of a given digit al circuit wit h regard t o an ident ified
opt imizat ion crit erion.
4. Anal y si s
4. 1 Compare t he performances of combinat ional and sequent ial circuit s implement ed
wit h SSI s/ MSI s and PLDs.
4. 2 Det ermine t he funct ion and performance of a given digit al circuit .
4. 3 I dent ify t he fault s in a given circuit and det ermine t he consequences of t he same
on t he circuit performance.
4. 4 Draw conclusions on t he behavior of a given digit al circuit wit h regard t o
hazards, asynchronous input s, and out put races.
4. 5 Det ermine t he appropriat eness of t he choice of t he I Cs used in a given digit al
circuit .
4. 6 Det ermine t he t ransit ion sequence of a given st at e in a st at e diagram for a given
input sequence.
5. Sy nt hesi s
5.1 Generat e mult iple digit al solut ions t o a verbally described problem.
5.2 Modify a given digit al circuit t o change it s performance as per specificat ions.
6. Eval uat i on
6.1 Evaluat e t he performance of a given digit al circuit .
6.2 Assess t he performance of a given digit al circuit wit h Moore and Melay
configurat ions.
6.3 Compare t he performance of given digit al circuit s wit h respect t o t heir speed,
power consumpt ion, number of I Cs, and cost .

Di gi t al Syst ems: Mot i vat i on
A digit al cir cuit is one t hat is built wit h devices wit h t wo well- defined st at es. Such circuit s
can process informat ion represent ed in binary form. Syst ems based on digit al circuit s t ouch
all aspect s our present day lives. The present day home product s including elect ronic
games and appliances, communicat ion and office aut omat ion product s, comput ers wit h a
wide range of capabilit ies, and indust rial inst rument at ion and cont rol syst ems, elect ro-
medical equipment , and defence and aerospace syst ems are heavily dependent on digit al
circuit s. Many fields t hat emerged lat er t o digit al elect ronics have peaked and levelled off,
but t he applicat ion of digit al concept s appears t o be st ill growing exponent ially. This
unprecedent ed growt h is powered by t he semiconduct or t echnology, which enables t he
int roduct ion of more and complex int egrat ed circuit s. The complexit y of an int egrat ed
circuit is measured in t erms of t he number of t ransist ors t hat can be int egrat ed int o a
single unit . The number of t ransist ors in a single int egrat ed circuit has been doubling every
eight een mont hs ( Moore Law) for several decades and reached t he figure of almost one
billion t ransist ors per chip. This allowed t he circuit designers t o provide more and more
complex funct ions in a single unit .
The int roduct ion of programmable int egrat ed circuit s in t he form of microprocessors in 70s
complet ely t ransformed every facet of elect ronics. While fixed funct ion int egrat ed circuit s
and microprocessors coexist ed for considerable t ime, t he need t o make t he equipment
smaller and port able lead t o replacement of fixed funct ion devices wit h pr ogrammable
devices. Wit h t he all pervasive presence of t he microprocessor and t he increasing usage of
ot her programmable circuit s like PLDs ( Programmable Logic devices) , FPGAs ( Field
Programmable Gat e Arrays) and ASI Cs ( Applicat ion Specific I nt egrat ed Circuit s) , t he very
nat ure of digit al syst ems is cont inuously changing.
The cent ral role of digit al circuit s in all our professional and personal lives makes it
imperat ive t hat every elect rical and elect ronics engineer acquire good knowledge of
relevant basic concept s and abilit y t o work wit h digit al circuit s.
At present many of t he undergraduat e programmes offer t wo t o four courses in t he area of
digit al syst ems, wit h at least t wo of t hem being core courses. The course under
considerat ion const it ut es t he first course in t he area of digit al syst ems. The rat e of
obsolescence of knowledge, design met hods, and design t ools is uncomfort ably high. Even
t he first level course in digit al elect ronics is not exempt from t his obsolescence.
Any course in elect ronics should enable t he st udent s t o design circuit s t o meet some st at ed
requirement s as encount ered in real life sit uat ions. However, t he design approaches should
be based on a sound underst anding of t he underlying principles. The basic feat ure of all
design problems is t hat all of t hem admit mult iple solut ions. The select ion of t he final
solut ion depends on a variet y of crit eria t hat could include t he size and cost of t he subst rat e
on which t he component s are assembled, t he cost of component s, manufact urabilit y,

reliabilit y, speed et c.
The course cont ent s are designed t o enable t he st udent s t o design digit al circuit s of
medium level of complexit y t aking t he funct ional and hardware aspect s in an int egrat ed
manner wit hin t he cont ext of commercial and manufact uring const raint s. However, no
compromises are made wit h regard t o t heoret ical aspect s of t he subj ect .

Lear ni ng Obj ect i ves
Modul e 1: Number Sy st ems and Codes ( 3)
Number syst ems: Binary, oct al, and hexadecimal number syst ems, binary
arit hmet ic. Codes: Binary code, excess- 3 code, gray code, error det ect ion and
correct ion codes.
Recal l
1. Describe t he format of numbers of different radices?
2. What is parit y of a given number?
Compr ehensi on
1. Explain how a number wit h one radix is convert ed int o a number wit h anot her
radix.
2. Summarize t he advant ages of using different number syst ems.
3. I nt erpret t he arit hmet ic operat ions of binary numbers.
4. Explain t he usefulness of different coding schemes.
5. Explain how errors are det ect ed and/ or correct ed using different codes.
Appl i cat i on
1. Convert a given number from one syst em t o an equivalent number in anot her
syst em.
2. I llust rat e t he const ruct ion of a weight ed code.
Anal y si s: Ni l
Sy nt hesi s: Ni l
Eval uat i on: Ni l
Digital Electronics
Module 1: Number Systems and
Codes - Number Systems
N.J. Rao
Indian Institute of Science
id379776 pdfMachine by Broadgun Software - a great PDF writer! - a great PDF creator! - http://www.pdfmachine.com http://www.broadgun.com
December 2006 N.J. Rao M1L1 2
Numbers
We use numbers
to communicate
to perform tasks
to quantify
to measure
Numbers have become symbols of the present era
Many consider what is not expressible in terms of
numbers is not worth knowing
Number Systems in use
Symbolic number system
uses Roman numerals (I = 1, V = 5, X = 10, L = 50,
C = 100, D = 500 and M = 1000)
still used in some watches
Weighted position system
Decimal system is the most commonly used
Decimal numbers are based on Indian numerals
Radix used is 10
Other weighted position systems
Advent of electronic devices with two states created a
possibility of working with binary numbers
Binary numbers are most extensively used
Binary system uses radix 2
Octal system uses radix 8
Hexa-decimal system uses radix 16
Weighted Position Number System
Value associated with a digit is dependent on its position
The value of a number is weighted sum of its digits
2357 = 2 x 10
3
+ 3 x 10
2
+ 5 x 10
1
+ 7 x 10
0
Decimal point allows negative and positive powers of 10
526.47 = 5 x 10
2
+2 x 10
1
+ 6 x 10
0
+ 4 x 10
-1
+ 7 x 10
-2
10 is called the base or radix of the number system
General positional number system
Any integer > 2 can serve as the radix
Digit position i has weight r
i
.
The general form of a number is
d
p-1
d
p-2
, .... d
1
, d
0
. d
-1
d
-2
.... d
-n
p digits to the left of the point (radix point) and n digits to
the right of the point
General positional number system (2)
The value of the number is
D =
Leading and trailing zeros have no values
The values d
i
s can take are limited by the radix value
A number like (357)
5
is incorrect

1 p
n i
i
i
r d
Binary Number System
Uses 2 as its radix
Has only two numerals, 0 and 1
Example:
(N)
2
= (11100110)
2
It is an eight digit binary number
The binary digits are also known as bits
(N)
2
is an 8-bit number
Binary numbers to Decimal Number
(N)
2
= (11100110)
2
Its decimal value is given by,
(N)
2
= 1 x 2
7
+ 1 x 2
6
+ 1 x 2
5
+ 0 x 2
4
+ 0 x 2
3
+ 1 x 2
2
+ 1 x 2
1
+ 0 x 2
0
= 128 + 64 + 32 + 0 + 0 + 4 + 2 + 0 = (230)
10
Binary fractional number to
Decimal number
A binary fractional number (N)
2
= 101.101
Its decimal value is given by
(N)2 = 1 x 2
2
+ 0 x 2
1
+ 1 x 2
0
+ 1 x 2
-1
+ 0 x 2
-2
+ 1 x 2
-3
= 4 + 0 + 1 + + 0 +
= 5 + 0.5 + 0.125 = (5.625)
10
1
2
1
8
1
8
Some features of Binary Numbers
Require very long strings of 1s and 0s
Some simplification can be done through grouping
3-bit groupings: Octal (radix 8) groups three binary digits
Digits will have one of the eight values 0, 1, 2, 3, 4, 5, 6
and 7
4-digit groupings: Hexa-decimal (radix 16)
Digits will have one of the sixteen values 0 through 15.
Decimal values from 10 to 15 are designated as A (=10),
B (=11), C (=12), D (=13), E (=14) and F (=15)
Conversion of binary numbers
Conversion to an octal number
Group the binary digits into groups of three
(11011001)
2
= (011) (011) (001) = (331)
8
Conversion to an hexa-decimal number
Group the binary digits into groups of four
(11011001)
2
= (1101) (1001) = (D9)
16
Changing the radix of numbers
Conversion requires, sometimes, arithmetic operations
The decimal equivalent value of a number in any radix
D =
Examples
(331)
8
= 3 x 8
2
+ 3 x 8
1
+ 1 x 8
0
= 192 + 24 + 1 = (217)
10
(D9)
16
= 13 x 16
1
+ 9 x 16
0
= 208 + 9 = (217)
10
(33.56)
8
= 3 x 8
1
+ 3 x 8
0
+ 5 x 8
-1
+ 6 x 8
-2
= (27.69875)
10
(E5.A)
16
= 14 x 16
1
+ 5 x 16
0
+ 10 x 16
-1
= (304.625)
10

1 p
n i
i
i
r d
Conversion of decimal numbers to
numbers with radix r
Represent a number with radix r as
D = ((... ((d
n-1
).r + d
n-2
) r + ....).r + d
1
).r + d
0
To convert a number with radix r to a decimal number
Divide the right hand side by r
Remainder: d
0
Quotient: Q = ((... ((d
n-1
).r + d
n-2
) r + ....).r + d
1
Division of Q by r gives d
1
as the remainder
so on
Example of Conversion
Quotient Remainder
156 2 78 0
78 2 39 0
39 2 19 1
19 2 9 1
9 2 4 1
4 2 2 0
2 2 1 0
1 2 0 1
(156)
10
= (10011100)
2
Example of Conversion
Quotient Remainder
678 8 84 6
84 8 10 4
10 8 1 2
1 8 0 1
(678)
10
= (1246)
8
Quotient Remainder
678 16 42 6
42 16 2 A
2 16 0 2
(678)
10
= (2A6)
16
Negative Numbers
Sign-Magnitude representation
+ sign before a number indicates it as a positive
number
- sign before a number indicates it as a negative
number
Not very convenient on computers
Replace + sign by 0 and - by 1
(+1100101)
2
(01100101)
2
(+101.001)
2
(0101.001)
2
(-10010)
2
(110010)
2
(-110.101)
2
--. (1110.101)
2
Representing signed numbers
Diminished Radix Complement (DRC) or
(r-1) - complement
Radix Complement (RXC) or r-complement
Binary numbers
DRC is known as ones-complement
RXC is known as twos-complement
Decimal numbers
DRC is known as 9s-complement
RXC is known as 10s-complement
Ones Complement Representation
The most significant bit (MSD) represents the sign
If MSD is a 0
The number is positive
Remaining (n-1) bits directly indicate the magnitude
If the MSD is 1
The number is negative
Complement of all the remaining (n-1) bits gives the
magnitude
Example: Ones complement
1111001(1)(111001)
First (sign) bit is 1: The number is negative
Ones Complement of 111001 000110
(6)
10
Range of n-bit numbers
Ones complement numbers:
0111111 + 63
0000110 --> + 6
0000000 --> + 0
1111111 --> + 0
1111001 --> - 6
1000000 --> - 63
0 is represented by 000.....0 and 111.....1
7- bit number covers the range from +63 to -63.
n-bit number has a range from +(2
n-1
- 1) to -(2
n-1
- 1)
Ones complement of a number
Complement all the digits
If A is an integer in ones complement form, then
ones complement of A = -A
This applies to fractions as well.
A = 0.101 (+0.625)
10
Ones complement of A = 1.010, (-0.625)
10
Mixed number
B = 010011.0101 (+19.3125)
10
Ones complement of B = 101100.1010 (- 19.3125)
10
Twos Complement Representation
If MSD is a 0
The number is positive
Remaining (n-1) bits directly indicate the magnitude
If the MSD is 1
The number is negative
Magnitude is obtained by complementing all the
remaining (n-1) bits and adding a 1
Example: Twos complement
1111010(1)(111010)
First (sign) bit is 1: The number is negative
Complement 111010 and add 1000101 + 1
= 000110 = (6)
10
Range of n-bit numbers
Twos complement numbers:
0111111 + 63
0000110 + 6
0000000 + 0
1111010 - 6
1000001 - 63
1000000 - 64
0 is represented by 000.....0
7- bit number covers the range from +63 to -64.
n-bit number has a range from +(2
n-1
- 1) to -(2
n-1
)
Twos complement of a number
Complement all the digits and add 1 to the LSB
If A is an integer in ones complement form, then
Twos complement of A = -A
This applies to fractions as well
A = 0.101 (+0.625)10
Twos complement of A = 1.011(-0.625)
10
Mixed number
B = 010011.0101 (+19.3125)
10
Twos complement of B = 101100.1011(- 9.3125)
10
Number Sy st ems
We all use numbers t o communicat e and perform several t asks in our daily lives.
Our present day world is charact erized by measurement s and numbers associat ed
wit h everyt hing. I n fact , many consider if we cannot express somet hing in t erms of
numbers is not wort h knowing. While t his is an ext reme view t hat is difficult t o
j ust ify, t here is no doubt t hat quant ificat ion and measurement , and consequent ly
usage of numbers, are desirable whenever possible. Manipulat ion of numbers is one
of t he early skills t hat t he present day child is t rained t o acquire. The present day
t echnology and t he way of life require t he usage of several number syst ems. Usage
of decimal numbers st art s very early in ones life. Therefore, when one is confront ed
wit h number syst ems ot her t han decimal, some t ime during t he high- school years, it
calls for a fundament al change in ones framework of t hinking.
There have been t wo t ypes of numbering syst ems in use t hrough out t he world.
One t ype is symbolic in nat ure. Most import ant example of t his symbolic numbering
syst em is t he one based on Roman numerals
I = 1, V = 5, X = 10, L = 50, C = 100, D = 500 and M = 1000
I I MVI I - 2007
While t his syst em was in use for several cent uries in Europe it is complet ely
superseded by t he weight ed- posit ion syst em based on I ndian numerals. The Roman
number syst em is st ill used in some places like wat ches and release dat es of movies.
The weight ed- posit ional syst em based on t he use of radix 10 is t he most commonly
used numbering syst em in most of t he t ransact ions and act ivit ies of t odays world.
However, t he advent of comput ers and t he convenience of using devices t hat have
t wo well defined st at es brought t he binary syst em, using t he radix 2, int o ext ensive
use. The use of binary number syst em in t he field of comput ers and elect ronics also
lead t o t he use of oct al ( based on radix 8) and hex- decimal syst em ( based on radix
16) . The usage of binary numbers at various levels has become so essent ial t hat it
is also necessary t o have a good underst anding of all t he binary arit hmet ic
operat ions.
Here we explore t he weight ed- posit ion number syst ems and conversion from one
syst em t o t he ot her.

Wei ght ed- Posi t i on Number Sy st em
I n a weight ed- posit ion numbering syst em using I ndian numerals t he value
associat ed wit h a digit is dependent on it s posit ion. The value of a number is
weight ed sum of it s digit s.
Consider t he decimal number 2357. I t can be expressed as
2357 = 2 x 10
3
+ 3 x 10
2
+ 5 x 10
1
+ 7 x 10
0

Each weight is a power of 10 corresponding t o t he digit s posit ion. A decimal point
allows negat ive as well as posit ive powers of 10 t o be used;
526. 47 = 5 x 10
2
+ 2 x 10
1
+ 6 x 10
0
+ 4 x 10
- 1
+ 7 x 10
- 2

Here, 10 is called t he base or radix of t he number syst em. I n a general posit ional
number syst em, t he radix may be any int eger r > 2, and a digit posit ion i has weight
r
i
. The general form of a number in such a syst em is
d
p- 1
d
p- 2
, . .. . d
1
, d
0
. d
- 1
d
- 2
. .. . d
- n

where t here are p digit s t o t he left of t he point ( called radix point ) and n digit s t o t he
right of t he point . The value of t he number is t he sum of each digit mult iplied by t he
corresponding power of t he radix.
D =

=
1 p
n i
i
i
r d
Except for possible leading and t railing zeros, t he represent at ion of a number in
posit ional syst em is unique ( 00256. 230 is t he same as 256. 23) . Obviously t he
values d
i
s can t ake are limit ed by t he radix value. For example a number like
( 356)
5
, where t he suffix 5 represent s t he radix will be incorrect , as t here can not be
a digit like 5 or 6 in a weight ed posit ion number syst em wit h radix 5.
I f t he radix point is not shown in t he number, t hen it is assumed t o be locat ed near
t he last right digit t o it s immediat e right . The symbol used for t he radix point is a
point ( . ) . However, a comma is used in some count ries. For example 7, 6 is used,
inst ead of 7. 6, t o represent a number having seven as it s int eger component and six
as it s fract ional.
As much of t he present day elect ronic hardware is dependent on devices t hat work
reliably in t wo well defined st at es, a numbering syst em using 2 as it s radix has
become necessary and popular. Wit h t he radix value of 2, t he binary number syst em
will have only t wo numerals, namely 0 and 1.
Consider t he number ( N)
2
= ( 11100110)
2
.
I t is an eight digit binary number. The binary digit s are also known as bit s.
Consequent ly t he above number would be referred t o as an 8- bit number. I t s
decimal value is given by
( N)
2
= 1 x 2
7
+ 1 x 2
6
+ 1 x 2
5
+ 0 x 2
4
+ 0 x 2
3
+ 1 x 2
2
+ 1 x 2
1
+ 0 x 2
0

= 128 + 64 + 32 + 0 + 0 + 4 + 2 + 0 = ( 230)
10
Consider a binary fract ional number ( N)
2
= 101. 101.
I t s decimal value is given by
( N)
2
= 1 x 2
2
+ 0 x 2
1
+ 1 x 2
0
+ 1 x 2
- 1
+ 0 x 2
- 2
+ 1 x 2
- 3

= 4 + 0 + 1 +
1
2 + 0 +
1
8
= 5 + 0. 5 + 0. 125 = ( 5. 625)
10

From here on we consider any number wit hout it s radix specifically ment ioned, as a
decimal number.
Wit h t he radix value of 2, t he binary number syst em requires very long st rings of 1s
and 0s t o represent a given number. Some of t he problems associat ed wit h handling
large st rings of binary digit s may be eased by grouping t hem int o t hree digit s or four
digit s. We can use t he following groupings.
Oct al ( radix 8 t o group t hree binary digit s)
Hexadecimal ( radix 16 t o group four binary digit s)
I n t he oct al number syst em t he digit s will have one of t he following eight values 0, 1,
2, 3, 4, 5, 6 and 7.
I n t he hexadecimal syst em we have one of t he sixt een values 0 t hrough 15.
However, t he decimal values from 10 t o 15 will be represent ed by alphabet A ( = 10) ,
B ( = 11) , C ( = 12) , D ( = 13) , E ( = 14) and F ( = 15) .
Conversion of a binary number t o an oct al number or a hexadecimal number is very
simple, as it requires simple grouping of t he binary digit s int o groups of t hree or
four. Consider t he binary number 11011011. I t may be convert ed int o oct al or
hexadecimal numbers as
( 11011001)
2
= ( 011) ( 011) ( 001) = ( 331)
8

= ( 1101) ( 1001) = ( D9)
16

Not e t hat adding a leading zero does not alt er t he value of t he number. Similarly for
grouping t he digit s in t he fract ional part of a binary number, t railing zeros may be
added wit hout changing t he value of t he number.
Number Sy st em Conv er si ons
I n general, conversion bet ween numbers wit h different radices cannot be done by
simple subst it ut ions. Such conversions would involve arit hmet ic operat ions. Let us
work out procedures for convert ing a number in any radix t o radix 10, and vice-
versa. The decimal equivalent value of a number in any radix is given by t he
formula
D =

=
1 p
n i
i
i
r d
where r is t he radix of t he number and t here are p digit s t o t he left of t he radix point
and n digit s t o t he right . Decimal value of t he number is det ermined by convert ing
each digit of t he number t o it s radix- 10 equivalent and expanding t he formula using
radix- 10 arit hmet ic.
Some examples are:
( 331)
8
= 3 x 8
2
+ 3 x 8
1
+ 1 x 8
0
= 192 + 24 + 1 = ( 217)
10

( D9)
16
= 13 x 16
1
+ 9 x 16
0
= 208 + 9 = ( 217)
10

( 33. 56)
8
= 3 x 8
1
+ 3 x 8
0
+ 5 x 8
- 1
+ 6 x 8
- 2
= ( 27. 69875)
10

( E5. A)
16
= 14 x 16
1
+ 5 x 16
0
+ 10 x 16
- 1
= ( 304. 625)
10

The conversion formula can be rewrit t en as
D = ( ( . .. ( ( d
n- 1
) . r + d
n- 2
) r + . . .. ) . r + d
1
) . r + d
0

This forms t he basis for convert ing a decimal number D t o a number wit h radix r. I f
we divide t he right hand side of t he above formula by r, t he remainder will be d
0
,
and t he quot ient will be
Q = ( ( .. . ( ( d
n- 1
) . r + d
n- 2
) r + . . .. ) . r + d
1

Thus, d
0
can be comput ed as t he remainder of t he long division of D by t he radix r.
As t he quot ient Q has t he same form as D, anot her long division by r will give d
1
as
t he remainder. This process can cont inue t o produce all t he digit s of t he number
wit h radix r. Consider t he following examples.
Quot ient Remainder
156 2 78 0
78 2 39 0
39 2 19 1
19 2 9 1
9 2 4 1
4 2 2 0
2 2 1 0
1 2 0 1
( 156)
10
= ( 10011100)
2

Quot ient Remainder
678 8 84 6
84 8 10 4
10 8 1 2
1 8 0 1
( 678)
10
= ( 1246)
8

Quot ient Remainder
678 16 42 6
42 16 2 A
2 16 0 2
( 678)
10
= ( 2A6)
16

Repr esent at i on of Negat i v e Number s
I n our t radit ional ar it hmet ic we use t he + sign before a number t o indicat e it as a
posit ive number and a - sign t o indicat e it as a negat ive number. We usually omit t he
sign before t he number if it is posit ive. This met hod of represent at ion of numbers is
called sign- magnit ude represent at ion. But using + and - signs on a comput er is
not convenient , and it becomes necessary t o have some ot her convent ion t o represent
t he signed numbers. We replace + sign wit h 0 and - wit h 1 . These t wo symbols
already exist in t he binary syst em. Consider t he following examples:
( + 1100101)
2
( 01100101)
2

( + 101. 001)
2
( 0101. 001)
2

( - 10010)
2
( 110010)
2

( - 110. 101)
2
( 1110. 101)
2

I n t he sign- magnit ude represent at ion of binar y numbers t he first digit is always t reat ed
separat ely. Therefore, in working wit h t he signed binary numbers in sign- magnit ude
form t he leading zeros should not be ignored. However, t he leading zeros can be
ignored aft er t he sign bit is separat ed. For example,
1000101. 11 = - 101. 11
While t he sign- magnit ude represent at ion of signed numbers appears t o be nat ural
ext ension of t he t radit ional arit hmet ic, t he arit hmet ic operat ions wit h signed numbers in
t his form are not t hat very convenient , eit her for implement at ion on t he comput er or for
hardware implement at ion. There are t wo ot her met hods of r epresent ing signed
numbers.
Diminished Radix Complement ( DRC) or ( r - 1) - complement
Radix Complement ( RX) or r- complement
When t he numbers are in binary form
Diminished Radix Complement will be known as ones- complement
Radix complement will be known as t wos- complement .
I f t his represent at ion is ext ended t o t he decimal numbers t hey will be known as 9s-
complement and 10s- complement respect ively.
One s Compl ement Repr esent at i on
Let A be an n- bit signed binary number in ones complement form.
The most significant bit represent s t he sign. I f it is a 0 t he number is posit ive and if it
is a 1 t he number is negat ive.

The remaining ( n- 1) bit s represent t he magnit ude, but not necessarily as a simple
weight ed number.
Consider t he following ones complement numbers and t heir decimal equivalent s:
0111111 + 63
0000110 - - > + 6
0000000 - - > + 0
1111111 - - > + 0
1111001 - - > - 6
1000000 - - > - 63
There are t wo represent at ions of 0 , namely 000. . . . . 0 and 111. . . . . 1.
From t hese illust rat ions we observe
I f t he most significant bit ( MSD) is zero t he remaining ( n- 1) bit s direct ly indicat e
t he magnit ude.
I f t he MSD is 1, t he magnit ude of t he number is obt ained by t aking t he
complement of all t he r emaining ( n- 1) bit s.
For example consider ones complement represent at ion of - 6 as given above.
Leaving t he first bit 1 for t he sign, t he remaining bit s 111001 do not direct ly
represent t he magnit ude of t he number - 6.
Take t he complement of 111001, which becomes 000110 t o det ermine t he
magnit ude.
I n t he example shown above a 7- bit number can cover t he range from + 63 t o - 63. I n
general an n- bit number has a range from + ( 2
n- 1
- 1) t o - ( 2
n- 1
- 1) wit h t wo
represent at ions for zero.
The represent at ion also suggest s t hat if A is an int eger in ones complement form, t hen
ones complement of A = - A
Ones complement of a number is obt ained by merely complement ing all t he digit s.
This relat ionship can be ext ended t o fract ions as well.
For example if A = 0. 101 ( + 0. 625)
10
, t hen t he ones complement of A is 1. 010, which is
ones complement represent at ion of ( - 0. 625)
10
. Similarly consider t he case of a mixed
number.
A = 010011. 0101 ( + 19. 3125)
10

Ones complement of A = 101100. 1010 ( - 19. 3125)
10

This relat ionship can be used t o det ermine ones complement represent at ion of negat ive
decimal numbers.
Ex ampl e 1: What is ones complement binary represent at ion of decimal number - 75?
Decimal number 75 requires 7 bit s t o represent it s magnit ude in t he binary form. One
addit ional bit is needed t o represent t he sign. Therefore,
ones complement represent at ion of 75 = 01001011
ones complement represent at ion of - 75 = 10110100
Tw o s Compl ement Repr esent at i on
Let A be an n- bit signed binary number in t wos complement form.
The most significant bit represent s t he sign. I f it is a 0 , t he number is posit ive,
and if it is 1 t he number is negat ive.
The remaining ( n- 1) bit s represent t he magnit ude, but not as a simple weight ed
number.
Consider t he following t wos complement numbers and t heir decimal equivalent s:
0111111 + 63
0000110 + 6
0000000 + 0
1111010 - 6
1000001 - 63
1000000 - 64
There is only one represent at ion of 0 , namely 000. . . . 0.
From t hese illust rat ions we observe
I f most significant bit ( MSD) is zero t he remaining ( n- 1) bit s direct ly indicat e t he
magnit ude.
I f t he MSD is 1, t he magnit ude of t he number is obt ained by t aking t he complement of
all t he remaining ( n- 1) bit s and adding a 1.
Consider t he t wos complement represent at ion of - 6.
We assume we are represent ing it as a 7- bit number.
Leave t he sign bit .
The remaining bit s are 111010. These have t o be complement ed ( t hat is
000101) and a 1 has t o be added ( t hat is 000101 + 1 = 000110 = 6) .

I n t he example shown above a 7- bit number can cover t he range from + 63 t o - 64. I n
general an n- bit number has a range from + ( 2
n- 1
- 1) t o - ( 2
n- 1
) wit h one represent at ion
for zero.
The represent at ion also suggest s t hat if A is an int eger in t wos complement form, t hen
Twos complement of A = - A
Twos complement of a number is obt ained by complement ing all t he digit s and adding
1 t o t he LSB.
This relat ionship can be ext ended t o fract ions as well.
I f A = 0. 101 ( + 0. 625)
10
, t hen t he t wos complement of A is 1. 011, which is t wos
complement represent at ion of ( - 0. 625)
10
.
Similarly consider t he case of a mixed number.
A = 010011. 0101 ( + 19. 3125)
10

Twos complement of A = 101100. 1011 ( - 19. 3125)
10
This relat ionship can be used t o det ermine t wos complement represent at ion of negat ive
decimal numbers.
Ex ampl e 2: What is t wos complement binary represent at ion of decimal number - 75?
Decimal number 75 requires 7 bit s t o represent it s magnit ude in t he binary form. One
addit ional bit is needed t o represent t he sign. Therefore,
Twos complement represent at ion of 75 = 01001011
Twos complement represent at ion of - 75 = 10110101

M1L1: Number Sy st ems
Mult iple Choice Quest ions
1. Which number syst em is underst ood easily by t he comput er?
( a) Binary ( b) Decimal ( c) Oct al ( d) Hexadecimal
2. How many symbols are used in t he decimal number syst em?
( a) 2 ( b) 8 ( c) 10 ( d) 16
3. How are number syst ems generally classified?
a. Condit ional or non condit ional
b. Posit ional or non posit ional
c. Real or imaginary
d. Lit eral or numerical
4. What does ( 10)
16
represent in decimal number syst em?
( a) 10 ( b) 0A ( c) 16 ( d) 15
5. How many bit s have t o be grouped t oget her t o convert t he binary number t o it s
corresponding oct al number?
( a) 2 ( b) 3 ( c) 4 ( d) 5
6. Which bit represent s t he sign bit in a signed number syst em?
a. Left most bit
b. Right most bit
c. Left cent re
d. Right cent re
7. The ones complement of 1010 is
( a) 1100 ( b) 0101 ( c) 0111 ( d) 1011
8. How many bit s are required t o cover t he numbers from + 63 t o - 63 in ones
complement represent at ion?
( a) 6 ( b) 7 ( c) 8 ( d) 9
M1L1: Number Syst ems
Pr obl ems
1. Perform t he following number syst em conversions:
( a) 10110111
2
= ?
10
( b) 5674
10
= ?
2
( c) 10011100
2
= ?
8
( d) 2453
8
= ?
2
( e) 111100010
2
= ?
16
( f) 68934
10
= ?
2

( g) 10101. 001
2
= ?
10
( h) 6FAB7
16
= ?
10
( i) 11101. 101
2
= ?
8
( j ) 56238
16
= ?
2

2. Convert t he following hexadecimal numbers int o binary and oct al numbers
( a) 78AD ( b) DA643 ( c) EDC8
( d) 3245 ( e) 68912 ( f) AF4D
3. Convert t he following oct al numbers int o binary and hexadecimal numbers
( a) 7643 ( b) 2643 ( c) 1034
( d) 3245 ( e) 6712 ( f) 7512
4. Convert t he following numbers int o binary:
( a) 1236
10
( b) 2349
10
( c) 345. 275
10

( d) 4567
8
( e) 45. 65
8
( f) 145. 23
8

( g) ADF5
16
( h) AD. F3
16
( i) 12. DA
16

5. What is t he range of unsigned decimal values t hat can be represent ed by 8 bit s?
6. What is t he range of signed decimal values t hat can be represent ed by 8 bit s?
7. How many bit s are required t o represent decimal values ranging from 75 t o - 75?
8. Represent each of t he following values as a 6- bit signed binary number in ones
complement and t wos complement forms.
( a) 28 ( b) - 21 ( c) - 5 ( d) - 13
9. Det ermine t he decimal equivalent of t wos complement numbers given below:
( a) 1010101 ( b) 0111011 ( c) 11100010

Digital Electronics
Module 1:Number Systems and
Codes - Codes
N.J. Rao
Need for Coding
Information sent over a noisy channel is likely to be
distorted
Information is coded to facilitate
Efficient transmission
Error detection
Error correction
Coding
Coding is the process of altering the characteristics of
information to make it more suitable for intended
application
Coding schemes depend on
Security requirements
Complexity of the medium of transmission
Levels of error tolerated
Need for standardization
Decoding
Decoding is the process of reconstructing source
information from the received encoded information
Decoding can be more complex than coding if there is no
prior knowledge of coding schemes
Bit combinations
Bit - a binary digit 0 or 1
Nibble - a group of four bits
Byte - a group of eight bits
Word - a group of sixteen bits;
(Sometimes used to designate 32 bit or 64 bit
groups of bits)
Binary coding
Assign each item of information a unique combination of 1s
and 0s
n is the number of bits in the code word
x be the number of unique words
If n = 1, then x = 2 (0, 1)
n = 2, then x = 4 (00, 01, 10, 11)
n = 3, then x = 8 (000,001,010 ...111)
n = j, then x = 2
j
Number of bits in a code word
x: number of elements to be coded binary coded format
x < 2
j
or j > log
2
x
> 3.32 log
10
x
j is the number of bits in a code word.
Example: Coding of alphanumeric
information
Alphanumeric information: 26 alphabetic characters + 10
decimals digits = 36 elements
j > 3.32 log
10
36
j > 5.16 bits
Number of bits required for coding = 6
Only 36 code words are used out of the 64 possible code
words
Some codes for consideration
Binary coded decimal codes
Unit distance codes
Error detection codes
Alphanumeric codes
Simple Scheme
Convert decimal number inputs into binary form
Manipulate these binary numbers
Convert resultant binary numbers back into decimal
numbers
However, it
requires more hardware
slows down the system
Encode each decimal symbol in a unique string of 0s
and 1s
Ten symbols require at least four bits to encode
There are sixteen four-bit groups to select ten groups.
There can be 30 x 10
10
(
16
C
10
.10!) possible codes
Most of these codes will not have any special properties
Example of a BCD code
Natural Binary Coded Decimal code (NBCD)
Consider the number (16.85)
10
(16.85)
10
= (0001 0110 . 1000 0101) NBCD
1 6 8 5
NBCD code is used in calculators
How do we select a coding scheme?
It should have some desirable properties
ease of coding
ease in arithmetic operations
minimum use of hardware
error detection property
ability to prevent wrong output during transitions
Weighted Binary Coding
Decimal number (A)
10
Encoded in the binary form as a3 a2 a1 a0
w3, w2, w1 and w0 are the weights selected for a given
code
(A)
10
= w3a3 + w2a2 + w1a1 +w0a0
The more popularly used codes have these weights as
w3 w2 w1 w0
8 4 2 1
2 4 2 1
8 4 -2 -1
Binary codes for decimal numbers
1 1 1 1 1 1 1 1 1 0 0 1 9
1 0 0 0 1 1 1 0 1 0 0 0 8
1 0 0 1 1 1 0 1 0 1 1 1 7
1 0 1 0 1 1 0 0 0 1 1 0 6
1 0 1 1 1 0 1 1 0 1 0 1 5
0 1 0 0 0 1 0 0 0 1 0 0 4
0 1 0 1 0 0 1 1 0 0 1 1 3
0 1 1 0 0 0 1 0 0 0 1 0 2
0 1 1 1 0 0 0 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0
Weights
8 4 -2 -1
Weights
2 4 2 1
Weight
8 4 2 1
Decimal digit
Binary coded decimal numbers
The unused six combinations are illegal
They may be utilised for error detection purposes.
Choice of weights in a BCD codes
1. Self-complementing codes
2. Reflective codes
Self complementing codes
Logical complement of a coded number is also its
arithmetic complement
Example: 2421 code
Nines complement of (4)
10
= (5)
10
2421 code of (4)
10
= 0100
Complement 0f 0100 = 1011 = 2421 code for (5)
10
= (9 - 4)
10
.
A necessary condition: Sum of its weights should be 9.
Other self complementing codes
Excess-3 code (not weighted)
Add 0011 (3) to all the 8421 coded numbers
Another example is 631-1 weighted code
Examples of self-complementary codes
1111 1100 1100 9
1110 1101 1011 8
1101 1010 1010 7
1100 1000 1001 6
1011 1001 1000 5
0100 0110 0111 4
0011 0111 0110 3
0010 0101 0101 2
0001 0010 0100 1
0000 0011 0011 0
2421
Code
631-1
Code
Excess-3
Code
Decimal
Digit
Reflective code
Imaged about the centre entries with one bit changed
Example
9s complement of a reflected BCD code word is formed
by changing only one of its bits
Examples of reflective BCD codes
0101 1000 9
1011 1001 8
1001 1010 7
1111 1011 6
0001 1100 5
0000 0100 4
1110 0011 3
1000 0010 2
1010 0001 1
0100 0000 0
Code-B Code-A Decimal
Digit
Unit Distance Codes
Adjacent codes differ only in one bit
Gray code is the most popular example
Some of the Gray codes have also the reflective
properties
3-bit and 4-bit Gray codes
1101 - 9
1100 - 8
0100 100 7
0101 101 6
0111 111 5
0110 110 4
0010 010 3
0011 011 2
0001 001 1
0000 000 0
4-bit Gray
Code
3-bit Gray
Code
Decimal
Digit
1000 - 15
1001 - 14
1011 - 13
1010 - 12
1110 - 11
1111 - 10
4-bit Gray
Code
3-bit Gray
Code
Decimal
Digit
More examples of Unit Distance Codes
0010 0100 0001 9
1010 1100 0011 8
1011 1101 0111 7
1111 1111 1111 6
0111 1110 1011 5
0011 0110 1001 4
0001 0010 1000 3
1001 0011 1100 2
1000 0001 0100 1
0000 0000 0000 0
UDC-3 UDC-2 UDC-1 Decimal
Digit
3-bit simple binary coded shaft encoder
000
111
110
101
100 011
010
001
0 0 1
Can lead to errors (001 011 010)
Shaft encoder disk using 3-bit Gray code
000
100
101
111
110 010
011
001
0 0 1
Constructing Gray Code
The bits of Gray code words are numbered from right to
left, from 0 to n-1.
Bit i is 0 if bits i and i+1 of the corresponding binary code
word are the same, else bit i is 1
When i+1 = n, bit n of the binary code word is considered
to be 0
Example: Consider the decimal number 68.
(68)
10
= (1000100)
2
Binary code : 1 0 0 0 1 0 0
Gray code : 1 1 0 0 1 1 0
Convert a Gray coded number to a
straight binary number
Scan the Gray code word from left to right
All the bits of the binary code are the same as those of
the Gray code until the first 1 is encountered, including
the first 1
1s are written until the next 1 is encountered, in which
case a 0 is written.
0s are written until the next 1 is encountered, in which
case a 1 is written.
Examples
Gray code : 1 1 0 1 1 0
Binary code: 1 0 0 1 0 0
Gray code : 1 0 0 0 1 0 1 1
Binary code: 1 1 1 1 0 0 1 0
Alphanumeric Code (ASCII)
DEL o - O ? / US SI 1 1 1 1
~ n N > . RS SO 0 1 1 1
} m ] M = - GS CR 1 0 1 1
| l \ L < , FS FF 0 0 1 1
{ k [ K ; + ESC VT 1 1 0 1
z j Z J : * SUB LF 0 1 0 1
y i Y I 9 ) EM HT 1 0 0 1
x h X H 8 ( CAN BS 0 0 0 1
w g W G 7 , ETB BEL 1 1 1 0
v f V F 6 & SYN ACK 0 1 1 0
u e U E 5 % NAK ENQ 1 0 1 0
t d T D 4 $ DC4 EOT 0 0 1 0
s c S C 3 # DC3 ETX 1 1 0 0
r b R B 2 DC2 STX 0 1 0 0
q a Q A 1 ! DC1 SOH 1 0 0 0
p P @ 0 SP DLE NUL 0 0 0 0
111 110 101 100 011 010 001 000
b7 b6 b5 b1 b2 b3 b4
Other alphanumeric codes
EBCDIC (Extended Binary Coded Decimal Interchange
Code)
12-bit Hollerith code
are in use for some applications
Error Detection and Correction
Error rate cannot be reduced to zero
We need a mechanism of correcting the errors that occur
It is not always possible or may prove to be expensive
It is necessary to know if an error occurred
If an occurrence of error is known, data may be
retransmitted
Data integrity is improved by encoding
Encoding may be done for error correction or merely for
error detection.
Encoding for data integrity
Add a special code bit to a data word
It is called the Parity Bit
Parity bit can be added on an odd or even basis
Parity
Odd Parity
The number of 1s, including the parity bit, should be odd
Example: S in ASCII code is
(S) = (1010011)
ASCII
S, when coded for odd parity, would be shown as
(S) = (11010011)
ASCII with odd parity
Even Parity
The number of 1s, including the parity bit, should be even
When S is encoded for even parity
(S) = (01010011)
ASCII with even parity
Error detection with parity bits
If odd number of 1s occur in the received data word
coded for even parity then an error occurred
Single or odd number bit errors can be detected
Two or even number bit errors will not be detected
Error Correction
Parity bit allows us only to detect the presence of one bit
error in a group of bits
It does not enable us to exactly locate the bit that
changed
Parity bit scheme can be extended to locate the faulty bit
in a block of information
Single error detecting and single error
correcting coding scheme
Column parity bits
Row
Parity
bits
Information bits
The bits are conceptually arranged in a two-dimensional
array, and parity bits are provided to check both the rows
and the columns
Parity-check block codes
Detect and correct more than one-bit errors
These are known as (n, k) codes
They have r (= n - k) parity check bits, formed by linear
operations on the k data bits
R bits are appended to each block of k bits to generate an
n-bit code word
A (15, 11) code has r = 4 parity-check bits for every 11 data
bits
As r increases it should be possible to correct more and
more errors
With r = 1 error correction is not possible
Long codes with a relatively large number of parity-check
bits should provide better performance.
Single-error correcting code
(7, 3) code
Data bits Code words
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 1 1 1 1
0 1 0 0 1 0 0 1 1 0
0 1 1 0 1 1 1 0 0 1
1 0 0 1 0 0 1 1 0 0
1 0 1 1 0 1 0 0 1 1
1 1 0 1 1 0 1 0 1 0
1 1 1 1 1 1 0 1 0 1
Code words differ in at least three positions.
Any one error is correctable since the resultant code word will still be
closer to the correct one
Hamming distance
Difference in the number of positions between any two
code words
For two errors to be correctable, the Hamming distance
d should be at least 5
For t errors correctable, d > 2t+1 or t = [(d -1)/2]
[ ] refers to the integer less than or equal to x.
Codes with different properties
Codes exit for
correcting independently occurring errors
correcting burst errors
providing relatively error-free synchronization of binary
data
etc.
Coding Theory is very important to communication systems.
It is a discipline by itself.
CODES: I nt r oduct i on
When we wish t o send informat ion over long dist ances unambiguously it becomes
necessary t o modify ( encoding) t he informat ion int o some form before sending, and
convert ( decode) at t he receiving end t o get back t he original informat ion. This
process of encoding and decoding is necessary because t he channel t hrough which
t he informat ion is sent may dist ort t he t ransmit t ed informat ion. Much of t he
informat ion is sent as numbers. While t hese numbers are creat ed using simple
weight ed- posit ional numbering syst ems, t hey need t o be encoded before
t ransmission. The modificat ions t o numbers were based on changing t he weight s,
but predominant ly on some form of binary encoding. There are several codes in use
in t he cont ext of present day informat ion t echnology, and more and more new codes
are being generat ed t o meet t he new demands.
Codi ng i s t he pr ocess of al t er i ng t he char act er i st i cs of i nf or mat i on t o mak e
i t mor e sui t abl e f or i nt ended appl i cat i on
By assigning each it em of informat ion a unique combinat ion of 1s and 0s we
t ransform some given informat ion int o binary coded form. The bit combinat ions are
referred t o as words or code words . I n t he field of digit al syst ems and comput ers
different bit combinat ions have different designat ions.
Bit - a binary digit 0 or 1
Nibble - a group of four bit s
Byt e - a group of eight bit s
Word - a group of sixt een bit s;
a word has t wo byt es or four nibbles
Somet imes word is used t o designat e a larger group of bit s also, for example 32 bit
or 64 bit words.
We need and use coding of informat ion for a variet y of reasons
t o increase efficiency of t ransmission,
t o make it error free,
t o enable us t o correct it if errors occurred,
t o inform t he sender if an error occurred in t he received informat ion et c.
for securit y reasons t o limit t he accessibilit y of informat ion
t o st andardise a universal code t hat can be used by all
Coding schemes have t o be designed t o suit t he securit y requirement s and t he
complexit y of t he medium over which informat ion is t ransmit t ed.
Decodi ng i s t he pr ocess of r econst r uct i ng sour ce i nf or mat i on f r om t he
encoded i nf or mat i on. Decoding process can be more complex t han coding if we
do not have prior knowledge of coding schemes.
I n view of t he modern day requirement s of efficient , error free and secure
informat ion t ransmission coding t heory is an ext remely import ant subj ect . However,
at t his st age of learning digit al syst ems we confine ourselves t o familiarising wit h a
few commonly used codes and t heir propert ies.
We will be mainly concerned wit h binary codes. I n binary coding we use binary digit s
or bit s ( 0 and 1) t o code t he element s of an informat ion set . Let n be t he number of
bit s in t he code word and x be t he number of unique words.
I f n = 1, t hen x = 2 ( 0, 1)
n = 2, t hen x = 4 ( 00, 01, 10, 11)
n = 3, t hen x = 8 ( 000, 001, 010 . . . 111)
.
n = j , t hen x = 2
j

From t his we can conclude t hat if we are given element s of informat ion t o code int o
binary coded format ,
x < 2
j

or j > log
2
x
> 3. 32 log
10
x
where j is t he number of bit s in a code word.
For example, if we want t o code alphanumeric informat ion ( 26 alphabet ic charact ers
+ 10 decimals digit s = 36 element s of informat ion) , we require
j > 3. 32 log
10
36
j > 5. 16 bit s
Since bit s are not defined as fract ional part s, we t ake j = 6. I n ot her words a
minimum six- bit code would be required t o code 36 alphanumeric element s of
informat ion. However, wit h a six- bit code only 36 code words are used out of t he 64
code words possible.
I n t his Learning Unit we consider a few commonly used codes including
1. Binary coded decimal codes
2. Unit dist ance codes
3. Error det ect ion codes
4. Alphanumeric codes

Bi nar y Coded Deci mal Codes
The main mot ivat ion for binary number syst em is t hat t here are only t wo element s in
t he binary set , namely 0 and 1. While it is advant ageous t o perform all
comput at ions on hardware in binary forms, human beings st ill prefer t o work wit h
decimal numbers. Any elect ronic syst em should t hen be able t o accept decimal
numbers, and make it s out put available in t he decimal form.
One met hod, t herefore, would be t o
convert decimal number input s int o binary form
manipulat e t hese binary numbers as per t he required funct ions, and
convert t he result ant binary numbers int o t he decimal form
However, t his kind of conversion requires more hardware, and in some cases
considerably slows down t he syst em. Fast er syst ems can afford t he addit ional
circuit ry, but t he delays associat ed wit h t he conversions would not be accept able. I n
case of smaller syst ems, t he speed may not be t he main crit erion, but t he addit ional
circuit ry may make t he syst em more expensive.
We can solve t his problem by encoding decimal numbers as binary st rings, and use
t hem for subsequent manipulat ions.
There are t en different symbols in t he decimal number syst em: 0, 1, 2, . . . , 9. As
t here are t en symbols we require at least four bit s t o represent t hem in t he binary
form. Such a represent at ion of decimal numbers is called bi nar y codi ng of deci mal
number s.
As four bit s are required t o encode one decimal digit , t here are sixt een four- bit
groups t o select t en groups. This would lead t o nearly 30 x 10
10
(
16
C
10
. 10! ) possible
codes. However, most of t hem will not have any special propert ies t hat would be
useful in hardware design. We wish t o choose codes t hat have some desirable
propert ies like
ease of coding
ease in arit hmet ic operat ions
minimum use of hardware
error det ect ion propert y
abilit y t o prevent wrong out put during t ransit ions
I n a w ei ght ed code t he decimal value of a code is t he algebraic sum of t he weight s
of 1s appearing in t he number. Let ( A)
10
be a decimal number encoded in t he binary
form as a
3
a
2
a
1
a
0
. Then
( A)
10
= w
3
a
3
+ w
2
a
2
+ w
1
a
1
+ w
0
a
0

where w
3
, w
2
, w
1
and w
0
are t he weight s select ed for a given code, and a
3
, a
2
, a
1
and
a
0
are eit her 0s or 1s. The more popularly used codes have t he weight s as
w
3
w
2
w
1
w
0

8 4 2 1
2 4 2 1
8 4 - 2 - 1
The decimal numbers in t hese t hree codes are
Decimal
digit
Weight s
8 4 2 1
Weight s
2 4 2 1
Weight s
8 4 - 2 - 1
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 1 1 1
2 0 0 1 0 0 0 1 0 0 1 1 0
3 0 0 1 1 0 0 1 1 0 1 0 1
4 0 1 0 0 0 1 0 0 0 1 0 0
5 0 1 0 1 1 0 1 1 1 0 1 1
6 0 1 1 0 1 1 0 0 1 0 1 0
7 0 1 1 1 1 1 0 1 1 0 0 1
8 1 0 0 0 1 1 1 0 1 0 0 0
9 1 0 0 1 1 1 1 1 1 1 1 1

I n all t he cases only t en combinat ions are ut ilized t o represent t he decimal digit s.
The remaining six combinat ions are illegal. However, t hey may be ut ilized for error
det ect ion purposes.
Consider, for example, t he represent at ion of t he decimal number 16.85 in Nat ural
Binary Coded Decimal code ( NBCD)
( 16. 85)
10
= ( 0001 0110 . 1000 0101)
NBCD

1 6 8 5
There are many possible weight s t o writ e a number in BCD code. Some codes have
desirable propert ies, which make t hem suit able for specific applicat ions. Two such
desirable propert ies are:
1. Self- complement ing codes
2. Reflect ive codes
When we perform arit hmet ic operat ions, it is oft en required t o t ake t he
complement of a given number. I f t he logical complement of a coded number is
also it s arit hmet ic complement , it will be convenient from hardware point of view. I n
a sel f - compl ement i ng coded decimal number, ( A)
10
, if t he individual bit s of a
number are complement ed it will result in ( 9 - A)
10
.
Ex ampl e: Consider t he 2421 code.
The 2421 code of ( 4)
10
is 0100.
I t s complement is 1011 which is 2421 code for ( 5)
10
= ( 9 - 4)
10
.
Therefore, 2421 code may be considered as a self- complement ing code. A necessary
condit ion for a self- compliment ing code is t hat t he sum of it s weight s should be 9.
A self- complement ing code, which is not weight ed, is excess- 3 code. I t is derived
from 8421 code by adding 0011 t o all t he 8421 coded numbers.
Anot her self- complement ing code is 631- 1 weight ed code.
Three self- complement ing codes are
Decimal
Digit
Excess- 3
Code
631- 1
Code
2421
Code
0 0011 0011 0000
1 0100 0010 0001
2 0101 0101 0010
3 0110 0111 0011
4 0111 0110 0100
5 1000 1001 1011
6 1001 1000 1100
7 1010 1010 1101
8 1011 1101 1110
9 1100 1100 1111

A r ef l ect i ve code is charact erized by t he fact t hat it is imaged about t he cent re
ent ries wit h one bit changed. For example, t he 9s complement of a reflect ed BCD
code word is formed by changing only one it s bit s. Two such examples of reflect ive
BCD codes are

Decimal Code- A Code- B
0 0000 0100
1 0001 1010
2 0010 1000
3 0011 1110
4 0100 0000
5 1100 0001
6 1011 1111
7 1010 1001
8 1001 1011
9 1000 0101

The BCD codes are widely used and t he reader should become familiar wit h reasons
for using t hem and t heir applicat ion. The most common applicat ion of NBCD codes is
in t he calculat or.

Uni t Di st ance Codes
There are many applicat ions in which it is desirable t o have a code in which t he
adj acent codes differ only in one bit . Such codes are called Unit dist ance Codes.
Gray code is t he most popular example of unit dist ance code. The 3- bit and 4- bit
Gray codes are
Decimal 3- bit Gray 4- bit Gray
0 000 0000
1 001 0001
2 011 0011
3 010 0010
4 110 0110
5 111 0111
6 101 0101
7 100 0100
8 - 1100
9 - 1101
10 - 1111
11 - 1110
12 - 1010
13 - 1011
14 - 1001
15 - 1000

These Gray codes list ed here have also t he reflect ive propert ies. Some addit ional
examples of unit dist ance codes are
Decimal
Digit
UDC- 1 UDC- 2

UDC- 3

0 0000 0000 0000
1 0100 0001 1000
2 1100 0011 1001
3 1000 0010 0001
4 1001 0110 0011
5 1011 1110 0111
6 1111 1111 1111
7 0111 1101 1011
8 0011 1100 1010
9 0001 0100 0010

The most popular use of Gray codes is in t he posit ion sensing t ransducer known as
shaft encoder. A shaft encoder consist s of a disk in which concent ric circles have
alt ernat e sect ors wit h reflect ive surfaces while t he ot her sect ors have non- reflect ive
surfaces. The posit ion is sensed by t he reflect ed light from a light emit t ing diode.
However, t here is choice in arranging t he reflect ive and non- reflect ive sect ors. A 3-
bit binary coded disk will be as shown in t he figure 1.

FI G. 1: 3- bit binary coded shaft encoder
From t his figure we see t hat st raight binary code can lead t o errors because of
mechanical imperfect ions. When t he code is t ransit ing from 001 t o 010, a slight
misalignment can cause a t ransient code of 011 t o appear. The elect ronic circuit ry
associat ed wit h t he encoder will receive 001 - - > 011 - > 010. I f t he disk is pat t erned
t o give Gray code out put , t he possibilit ies of wrong t ransient codes will not arise.
This is because t he adj acent codes will differ in only one bit . For example t he
adj acent code for 001 is 011. Even if t here is a mechanical imperfect ion, t he
t ransient code will be eit her 001 or 011. The shaft encoder using 3- bit Gray code is
shown in t he figure 2.

000 100
101
111
110 010
011
001
0 0 1

FI G. 2: Shaft encoder disk using a 3- bit Gray code
There are t wo convenient met hods t o const ruct Gray code wit h any number of
desired bit s. The first met hod is based on t he fact t hat Gray code is also a reflect ive
code. The following rule may be used t o const ruct Gray code:
A one- bit Gray code had code words, 0 and 1
000 111
110
101
100 011
010
001
0 0 1
The first 2
n
code words of an ( n+ 1) - bit Gray code equal t he code words of an
n- bit Gray code, writ t en in order wit h a leading 0 appended.
The last 2
n
code words of a ( n+ 1) - bit Gray code equal t he code words of an
n- bit Gray code, writ t en in reverse order wit h a leading 1 appended.
However, t his met hod requires Gray codes wit h all bit lengt hs less t han n also be
generat ed as a part of generat ing n- bit Gray code. The second met hod allows us t o
derive an n- bit Gray code word direct ly from t he corresponding n- bit binary code
word:
The bit s of an n- bit binary code or Gray code words are numbered from right
t o left , from 0 t o n- 1.
Bit i of a Gray- code word is 0 if bit s i and i+ 1 of t he corresponding binary
code word are t he same, else bit i is 1. When i+ 1 = n, bit n of t he binary
code word is considered t o be 0.
Ex ampl e: Consider t he decimal number 68.
( 68)
10
= ( 1000100)
2

Binary code: 1 0 0 0 1 0 0
Gray code : 1 1 0 0 1 1 0
The following rules can be followed t o convert a Gray coded number t o a st raight
binary number:
Scan t he Gray code word from left t o right . All t he bit s of t he binary code are
t he same as t hose of t he Gray code unt il t he first 1 is encount ered, including
t he first 1.
1s are writ t en unt il t he next 1 is encount ered, in which case a 0 is
writ t en.
0s are writ t en unt il t he next 1 is encount ered, in which case a 1 is writ t en.
Consider t he following examples of Gray code numbers convert ed t o binary numbers
Gray code : 1 1 0 1 1 0 1 0 0 0 1 0 1 1
Binary code: 1 0 0 1 0 0 1 1 1 1 0 0 1 0

Al phanumer i c Codes
When informat ion t o be encoded includes ent it ies ot her t han numerical values, an
expanded code is required. For example, alphabet ic charact ers ( A, B, . . . . Z) and
special operat ion symbols like + , - , / , * , ( , ) and ot her special symbols are used in
digit al syst ems. Codes t hat include alphabet ic charact ers are commonly referred t o
as Alphanumeric Codes. However, we require adequat e number of bit s t o encode all
t he charact ers. As t here was a need for alphanumeric codes in a wide variet y of
applicat ions in t he early era of comput ers, like t elet ype, punched t ape and punched
cards, t here has always been a need for evolving a st andard for t hese codes.
Alphanumeric keyboard has become ubiquit ous wit h t he popularizat ion of personal
comput ers and not ebook comput ers. These keyboards use ASCI I ( American
St andard Code for I nformat ion I nt erchange) code
b4 b3 b2 b1 b7 b6 b5
000 001 010 011 100 101 110 111
0 0 0 0 NUL DLE SP 0 @ P p
0 0 0 1 SOH DC1 ! 1 A Q a q
0 0 1 0 STX DC2 2 B R b r
0 0 1 1 ETX DC3 # 3 C S c s
0 1 0 0 EOT DC4 $ 4 D T d t
0 1 0 1 ENQ NAK % 5 E U e u
0 1 1 0 ACK SYN & 6 F V f v
0 1 1 1 BEL ETB , 7 G W g w
1 0 0 0 BS CAN ( 8 H X h x
1 0 0 1 HT EM ) 9 I Y i y
1 0 1 0 LF SUB * : J Z j z
1 0 1 1 VT ESC + ; K [ k {
1 1 0 0 FF FS , < L \ l |
1 1 0 1 CR GS - = M ] m }
1 1 1 0 SO RS . > N n ~
1 1 1 1 SI US / ? O - o DEL

Alphanumeric codes like EBCDI C ( Ext ended Binary Coded Decimal I nt erchange Code)
and 12- bit Hollerit h code are in use for some applicat ions. However, ASCI I code is
now t he st andard code for most dat a communicat ion net works. Therefore, t he
reader is urged t o become familiar wit h t he ASCI I code.

Er r or Det ect i on and Cor r ect i ng Codes
When dat a is t ransmit t ed in digit al form from one place t o anot her t hrough a
t ransmission channel/ medium, some dat a bit s may be lost or modified. This loss of
dat a int egrit y occurs due t o a variet y of elect rical phenomena in t he t ransmission
channel. As t here are needs t o t ransmit millions of bit s per second, t he dat a
int egrit y should be very high. The error rat e cannot be reduced t o zero. Then we
would like t o ideally have a mechanism of correct ing t he errors t hat occur. I f t his is
not possible or proves t o be expensive, we would like t o know if an error occurred.
I f an occurrence of error is known, appropriat e act ion, like ret ransmit t ing t he dat a,
can be t aken. One of t he met hods of improving dat a int egrit y is t o encode t he dat a
in a suit able manner. This encoding may be done for error correct ion or merely for
error det ect ion.
A simple process of adding a special code bit t o a dat a word can improve it s
int egrit y. This ext ra bit will allow det ect ion of a single error in a given code word in
which it is used, and is called t he Parit y Bit . This parit y bit can be added on an odd
or even basis. The odd or even designat ion of a code word may be det ermined by
act ual number of 1s in t he dat a ( including t he added parit y bit ) t o which t he parit y
bit is added. For example, t he S in ASCI I code is
( S) = ( 1010011)
ASCI I

S, when coded for odd parit y, would be shown as
( S) = ( 11010011)
ASCI I wit h odd parit y

I n t his encoded S t he number of 1s is five, which is odd.
When S is encoded for even parit y
( S) = ( 01010011)
ASCI I

wit h even parit y
.
I n t his case t he coded word has even number ( four) of ones.
Thus t he parit y encoding scheme is a simple one and requires only one ext ra bit . I f
t he syst em is using even parit y and we find odd number of ones in t he received dat a
word we know t hat an error has occurred. However, t his scheme is meaningful only
for single errors. I f t wo bit s in a dat a word were received incorrect ly t he parit y bit
scheme will not det ect t he fault s. Then t he quest ion arises as t o t he level of
improvement in t he dat a int egrit y if occurrence of only one bit error is det ect able.
The improvement in t he reliabilit y can be mat hemat ically det ermined.

Adding a parit y bit allows us only t o det ect t he presence of one bit error in a group of
bit s. But it does not enable us t o exact ly locat e t he bit t hat changed. Therefore,
addit ion of one parit y bit may be called an error det ect ing coding scheme. I n a
digit al syst em det ect ion of error alone is not sufficient . I t has t o be correct ed as
well. Parit y bit scheme can be ext ended t o locat e t he fault y bit in a block of
informat ion. The informat ion bit s are concept ually arranged in a t wo- dimensional
array, and parit y bit s are provided t o check bot h t he rows and t he columns.
I f we can ident ify t he code word t hat has an error wit h t he parit y bit , and t he column
in which t hat error occurs by a way of change in t he column parit y bit , we can bot h
det ect and correct t he wrong bit of informat ion. Hence such a scheme is single error
det ect ing and single error correct ing coding scheme.
This met hod of using parit y bit s can be generalized for det ect ing and correct ing more
t han one- bit error. Such codes are called parit y- check block codes. I n t his class
known as ( n, k) codes, r ( = n- k) parit y check bit s, formed by linear operat ions on
t he k dat a bit s, are appended t o each block of k bit s t o generat e an n- bit code word.
An encoder out put s a unique n- bit code word for each of t he 2
k
possible input k- bit
blocks. For example a ( 15, 11) code has r = 4 parit y- check bit s for every 11 dat a
bit s. As r increases it should be possible t o correct more and more errors.
Wit h r = 1 error correct ion is not possible, as such a code will only det ect an odd
number of errors.
I t can also be est ablished t hat as k increases t he overall probabilit y of error should
also decrease. Long codes wit h a relat ively large number of parit y- check bit s should
t hus provide bet t er performance. Consider t he case of ( 7, 3) code
Dat a bit s Code words
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 1 1 1 1
0 1 0 0 1 0 0 1 1 0
0 1 1 0 1 1 1 0 0 1
1 0 0 1 0 0 1 1 0 0
1 0 1 1 0 1 0 0 1 1
1 1 0 1 1 0 1 0 1 0
1 1 1 1 1 1 0 1 0 1

A close look at t hese indicat es t hat t hey differ in at least t hree posit ions. Any one
error should t hen be correct able since t he result ant code word will st ill be closer t o
t he correct one, in t he sense of t he number of bit posit ions in which t hey agree, t han
t o any ot her. This is an example of single- error- correct ing- code. The difference in
t he number of posit ions bet ween any t wo code words is called t he Hamming
dist ance, named aft er R. W. Hamming who, in 1950, described a general met hod for
const ruct ing codes wit h a minimum dist ance of 3. The Hamming dist ance plays a
key role in assessing t he error- correct ing capabilit y of codes. For t wo errors t o be
correct able, t he Hamming dist ance d should be at least 5. I n general, for t errors t o
be correct able, d > 2t + 1 or t = [ ( d- 1) / 2] , where t he [ x] not at ion refers t o t he
int eger less t han or equal t o x.
I nnumerable variet ies of codes exist , wit h different propert ies. There are various
t ypes of codes for correct ing independent ly occurring errors, for correct ing burst
errors, for providing relat ively error- free synchronizat ion of binary dat a et c. The
t heory of t hese codes, met hods of generat ing t he codes and decoding t he coded
dat a, is a very import ant subj ect of communicat ion syst ems, and need t o be st udied
as a separat e discipline.

Pr obl ems
M1L2: Codes
1. Writ e t he following decimal number in Excess- 3, 2421, 84- 2- 2 BCD codes:
( a) 563 ( b) 678 ( c) 1465

2. What is t he use of self- complement ing propert y? Demonst rat e 631- 1 BCD code is
self- complement ary.
3. Develop t wo different 4- bit unit dist ance codes.
4. Prove t hat Gray code is bot h a reflect ive and unit dist ance code?
5. Det ermine t he Gray code for ( a) 37
10
and ( b) 97
10
.
6. Writ e your address in ASCI I code.
7. Writ e 8- bit ASCI I code sequence of t he name of your t own/ cit y wit h even parit y.
8. ( a) Wr it e t he following st at ement s in ASCI I
A = 4. 5 x B
X = 75/ Y
( b) At t ach an even parit y bit t o each code word of t he ASCI I st rings writ t en for t he
above st at ement s
9. Find and correct t he error in t he following code sequence
0 1 0 1 0
0 1 1 0 0
1 1 0 1 1
1 0 1 1 0
1 0 0 0 1
0 0 0 1 1
1 1 0 0 0
0 1 0 0 1
0 1 0 1 0 - - - Parit y word
| __________ Parit y bit

Digital Electronics
Module 2: Boolean Algebra and
Boolean Operators: Boolean Algebra
N.J. Rao
Switching Signals
We encounter situations where the choice is binary
Move -Stop
On - Off
Yes - No
An intended action takes place or does not take place
Signals with two possible states are called switching
signals
We need to work with a large number of such signals
There is a need for formal methods of handling such
signals
Examples of switching signals
A control circuit for an electric bulb
Four switches control the operation of the bulb
`the bulb is switched on if the switches S1 and S2 are
closed, and S3 or S4 is also closed, otherwise the bulb will
not be switched on'
Relay operations in telephone exchanges is another example
George Boole
English mathematician (1854)
Wrote An Investigation of the Laws of Thought
Examined the truth or falsehood of language statements
Used special algebra of logic - Boole's Algebra (Boolean
Algebra)
assigned a value 1 to statements that are completely correct
assigned a value 0 to statements that are completely false
Statements are referred to digital variables
We consider logical or digital variables to be synonymous
Claude Shannon
Masters Thesis at Massachusetts Institute of Technology
in 1938
A Symbolic Analysis of Relay and Switching Circuits
He applied Boolean algebra to the analysis and design
of electrical switching circuits
Realisation of switching circuits
Bipolar and MOS transistors are used as switches in
building integrated circuits
Need to understand the electrical aspects of these circuits
Learning Objectives
To know the basic axioms of Boolean algebra
To simplify logic functions (Boolean functions)
using the basic properties of Boolean Algebra
Boolean Algebra
A Boolean algebra consists of
a finite set BS
subject to equivalence relation "="
one unary operator not (symbolised by an over bar)
two binary operators "+" and "."
such that for every element x and y BS, the operations
(not x), x + y and x . y are uniquely defined
x
Boolean Algebra (2)
The unary operator not is defined by the relation
The not operator is also called the complement
is the complement of x
x
1 0 ; 0 1
Binary operator and
The and operator is defined by
0 . 0 = 0
0 . 1 = 0
1 . 0 = 0
1 . 1 = 1
Binary operator or
The or operator is defined by
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
Huntington's (1909) postulates
P1. The operations are closed
For all x and y BS,
x + y BS
x . y BS
P2. For each operation there exists an identity element.
There exists an element 0 BS such that for all
x BS, x + 0 = x
There exists an element 1 BS such that for all
x BS, x . 1 = x
Huntington's postulates (2)
P3. The operations are commutative
For all x and y BS,
x + y = y + x
x . y = y . x
P4. The operations are distributive
For all x, y and z BS,
x + (y . z) = (x + y) . (x + z)
x . (y + z) = (x . y) + (x . z)
Huntington's postulates (3)
P5. For every element x BS there exists an element
BS (called the complement of x) such that
x + = 1
x . = 0
P6. There exist at least two elements x and y BS such
that x y.
x
x
x

Useful properties
duality of law the applying by proved be can b Part
) 5b postulate ( 0
) a 2 (postulate x . x
4b) postulate ( ) x 0 ( . x
5b) (postulate ) x . (x 0) . (x
2a) (postulate 0 ) 0 . x ( 0 . x : Proof
1 1 x b.
0 0 . x a.
x all For
1 and 0 of law Special : 1 Property

BS
Useful properties (2)
Property 2:
The element 0 is unique.
The element 1 is unique.
Proof for Part b by contradiction:
Assume that there are two 1s denoted 1
1
and 1
2
.
x . 1
1
= x and y . 1
2
= y (Postulate 2b)
x . 1
1
= x and 1
2
. y = y (Postulate 3b)
Letting x = 1
2
and y = 1
1
1
2
. 1
1
= 1
2
and 1
2
. 1
1
= 1
1
1
1
= 1
2
(transitivity property)
which becomes a contradiction of initial assumption
Property a can be established by applying the principle of
duality.
duality of principle of n applicatio by the valid is b Part
1 0
a) postulate5 ( 1 0 0
0 0 0
2a) (postulate x 0 x : Proof
0 1 is 1 of complement The b.
1 0 is 0 of complement The a.
3 operty Pr

duality) (by x x . x
2a) (postulate x
5b) (postulate 0 x
) 4a (postulate ) x . (x x
) 5a (postulate ) x (x . x) x (
2b) (postulate 1 . x) (x x x : Proof
x x . x b.
x x x a.
BS x all For
Property 4: Idempotency law

s expression logical g simplifyin in Useful
duality) (by x ) y (x . y) (x
2b) (postulate x
5a) (postulate 1 . x
4b) (postulate ) y (y . x y . x y . x : Proof
x ) y (x . y) (x b.
x y . x y . x a.
BS y and x all For
law Adjacency : 5 operty Pr

Property 6: First law of absorption.
For all x and y BS,
x + (x . y) = x
x . (x + y) = x
Proof : x . (x + y) = (x + 0) . (x + y) (postulate 2a)
= x + (0 . y) (postulate 4a)
= x + 0 (property 2.1a)
= x (postulate 2a)
x + (x . y) = x (by duality)
duality) (by y . x y) x ( . x
2b) (postulate y x
5a) (postulate y) (x . 1
4a) (postulate y) (x . ) x (x y) . x ( x : Proof
y . x y) x ( . x b.
y x y) . x ( x a.
BS y and x all For
absorption of law Second : 7 operty Pr

duality) (by z) x ( . y) (x z) (y . z) x ( . y) (x
2b) (postulate z . x y . x
b) 2.1 (postulate 1 z. . x 1 y. . x
4b) (postulate y) (1 . z . x z) (1 . y . x
4b) (postulate z . y . x z . x z y. . x y . x
5a) (postulate z . y ). x (x z . x y . x
2b) (postulate z . y 1. z . x y . x
z y. z . x y . x : Proof
z) x ( . y) (x z) (y . z) . x ( . y) (x b.
z . x y . x z . y z . x y . x a.
BS z y, x, all For
law Consensus : 8 Property


For all x and y BS,
If (a) x + y = y and (b) x . y = y, then x = y
Proof: Substituting (a) into the left-hand side of (b), we have
x . (x + y) = y
However by the first law of absorption
x . (x + y) = x (property 6)
Therefore, by transitivity x = y
5a) (postulate x . x 1 . x) x (
4a) (postulate ) x x ( . x) x (
5b) (postulate ) x . (x x
2a) (postulate 0 x x
x x . x and x x) x (
is, that holds, 2.9) (property identity of
law that the show to need We : Proof
x x BS, x all For
involution of law The : 10 Property

Useful properties (10) (contd.)
x x have we identity, of law by the Therefore,
2a) (postulate x . x
5b) (postualte 0 x . x
5a) (postulate x . x x . x
2b) (postulate ) x (x . x
1 . x x Also

duality) (by y x .y x
y x of complement the is ) y . x ( Therefore,
2.16) (property 1
5a) (postulate 1 x
2.7a) (property y y x
3a) (postulate y ) y . x (x ) y . x ( y) (x
2a) (postulate 0 0 0
4b) (postulate ) y . x . (y ) y . x . (x ) y . x ( . y) (x : Proof
y x y . x b.
y . x y x a.
BS y x, all For
Law s DeMorgan' : 11 Property

DeMorgan's law
bridges the AND and OR operations
establishes a method for converting one form of a
Boolean function into another
allows the formation of complements of expressions with
more than one variable
can be extended to expressions of any number of
variables through substitution
Example of DeMorgans Law
z . y . x
law) s DeMorgan' (by z y . x
on) substituti (by z y x w x Therefore
law) s DeMorgan' (by w . x w x Since
w x z y then x w, z y Let
z . y . x z y x

Boolean Operators
BS = {0, 1}
Resulting Boolean algebra is more suited to working with
switching circuits
Variables associated with electronic switching circuits
take only one of the two possible values.
The operations "+" and "." also need to be given
appropriate meaning
Binary Variables
Definition: A binary variable is one that can assume one
of the two values 0 and 1.
These two values are meant to express two exactly
opposite states.
If A 0, then A = 1.
If A 1, then A = 0
Examples:
if switch A is not open then it is closed
if switch A is not closed then it is open
Statement like
"0 is less than 1" or " 1 is greater than 0 are invalid in
Boolean algebra

NOT Operator
The Boolean operator NOT, also known as complement
operator
NOT operator is represented by " " (overbar) on the
variable, or "
/
" (a superscript slash) after the variable
Definition: Not operator is defined by
A A
/
0 1
1 0
"
/
" symbol is preferred for convenience in typing and
writing programs
Circuit representation:
OR Operator
Definition: The Boolean operator "+" known as OR operator
is defined by
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
The circuit symbol for logical OR operation
And Operator
Definition: The Boolean operator "." known as AND
operator is defined by
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
Circuit symbol for the logical AND operation
Boolean Operators and Switching
Circuits
Open Closed
Closed Open
A A
1 1 1 1
0 1 0 1
0 1 1 0
0 0 0 0
A.B A+B B A
Additional Boolean Operators
NAND,
NOR,
Exclusive-OR (Ex-OR)
Exclusive-NOR (Ex-NOR)
Definitions
1 0 0 0 1 1
0 1 0 1 0 1
0 1 0 1 1 0
1 0 1 1 0 0
A B A B (A+B)
/
(AB)
/
B A

Additional Operations (2)
NAND operation is just the complement of AND operation
NOR operation is the complement of OR operation
Exclusive-NOR is the complement of Exclusive-OR
operation
Circuit Symbols

Functionally complete sets of
operations
OR, AND and NOT
OR and NOT
AND and NOT
NAND
NOR
Completeness of AND, OR and NOT
A
B
NOR
A
B
NAND
A
B
EX-OR
A
B
EX-NOR
Completeness of OR and NOT
operations
Completeness of AND and NOT
A
B
OR
A
B
NOR
A
B
NAND
A
B
EX-NOR
A
B
EX-OR
Completeness of NAND
Completeness of NOR
A
B
OR
A
B
AND
A
NOT
A
B
NAND
A
B
EX-NOR
A
B
EX-OR

WHAT I S BOOLEAN ALGEBRA?
Consider t he elect rical circuit t hat cont rols t he light ing of a bulb.

Four swit ches cont rol t he operat ion of t he bulb. The manner in which t he operat ion of
t he bulb is cont rolled can be st at ed as
The bul b sw i t ches on i f t he sw i t ches S1 and S2 ar e cl osed, and S3 or S4 i s al so
cl osed, ot her w i se t he bul b w i l l not sw i t ch on
From t his st at ement one can make t he following observat ions:
Any swit ch has t wo st at es: closed or open
The bulb is swit ched on only when t he swit ches are in some well defined
combinat ion of st at es.
The possible combinat ions are expressed t hrough t wo t ypes of relat ionships:
and and or .
The t wo possible combinat ions are
S1 and S2 and S3 are closed
S1 and S2 and S4 are closed
There are many sit uat ions of engineering int erest where t he variables t ake only a small
number of possible values.
Some examples:
Relay net work used in t elephone exchanges of earlier era
Test ing t hr ough mult iple choice quest ions
Mechanical display boards in airport s and railway st at ions
Choices available at road j unct ions.
Can you ident ify a sit uat ion of significance where t he variables can t ake only a small
number of dist inct ly defined st at es?
How do we implement funct ions similar t o t he example shown above? We need devices
t hat have finit e number st at es. I t seems t o be easy t o creat e devices wit h t wo well
defined st at es. I t is more difficult and more expensive t o creat e devices wit h more t han
t wo st at es.
Let us consider devices wit h t wo well defined st at es. We should also have t he abilit y t o
swit ch t he st at e of t he device from one st at e t o t he ot her. We call devices having t wo
well defined st at es as t wo- valued swit ching devices .
Some examples of devices wit h t wo st at es
A bipolar t ransist or in eit her fully- off or fully- on st at e
A MOS t ransist or in eit her fully off or fully on st at e
Simple relays
Elect romechanical swit ch
I f we learn t o work wit h t wo- valued variables, we acquire t he abilit y t o implement
funct ions of such variables using t wo- st at e devices. We call t hem binary variables .
Very complex funct ions can be represent ed using several binary variables. As we can
also build syst ems using millions of elect ronic t wo- st at e devices at very low cost s, t he
mat hemat ics of binary variables becomes very import ant .
An English mat hemat ician, George Boole, int roduced t he idea of examining t he t rut h or
falsehood of language st at ement s t hrough a special algebra of logic. His work was
published in 1854, in a book ent it led An I nvest igat ion of t he Laws of Thought . Boole' s
algebra was applied t o st at ement s t hat are eit her complet ely correct or complet ely false.
A value 1 is assigned t o t hose st at ement s t hat are complet ely correct and a value 0 is
assigned t o st at ement s t hat are complet ely false. As t hese st at ement s are given
numerical values 1 or 0, t hey are referred t o as digit al variables.
I n our st udy of digit al syst ems, we use t he words swit ching variables, logical variables,
and digit al variables int erchangeably.
Boole' s algebra is referred t o as Boolean algebra. Originally Boolean algebra was mainly
applied t o est ablish t he v al i di t y or f al sehood of logical st at ement s.
I n 1938, Claude Shannon of Depart ment of Elect rical Engineering at Massachuset t s
I nst it ut e of Technology in ( his mast er' s t hesis) provided t he first applicat ions of t he
principles of Boolean algebra t o t he design of elect rical swit ching circuit s. The t it le of
t he paper, which was an abst ract of his t hesis, is A Symbolic Analysis of Relay and
Swit ching Circuit s . Shannon est ablished Boole' s algebra t o swit ching circuit s is what
ordinary algebra is t o analogue circuit s.
Logic designers of t oday use Boolean algebra t o funct ionally design a large variet y of
elect ronic equipment such as
hand- held calculat ors,
t raffic light cont rollers,

personal comput ers,
super comput ers,
communicat ion syst ems
aerospace equipment
et c.
We next explore Boolean algebra at t he axiomat ic level. However, we do not worry about
t he devices t hat would be used t o implement t hem and t heir limit at ions.

Bool ean Al gebr a and Hunt i ngt on Post ul at es
Any branch of mat hemat ics st art s wit h a set of self- evident st at ement s known as
post ulat es, axioms or maxims. These are st at ed wit hout any proof.
Boolean algebra is a specific inst ance of Algebra of Proposit ional Logic.
E. V. Hunt ingt on present ed basic post ulat es of Boolean Algebra in 1904 in his paper
Set s of I ndependent Post ulat es for t he Algebra of Logic . He defined a mult i- valued
Boolean algebra on a set of finit e number of element s.
I n Boolean algebra as applied t o t he swit ching circuit s, all variables and relat ions are
t wo- valued. The t wo values are normally chosen as 0 and 1, wit h 0 represent ing
false and 1 represent ing t rue. I f x is a Boolean variable, t hen
x = 1 means x is t rue
x = 0 means x is false
When we apply Boolean algebra t o digit al circuit s we will find t hat t he qualificat ions
assert ed and not - assert ed are bet t er names t han t rue and false . That is when
x = 1 we say x is assert ed, and when x = 0 we say x is not - assert ed.
You are expect ed t o be familiar wit h
Concept of a set
Meaning of equivalence relat ion
The principle of subst it ut ion
Def i ni t i on: A Boolean algebra consist s of a finit e set of element s BS subj ect t o
Equivalence relat ion "= ",
One unary operat or not ( symbolised by an over bar) ,
Two binary operat ors ". " and "+ ",
For every element x and y BS t he operat ions x ( not x) , x. y and x + y are
uniquely defined.
The unary operat or not is defined by t he relat ion
1= 0; 0 = 1
The not operat or is also called t he complement , and consequent ly x is t he
complement of x.
The binary operat or and is symbolized by a dot . The and operat or is defined by t he
relat ions
0 . 0 = 0
0 . 1 = 0
1 . 0 = 0
1 . 1 = 1
The binary operat or or is represent ed by a plus ( + ) sign. The or operat or is
defined by t he relat ions
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
Hunt ingt on' s post ulat es apply t o t he Boolean operat ions
P1. The oper at i ons ar e cl osed.
For all x and y BS,
a. x + y BS
b. x . y BS
P2. For each oper at i on t her e ex i st s an i dent i t y el ement .
a. There exist s an element 0 BS such t hat for all x BS, x + 0 = x
b. There exist s an element 1 BS such t hat for all x BS, x . 1 = x
P3. The oper at i ons ar e commut at i ve.
For all x and y BS,
a. x + y = y + x
b. x . y = y . x
P4. The oper at i ons ar e di st r i but i v e.
a. x + ( y . z) = ( x + y) . ( x + z)
b. x . ( y + z) = ( x . y) + ( x . z)
P5. For every element x BS t here exist s an element x BS ( called t he
complement of x) such t hat x + x = 1 and x . x = 0
P6. There exist at least t wo element s x and y BS such t hat x
y.

Pr oposi t i ons f r om Hunt i ngt on s Post ul at es
We derive several new proposit ions using t he basic Hunt ingt ons post ulat es.
Through t hese proposit ions we will be able t o explore t he st ruct ures and implicat ions
of t hat branch of mat hemat ics. Such proposit ions are called t heorems. A t heorem
gives a relat ionship among t he variables.
Def i ni t i on: A Boolean expression is a const ant , 1 or 0, a single Boolean variable or
it s complement , or several const ant s and/ or Boolean variables and/ or t heir
complement s used in combinat ion wit h one or more binary operat ors.
According t o t his definit ion 0, 1, x and x are Boolean expressions. I f A and B are
Boolean expressions, t hen A , B , A+ B and A. B are also Boolean expressions.
Dual i t y: Many of t he Hunt ingt ons post ulat es are given as pairs, and differ only by
t he simult aneous int erchange of operat ors "+ " and ". " and t he element s "0" and "1".
This special propert y is called dualit y.
The propert y of dualit y can be ut ilized effect ively t o est ablish many useful propert ies
of Boolean algebra.
The dualit y principle
I f t wo expressions can be proven equivalent by applying a sequence of basic
post ulat es, t hen t he dual expressions can be proven equivalent by simply applying
t he sequence of dual post ulat es
This implies t hat for each Boolean propert y, which we est ablish, t he dual propert y is
also valid wit hout needing addit ional proof.
Let us derive some useful propert ies:
Pr oper t y 1: Special law of 0 and 1
For all x BS,
a. x . 0 = 0
b. x + 1 = 1
Proof: x . 0 = ( x . 0) + 0 ( post ulat e 2a)
= ( x . 0) + ( x . x ) ( post ulat e 5b)
= x . ( 0 + x ) ( post ulat e 4b)
= x . x ( post ulat e 2a)
= 0 ( post ulat e 5b)
Propert y: b can be proved by applying t he law of dualit y, t hat is, by int erchanging ". "
and "+ ", and "1" and "0".
Pr oper t y 2:
a. The element 0 is unique.
b. The element 1 is unique.
Proof for Part b by cont radict ion: Let us assume t hat t here are t wo 1s denot ed 1
1

and 1
2
. Post ulat e 2b st at es t hat
x. 1
1
= x and y. 1
2
= y
Applying t he post ulat e 3b on commut at ivit y t o t he second relat ionship, we get
1
1
. x = x and 1
2
. y = y
Let t ing x = 1
2
and y = 1
1
, we obt ain
1
1
. 1
2
= 1
2
and 1
2
. 1
1
= 1
1

Using t he t ransit ivit y propert y of any equivalence relat ionship we obt ain 1
1
= 1
2
,
which becomes a cont radict ion of our init ial assumpt ion.
Propert y a can be est ablished by applying t he principle of dualit y.
Pr oper t y 3
a. The complement of 0 is 0 = 1.
b. The complement of 1 is1 = 0.
Proof: x + 0 = x ( post ulat e 2a)
0 + 0 = 0
0 + 0 = 1 ( post ulat e 5a)
0 = 1
Part b is valid by t he applicat ion of principle of dualit y.
Pr oper t y 4: I dempot ency law
For all x BS,
a. x + x = x
b. x . x = x
Proof: x + x = ( x + x) . 1 ( post ulat e 2b)
= ( x + x) . ( x + x ) ( post ulat e 5a)
= x + ( x . x ) ( post ulat e 4a)
= x + 0 ( post ulat e 5b)
= x ( post ulat e 2a)
x . x = x ( by dualit y)
Pr oper t y 5: Adj acency law
For all x and y BS,
a. x . y + x . y = x
b. ( x + y) . ( x + y ) = x
Proof: x . y + x . y = x . ( y + y ) ( post ulat e 4b)
= x . 1 ( post ulat e 5a)
= x ( post ulat e 2b)
( x + y) . ( x + y ) = x ( by dualit y)
The adj acency law is very useful in simplifying logical expressions encount ered in t he
design of digit al circuit s. This propert y will be ext ensively used in lat er learning
unit s.
Pr oper t y 6: First law of absorpt ion
For all x and y BS,
a. x + ( x . y) = x
b. x . ( x + y) = x
Proof x . ( x + y) = ( x + 0) . ( x + y) ( post ulat e 2a)
= x + ( 0 . y) ( post ulat e 4a)
= x + 0 ( propert y 2.1a)
= x ( post ulat e 2a)
x + ( x . y) = x ( by dualit y)
Pr oper t y 7: Second law of absorpt ion
For all x and y BS,
a. x + ( x . y) = x + y
b. x . ( x + y) = x . y
Proof: x + ( x . y) = ( x + x ) . ( x + y) ( post ulat e 4a)
= 1. ( x + y) ( post ulat e 5a)
= x + y ( post ulat e 2b)
x . ( x + y) = x . y ( by dualit y)
Pr oper t y 8: Consensus law
a. x . y + x . z + y . z = x . y + x . z
b. ( x + y) . ( x + z) . ( y + z) = ( x + y) . ( x + z)
Proof: x . y + x . z + y . z
= x . y + x . z + 1 . y . z ( post ulat e 2b)
= x . y + x . z + ( x + x ) . y . z ( post ulat e 5a)
= x . y + x . z + x . y . z + x . y . z ( post ulat e 4b)
= x . y + x . y . z + x . z + x . y . z ( post ulat e 3a)
= x . y . ( 1 + z) + x . z . ( 1 + y) ( post ulat e 4b)
= x . y . 1 + x . z . 1 ( propert y 2.1b)
= x . y + x . z ( post ulat e 2b)
( x + y) . ( x + z) . ( y + z) = ( x + y) . ( x + z) ( by dualit y)
Pr oper t y 9: Law of ident it y
For all x and y BS, if
a. x + y = y
b. x . y = y, t hen x = y
Proof: Subst it ut ing ( a) int o t he left - hand side of ( b) , we have
x . ( x + y) = y
However by t he first law of absorpt ion
x . ( x + y) = x ( propert y 6)
Therefore, by t ransit ivit y x = y
Pr oper t y 10: The law of involut ion
For all x BS, x = x
Proof: We need t o show t hat t he law of ident it y ( propert y 2. 9) holds, t hat is,
( x + x) = x and x . x = x
x = 0 x + ( post ulat e 2a)
= ) x . x ( x + ( post ulat e 5b)
= ) x x ).( x x ( + + ( post ulat e 4a)
= 1 ). x x ( + ( post ulat e 5a)
Thus x = x x +
Also x = 1 . x ( post ulat e 2b)
= ) x x .( x + ( post ulat e 5a)
= x . x x . x + ( post ulat e 4b)
= 0 x . x + ( post ulat e 5b)
= x . x ( post ulat e 2a)
Therefore by t he law of ident it y, we have x x =
Pr oper t y 11: DeMorgan' s Law
For all x, y BS,
a. y x + = y . x
b. y . x = y x +
Proof: ) y . x (y. ) y . x (x. ) y . x ).( y x ( + = + ( post ulat e 4b)
= 0 + 0
= 0 ( post ulat e 2a)
y ) y . x (x ) y . x ( y) (x + + = + + ( post ulat e 3a)
= y y x + + ( propert y 2.7a)
= x + 1 ( post ulat e 5a)
= 1 ( propert y 2.16)
Therefore, ( x . y) is t he complement of ( x + y) .
x.y = y x + ( by dualit y)
DeMorgan' s law bridges t he AND and OR operat ions, and est ablishes a met hod for
convert ing one form of a Boolean funct ion int o anot her. More part icularly it gives a
met hod t o form complement s of expressions involving more t han one variable. By
employing t he propert y of subst it ut ion, DeMorgan' s law can be ext ended t o
expressions of any number of variables. Consider t he following example:
z y x + + = z . y . x
Let y + z = w, t hen x + y + z = x + w.
w x + = w . x ( by DeMorgan' s law)
w x + = z y x + + ( by subst it ut ion)
= z y . x + ( by DeMorgan' s law)
= z . y . x ( by DeMorgan' s law)
At t he end of t his Sect ion t he reader should remind himself t hat all t he post ulat es
and propert ies of Boolean algebra are valid when t he number of element s in t he BS
is finit e. The case of t he set BS having only t wo element s is of more int erest here
and in t he t opics t hat follow in t his course on Design of Digit al syst ems.
All t he ident it ies derived in t his Sect ion are list ed in t he Table 1 t o serve as a ready
reference.
TABLE: Useful I dent it ies of Boolean Algebra
Complement at ion 0 x x. =
1 x x = +
0 - 1 law x. 0 = 0
x+ 1 = 1
x+ 0 = x
x. 1 = x
I dempot ency x. x = x
x+ x = x
I nvolut ion x x =
Commut at ive law x . y = y . x
X + y = y + x
Associat ive law ( x . y) .z = x. ( y. z)
( x + y) + z = x + ( y+ z)
Dist ribut ive law x + ( y. z) = ( x+ y) . ( x+ z)
X . ( y+ z) = x. y + x. z
Adj acency law x y x. x.y = +
x y) y).(x (x = + +
Absorpt ion law x + x . y = x
x . ( x+ y) = x
y x .y x x + = +
x.y y) x x.( = +
Consensus law .z x x.y y.z .z x x.y + = + +
z) x y).( (x z) z).(y x y).( (x + + = + + +
DeMorgan' s law y . x y x = +
y x x.y + =
The propert ies of Boolean algebra when t he set BS has t wo element s, namely 0 and
1, will be explored next .

BOOLEAN OPERATORS
Recall t hat Boolean Algebra is defined over a set ( BS) wit h finit e number of element s. I f
t he set BS is rest rict ed t o t wo element s { 0, 1} t hen t he Boolean variables can t ake only
one of t he t wo possible values. As all swit ches t ake only t wo possible posit ions, for
example ON and OFF, Boolean Algebra wit h t wo element s is more suit ed t o working wit h
swit ching circuit s. I n all t he swit ching circuit s encount ered in elect ronics, t he variables
t ake only one of t he t wo possible values.
Def i ni t i on: A binary variable is one t hat can assume one of t he t wo values, 0 or 1.
These t wo values, however, are meant t o express t wo exact ly opposit e st at es. I t means,
if a binary variable A 0 t hen A = 1. Similarly if A 1, t hen A = 0.
Not e t hat it agrees wit h our int uit ive underst anding of elect rical swit ches we are familiar
wit h.
a. if swit ch A is not open t hen it is closed
b. if swit ch A is not closed t hen it is open
The values 0 and 1 should not be t reat ed numerically, such as t o say "0 is less t han 1"
or " 1 is great er t han 0".
Def i ni t i on: The Boolean operat or NOT, also known as complement operat or represent ed
by " " ( overbar) on t he variable, or "
/
" ( a superscript slash) aft er t he variable, is
defined by t he following t able.
A A
/

0 1
1 0

Though it is more popular t o use t he symbol " " ( overbar) in most of t he t ext - books, we
will adopt t he "
/
" t o r epresent t he complement of a variable, for convenience of t yping.
The circuit represent at ion of t he NOT operat or is shown in t he following:

Def i ni t i on: The Boolean operat or " + " known as OR operat or is defined by t he t able
given in t he following.
A B A+ B
0 0 0
0 1 1
1 0 1
1 1 1

2
The circuit symbol for logical OR operat ion is given in t he following.

Def i ni t i on: The Boolean operat or ". " known as AND operat or is defined by t he t able
given below
A B A. B
0 0 0
0 1 0
1 0 0
1 1 1

The circuit symbol for t he logical AND operat ion is given in t he following.

The relat ionship of t hese operat ors t o t he elect rical swit ching circuit s can be seen from
t he equivalent circuit s given in t he following.
Consider t he NOT operat or

Consider t he OR and AND operat ors

A B A + B A. B
Open Open Open Open
Open Closed Closed Open
Closed Open Closed Open
Closed Closed Closed Closed

We can define several ot her logic operat ions besides t hese t hree basic logic operat ions.
These include
A
/
A
open closed
closed open

A
A
/

NAND
NOR
Exclusive- OR ( Ex- OR for short )
Exclusive- NOR ( Ex- NOR)
These are defined in t erms of different combinat ions of values t he variables assume, as
indicat ed in t he following t able:
A B ( A. B)
/
NAND
( A+ B)
/
NOR
AB
EX- OR
A B
EX- NOR
0 0 1 1 0 1
0 1 1 0 1 0
1 0 1 0 1 0
1 1 0 0 0 1

Observe t he following:
NAND oper at ion is j ust t he complement of AND operat ion
NOR operat ion is t he complement of OR operat ion.
Exclusive- OR operat ion is similar t o OR operat ion except t hat EX- OR
operat ion leads t o 0, when t he t wo variables t ake t he value of 1.
Exclusive- NOR is t he complement of Exclusive- OR operat ion.
These funct ions can also be represent ed graphically as shown in t he figure.

A set of Boolean operat ions is called funct ionally complet e set if all Boolean expressions
can be expressed by t hat set of operat ions. AND, OR and NOT const it ut e a funct ionally
complet e set . However, it is possible t o have several combinat ions of Boolean operat ions
as funct ionally complet e set s.
- OR, AND and NOT
- OR and NOT
- AND and NOT
4
- NAND
- NOR
The complet eness of t hese combinat ions is shown in t he following.
All Boolean funct ions t hrough AND and NOT operat ions

All Boolean funct ions t hrough OR and NOT operat ions

All Boolean funct ions t hrough NAND funct ion

All Boolean funct ions t hrough NOR funct ion
6

Digital Electronics
Module 2: Boolean Algebra and
Boolean Operators: Logic Functions
N.J. Rao
Logic Functions
Electrical and electronic circuits can be built with devices
that have two states
Variables with only two values are called Logic variables
or Switching variables
We defined several Boolean/Logic operators
A large variety of situations and problems can be
described using logic variables and logic operators.
The description is done through logic functions
Descriptions of logic functions
Algebraic
Truth-table
Logic circuit
Hardware description language
Maps
Each form of representation is convenient in a different
context.
Logic Functions in Algebraic Form
Let A1, A2, . . . An be logic variables defined on the set
BS = {0,1}.
A logic function of n variables associates a value 0 or 1 to
every one of the possible 2
n
combinations of the n
variables.
F1 = A1.A2/.A3.A4 + A1/.A2.A3/.A4 + A1.A2/.A3.A4/
F1 is a function of 4 variables
It is not necessary to have all the variables in all the terms.
F2 = A1.A2 + A1/.A2.A3/ + A1/.A2.A4/.A5
Properties of logic functions
If F1(A1, A2, ... An ) is a logic function, then (F1(A1,
A2, ... A n))/ is also a Boolean function.
If F1 and F2 are two logic functions, then F1+F2 and
F1.F2 are also Boolean functions.
Any function that is generated by the finite application
of the above two rules is also logic function
There are a total of 2 distinct logic functions of n
variables.
2
n
2
n
Terms to get familiarized
Literal: not-complemented or complemented version of
a variable (A and A
/
are literals)
Product term: A series of literals related to one another
through an AND operator.
Ex: A.B
/
.D, A.B.D
/
.E, etc.
Sum term: A series of literals related to one another
through an OR operator.
Ex: A+B
/
+D, A+B+D
/
+E, etc.
Truth Table
It is a tabular representation of a logic function.
It gives the value of the function for all possible
combinations of the values of the variables
For each combination, the function takes either 1 or 0
These combinations are listed in a table, which
constitute the truth table for the given function.
The information contained in the truth table and in the
algebraic representation of the function are the same.
Example of a truth-table
F(A, B) = A.B + A.B
/
Truth table
1 1 1
1 0 1
0 1 0
0 0 0
F B A
Truth and Truth Table
The term truth table came into usage long before
Boolean algebra came to be associated with digital
electronics.
Boolean functions were originally used to establish truth
or falsehood of a statement.
When statement is true the "1" is associated with it
When it is false "0" is associated.
This usage got extended to the variables associated with
digital circuits
Inappropriateness of truth and falsity
All variables in digital systems are indicative of actions.
Examples: "CLEAR", "LOAD", "SHIFT", "ENABLE", and
"COUNT"
They are suggestive of actions.
When a variable is asserted, the intended action takes
place
When a variable is not asserted the intended action does
not take place
Associate "1" with the assertion of a variable, and "0"
with the non-assertion of that variable.
Assertion and Non-assertion
F = A.B + A.B
/
Read it as "F is asserted when A and B are asserted or
A is asserted and B is not asserted".
We will continue to use the term "truth table" for
historical reasons
We understand it as
an input-output table associated with a logic function
but not as something that is concerned with the
establishment of truth.
Size of the Truth-Table
A five variable function would require 32 entries
A six-variable function would require 64 entries
When the number of variables increase a simple artefact
may be adopted.
A truth table will have entries only for those terms for
which the value of the function is "1", without loss of any
information.
This is particularly effective when the function has
smaller number of terms.
Simpler Truth Table
F = A.B.C.D
/
.E
/
+ A.B
/
.C.D
/
.E + A
/
.B
/
.C.D.E + A.B
/
.C
/
.D.E
1 1 1 0 0 1
1 1 1 1 0 0
1 1 0 1 0 1
1 0 0 1 1 1
F E D C B A
English Sentences Logic Functions
Anil freaks out with his friends if it is Saturday and
he completed his assignments
F = 1 if Anil freaks out with his friends; otherwise F = 0
A = 1 if it is Saturday; otherwise A = 0
B = 1 if he completed his assignments; otherwise B = 0
F is asserted if A is asserted and B is asserted.
The sentence, therefore, can be translated into a logic
equation as
F = A.B

Rahul will attend the Networks class
if and only if his friend Shaila is attending the class
and the topic being covered in class is important from
examination point of view
or there is no interesting matinee show in the city
and
the assignment is to be submitted
F
A
B
C
/
D
F = A.B + C
/
.D
Minterms
A logic function has product terms.
Product terms that consist of all the variables of a
function are called "canonical product terms",
"fundamental product terms" or "minterms".
The term A.B.C
/
is a minterm in a three variable logic
function, but will be a non-minterm in a four variable logic
function.
Maxterms
Sum terms which contain all the variables of a Boolean
function are called "canonical sum terms", "fundamental
sum terms" or "maxterms".
(A+B
/
+C) is an example of a maxterm in a three variable
logic function.
Minterms and Maxterms of 3 variables
A
/
+ B
/
+ C
/
= M
7
ABC = m
7
1 1 1 7
A
/
+ B
/
+ C= M
6
A B C
/
= m
6
0 1 1 6
A+ B+ C
/
= M
5
A B
/
C = m
5
1 0 1 5
A+ B+ C= M
4
A B
/
C
/
= m
4
0 0 1 4
A+ B
/
+ C
/
= M
3
A
/
BC = m
3
1 1 0 3
A+ B
/
+ C= M
2
A
/
BC
/
= m
2
0 1 0 2
A+ B+ C
/
= M
1
A
/
B
/
C = m
1
1 0 0 1
A+ B+ C= M
0
A
/
B
/
C
/
= m
0
0 0 0 0
Maxterms Minterms C B A Term No.
Logic function as a sum of minterms
Consider a function of three variables
F = m
0
+ m
3
+ m
5
+ m
6
This is equivalent to
F = A
/
B
/
C
/
+ A
/
BC + A
/
BC
/
+ ABC
/
A logic function that is expressed as an OR of several
product terms is considered to be in "sum-of-products" or
SOP form.
Logic function as a product of
Maxterms
F is a function of three variables
F = M0 . M3 . M5 . M6
When F expressed as an AND of several sum terms, it is
considered to be in "product-of-sums" or POS form.
Canonical form
If all the terms in an expression or function are
canonical in nature, then it is considered to be in
canonical form.
minterms in the case of SOP form
maxterms in the case of POS form
Canonical form (2)
Consider the function
F = A.B + A.B
/
.C + A
/
.B.C
It is not in canonical form
It can be converted into canonical form:
A.B = A.B.1 (postulate 2b)
= A.B.(C + C
/
) (postulate 5a)
= A.B.C + A.B.C
/
(postulate 4b)
The canonical version of F
F = A.B.C + A.B.C
/
+ A.B
/
.C + A
/
.B.C
Priorities in a logical expression
NOT (
/
) operation has the highest priority,
AND (.) has the next priority
OR (+) has the last priority
in
F = A.B + A.B
/
.C + A
/
.B.C
Sequence of operations
F = A.B + A.B
/
.C + A
/
.B.C
NOT operation on B and A
AND terms: A.B, A.B
/
.C, A
/
.B.C
OR operation on AB, A.B
/
.C and A
/
. B.C
The order of priority can be modified through using
parentheses.
F1 = A.(B+C
/
) + A
/
.(C+D)
By applying the distributive law, these expressions can
be brought into the SOP form
Circuit Representation of Logic
Functions
A logic function can be represented in a
circuit form using these circuit symbols
F1 = A.B + A.B
/
Other forms
Boolean function in POS form
F2 = (A+B+C) . (A+B
/
+C
/
)
Other forms
Logical function in terms of other functionally complete
set of logical operations
NAND is one such functionally complete set.
Other forms
NOR is another functionally complete set.
A
B
F1

Logi c Funct i ons
Many t ypes of elect rical and elect ronic circuit s can be built wit h devices t hat have t wo
possible st at es. We are, t herefore int erest ed in working wit h variables, which can t ake
only t wo values. Such t wo valued variables are called Logic variables or Swit ching
variables.
We defined several Boolean operat ors, which can also be called Logic operat ors. We will
find t hat it is possible t o describe a wide variet y of sit uat ions and problems using logic
variables and logic operat ors. This is done t hrough defining a logic funct ion of logic
variables.
We can describe logic funct ions in several ways. These include
Algebraic
Trut h- t able
Logic circuit
Hardware descript ion language
Maps
We use all t hese forms t o express logic funct ions in working wit h digit al circuit s. Each
form of represent at ion is convenient in some cont ext . I nit ially we will work wit h
algebraic, t r ut h- t able, and logic circuit represent at ion of logic funct ions.
The obj ect ives of t his learning unit are
1. Writ ing t he out put of a logic net work, whose word descript ion is given, as a
funct ion of t he input variables eit her as a logic funct ion, a t rut h- t able, or a logic
circuit .
2. Creat e a t rut h- t able if t he descript ion of a logic circuit is given in t erms of a logic
funct ion or as a logic circuit .
3. Writ e a logic funct ion if t he descript ion of a logic circuit is given in t erms of a
t rut h- t able or as a logic circuit .
4. Creat e a logic circuit if it s descript ion is given in t erms of a t rut h- t able or as a
logic funct ion.
5. Expand a given logic funct ion in t erms of it s mint erms or maxt erms.
6. Convert a given t rut h- t able int o a logic funct ion int o mint erm or maxt erm forms.
7. Explain t he nat ure and role of dont care t erms

Logi c Funct i ons i n Al gebr ai c For m
Let A
1
, A
2
, . . . A
n
be logic variables defined on t he set BS = { 0, 1} . A logic funct ion of n
variables associat es a value 0 or 1 t o every one of t he possible 2
n
combinat ions of t he n
variables. Let us consider a few examples of such funct ions.
F1 = A1. A2
/
. A3. A4 + A1
/
. A2. A3
/
. A4 + A1. A2
/
. A3. A4
/

F1 is a funct ion of 4 variables. You not ice t hat all t erms in t he funct ion have all t he four
variables. I t is not necessary t o have all t he variables in all t he t erms. Consider t he
following example.
F2 = A1. A2 + A1
/
. A2. A3
/
+ A1
/
. A2. A4
/
. A5
F2 happens t o be simplified version of a funct ion, which has a much larger number of
t erms, where each t erm has all t he variables. We will explore ways and means t o
generat e such simplificat ions from a given logic expression.
The logic funct ions have t he following propert ies:
1. I f F1( A
1
, A
2
, . . . A
n
) is a logic funct ion, t hen ( F1( A
1
, A
2
, . . . A
n
) )
/
is also a Boolean
funct ion.
2. I f F1 and F2 are t wo logic funct ions, t hen F1+ F2 and F1. F2 are also Boolean
funct ions.
3. Any funct ion t hat is generat ed by t he finit e applicat ion of t he above t wo rules is
also a logic funct ion
Try t o underst and t he meaning of t hese propert ies by solving t he following examples.
I f F1 = A. B.C + A.B
/
. C + A. B. C
/
what is t he logic funct ion t hat represent s F1
/
?
I f F1 = A. B + A
/
. C and F2 = A. B
/
+ B. C writ e t he logic funct ions F1 + F2 and F1. F2?
As each one of t he combinat ions can t ake value of 0 or 1, t here are a t ot al of 2
2
n
dist inct
logic funct ions of n var iables.
I t is necessary t o int roduce a few t erms at t his st age.
"Li t er al " is a not - complement ed or complement ed version of a var iable. A and A
/
are
lit erals
" Pr oduct t er m" or "product " refers t o a series of lit erals relat ed t o one anot her t hrough
an AND operat or. Examples of product t erms are A. B
/
. D, A. B.D
/
. E, et c.
"Sum t er m" or "sum" refers t o a series of lit erals relat ed t o one anot her t hrough an OR
operat or. Examples of sum t erms are A+ B
/
+ D, A+ B+ D
/
+ E, et c.

The choice of t erms "product " and "sum" is possibly due t o t he similarit y of OR and AND
operat or symbols "+ " and ". " t o t he t radit ional arit hmet ic addit ion and mult iplicat ion
operat ions.

Tr ut h Tabl e Descr i pt i on of Logi c Funct i ons
The t rut h t able is a t abular represent at ion of a logic funct ion. I t gives t he value of t he
funct ion for all possible combinat ions of values of t he variables. I f t here are t hree
variables in a given funct ion, t here are 2
3
= 8 combinat ions of t hese variables. For each
combinat ion, t he funct ion t akes eit her 1 or 0. These combinat ions are list ed in a t able,
which const it ut es t he t rut h t able for t he given funct ion. Consider t he expression,
F ( A, B) = A. B + A. B
/

The t rut h t able for t his funct ion is given by,
A B F
0 0 0
0 1 0
1 0 1
1 1 1

The informat ion cont ained in t he t rut h t able and in t he algebraic represent at ion of t he
funct ion are t he same.
The t erm t rut h t able came int o usage long before Boolean algebra came t o be
associat ed wit h digit al elect ronics. Boolean funct ions were originally used t o est ablish
t rut h or falsehood of st at ement s. When st at ement is t rue t he symbol "1" is associat ed
wit h it , and when it is false "0" is associat ed. This usage got ext ended t o t he variables
associat ed wit h digit al circuit s. However, t his usage of adj ect ives "t rue" and "false" is
not appropriat e when associat ed wit h variables encount ered in digit al syst ems. All
variables in digit al syst ems are indicat ive of act ions. Typical examples of such signals
are "CLEAR" , " LOAD" , " SHI FT", "ENABLE" , and " COUNT" . These are suggest ive of
act ions. Therefore, it is appropriat e t o st at e t hat a variable is ASSERTED or NOT
ASSERTED t han t o say t hat a variable is TRUE or FALSE. When a variable is assert ed,
t he int ended act ion t akes place, and when it is not assert ed t he int ended act ion does not
t ake place. I n t his cont ext we associat e "1" wit h t he assert ion of a variable, and "0" wit h
t he non- assert ion of t hat variable. Consider t he logic funct ion,
F = A. B + A. B
/

I t should now be read as "F is assert ed when A and B are assert ed or A is assert ed and
B is not assert ed". This convent ion of using "assert ion and non- assert ion" wit h t he
logic variables will be used in all t he Learning Unit s of t his course on Digit al Syst ems.
The t erm t rut h t able will cont inue t o be used for hist orical reasons. But we underst and
it as an input - out put t able associat ed wit h a logic funct ion, but not as somet hing t hat is
concerned wit h t he est ablishment of t r ut h.

As t he number of variables in a given funct ion increases, t he number of ent ries in t he
t rut h t able increases exponent ially. For example, a five variable expression would
require 32 ent ries and a six- variable funct ion would require 64 ent ries. I t , t herefore,
becomes inconvenient t o prepare t he t rut h t able if t he number of variables increases
beyond four. However, a simple art efact may be adopt ed. A t rut h t able can have
ent ries only for t hose t erms for which t he value of t he funct ion is "1", wit hout loss of any
informat ion. This is part icular ly effect ive when t he funct ion has only a small number of
t erms. Consider t he Boolean funct ion wit h six variables
F = A. B. C. D
/
. E
/
+ A. B
/
.C. D
/
. E + A
/
. B
/
. C.D. E + A. B
/
. C
/
. D. E
The t rut h t able will have only four ent ries rat her t han 64, and t he represent at ion of t his
funct ion is
A B C D E F
1 1 1 0 0 1
1 0 1 0 1 1
0 0 1 1 1 1
1 0 0 1 1 1

Trut h t able is a very effect ive t ool in working wit h digit al circuit s, especially when t he
number of variables in a funct ion is small, less t han or equal t o five.

Conv er si on of Engl i sh Sent ences t o Logi c Funct i ons
Some of t he problems t hat can be solved using digit al circuit s are expressed t hrough one
or more sent ences. For example,
At t he t raffic j unct ion t he amber light should come on 60 seconds aft er t he red
light , and get wit ched off aft er 5 seconds.
I f t he number of coins put int o t he vending machine exceed five rupees it should
dispense a Thums Up bot t le.
The lift should st art moving only if t he doors are closed and a floor number is
chosen.
These sent ences should init ially be t ranslat ed int o logic equat ions. This is done t hrough
breaking each sent ence int o phrases and associat ing a logic variable wit h each phrase.
As st at ed earlier many of t hese phrases will be indicat ive of act ions or direct ly represent
act ions. We first mark each act ion relat ed phrase in t he sent ence. Then we associat e a
logic variable wit h it . Consider t he following sent ence, which has t hree phrases:
Anil freaks out wit h his fr iends if it is Sat urday and he complet ed his assignment s

We will now associat e logic variables wit h each phr ase. The words if and and are not
included in any phrase and t hey show t he relat ionship among t he phrases.
F = 1 if Anil freaks out wit h his fr iends ; ot herwise F = 0
A = 1 if it is Sat urday ; ot herwise A = 0
B = 1 if he complet ed his assignment s ; ot herwise B = 0
F is assert ed if A is assert ed and B is assert ed. The sent ence, t herefore, can be
t ranslat ed int o a logic equat ion as
F = A. B
For simple problems it may be possible t o direct ly writ e t he logic funct ion from t he word
descript ion. I n more complex cases it is necessary t o properly define t he variables and
draw a t rut h- t able before t he logic funct ion is prepared. Somet imes t he given sent ences
may have some vagueness, in which case clarificat ions need t o be sought from t he
source of t he sent ence. Let us consider anot her sent ence wit h more number of
phrases.
Rahul will at t end t he Net works class if and only if his fr iend Shaila is at t ending t he class
and t he t opic being covered in class is import ant fr om examinat ion point of view or t here
is no int erest ing mat inee show in t he cit y and t he assignment is t o be submit t ed. Let us
associat e different logic variables wit h different phrases.
2
Rahul will at t end t he Net works class if and only if his fr iend Shaila is at t ending t he class
F A
and t he t opic being covered in class is import ant fr om examinat ion point of view or

B
t here is no int erest ing mat inee show in t he cit y and t he assignment is t o be
submit t ed

C
/
D

Wit h t he above assigned variables t he logic funct ion can be writ t en as

F = A. B + C
/ .
D

Mi nt er ms and Max t er ms
A logic funct ion has product t erms. Product t erms t hat consist of all t he variables of a
funct ion are called " canonical product t erms", " fundament al product t erms" or
"mint erms" . For example t he logic t erm A. B. C' is a mint erm in a t hree variable logic
funct ion, but will be a non- mint erm in a four variable logic funct ion. Sum t erms which
cont ain all t he variables of a Boolean funct ion are called "canonical sum t erms",
"fundament al sum t erms" or "maxt erms". ( A+ B
/
+ C) is an example of a maxt erm in a
t hree variable logic funct ion.
Consider t he Table which list s all t he mint erms and maxt erms of t hree variables. The
mint erms are designat ed as m
0
, m
1
, . . . m
7
, and maxt erms are designat ed as M
0
, M
1
, . .
. M
7
.
Term No. A B C Mint erms Maxt erms
0 0 0 0 A
/
B
/
C
/
= m
0
A

+ B

+ C

= M
0

1 0 0 1 A
/
B
/
C = m
1
A

+ B

+ C
/
= M
1

2 0 1 0 A
/
BC
/
= m
2
A

+ B
/
+ C

= M
2

3 0 1 1 A
/
BC = m
3
A

+ B
/
+ C
/
= M
3

4 1 0 0 A B
/
C
/
= m
4
A

+ B

+ C

= M
4

5 1 0 1 A B
/
C = m
5
A

+ B

+ C
/
= M
5

6 1 1 0 A B C
/
= m
6
A
/
+ B
/
+ C

= M
6

7 1 1 1 ABC = m
7
A
/
+ B
/
+ C
/
= M
7

A logic funct ion can be writ t en as a sum of mint erms. Consider F, which is a funct ion of
t hree variables.
F = m
0
+ m
3
+ m
5
+ m
6

This is equivalent t o
F = A
/
B
/
C
/
+

A
/
BC

+ AB
/
C

+ ABC
/

A logic funct ion t hat is expressed as an OR of several product t erms is considered t o be
in " sum- of- product s" or SOP form. I f it is expressed as an AND of several sum t erms, it
is considered t o be in "product - of- sums" or POS form. Examples of t hese t wo forms are
given in t he following:
F1 = A. B + A. B
/
.C + A
/
. B. C ( SOP form)
F2 = ( A+ B+ C
/
) . ( A+ B
/
+ C
/
) . ( A
/
+ B
/
+ C) ( POS form)
I f all t he t erms in an expression or funct ion are canonical in nat ure, t hat is, as mint erms
in t he case of SOP form, and maxt erms in t he case of POS form, t hen it is considered t o
be in canonical form. For example, t he funct ion in t he equat ion ( 1) is not in canonical
form. However it can be convert ed int o it s canonical form by expanding t he t erm A. B as

A. B = A . B . 1 ( post ulat e 2b)
= A . B . ( C + C
/
) ( post ulat e 5a)
= A . B . C + A . B . C
/
( post ulat e 4b)
The canonical version of F1 is,
F1 = A. B. C + A. B. C
/
+ A. B
/
. C + A
/
. B.C
The Boolean funct ion F2 is in canonical form, as all t he sum t erms are in t he form of
maxt erms.
The SOP and POS forms are also referred t o as t wo- level forms. I n t he SOP form, AND
operat ion is performed on t he variables at t he first level, and OR operat ion is performed
at t he second level on t he product t erms generat ed at t he first level.
Similarly, in t he POS form, OR operat ion is performed at t he first level t o generat e sum
t erms, and AND operat ion is perfor med at t he second level on t hese sum t erms.
I n any logical expression, t he right hand side of a logic funct ion, t here are cert ain
prior it ies in performing t he logical operat ions.
NOT (
/
) operat ion has t he highest prior it y,
AND ( . ) has t he next prior it y
OR ( + ) has t he last priorit y.
I n t he expression for F1 t he operat ions are t o be performed in t he following sequence
NOT operat ion on B and A
AND t erms: A. B, A. B
/
.C, A
/
. B. C
OR operat ion on AB, AB
/
C and A
/
BC
However, t he order of priorit y can be modified t hrough using parent heses. I t is also
common t o express logic funct ions t hrough mult i- level expressions using parent heses. A
simple example is shown in t he following.
F1 = A. ( B+ C
/
) + A
/
. ( C+ D)
These expressions can be brought int o t he SOP form by applying t he dist ribut ive law.
More det ailed manipulat ion of algebraic for m of logic funct ions will be explored in
anot her Learning Unit .

Ci r cui t Repr esent at i on of Logi c Funct i ons
Represent at ion of basic Boolean operat ors t hrough circuit s was already present ed in t he
earlier Lear ning Unit . A logic funct ion can be represent ed in a circuit form using t hese
circuit symbols. Consider t he logic funct ion
F1 = A. B + A. B
/

I t s circuit form is

Consider anot her example of a Boolean funct ion given in POS form.
F2 = ( A+ B+ C) . ( A+ B
/
+ C
/
)
The circuit form of t he logical expression F2 is

F1 can also be represent ed in t erms of ot her funct ionally complet e set of logical
operat ions. NAND is one such funct ionally complet e set . NAND represent at ion of logic
expression F2 is

NOR is anot her funct ionally complet e set . NOR represent at ion of t he same funct ion F1 is

Digital Electronics
Module 2: Boolean Algebra and Boolean
Operators: Karnaugh Map Method
N.J. Rao
Karnaugh Map
Key to minimizing a logic expression is identification of
logic adjacency
Graphic representation of logic expression can facilitate
identification of adjacency
M. Karnaugh introduced (1953) a map to pictorially
represent a logical expression.
It is known as Karnaugh Map abbreviated as K-map.
Karnaugh Map
K-Map is a pictorial form of the truth-table.
The inherent structure of the map facilitates systematic
minimization
K-map uses the ability of human perception to identify
patterns and relationships when the information is
presented graphically
Logical Adjacency
Two terms are logically adjacent if they differ with
respect any one variable.
ABC is logically adjacent to A
/
BC, AB
/
C and ABC
/
ABC is not logically adjacent to A
/
B
/
C, A
/
BC
/
, A
/
B
/
C
/
,
AB
/
C
/
The entries that are adjacent in a truth-table are not
necessarily logically adjacent
K-map arranges the logically adjacent terms to be
physically adjacent
Representation of a K-map
There are two popular ways
K-maps of a two variable function (representation a is
preferred)

A
A
B
0
0
1
1
2
2
3 3
B
a b
Cells in a K-Map
The four cells (squares)
represent four minterms
Cell 0 minterm m
0
Cell 1 minterm m
1
Cell 2 minterm m
2
Cell 3 minterm m
3
Cell 1 (minterm m
1
) is adjacent
to cell 0 (minterm m
0
) and cell 3
(minterm m
3
)
A
0
1
2
3
B
Example 1
Consider a two-variable logic function
F = A
/
B + AB
/
The truth table
A
/
B (01) and AB
/
(10) are not logically adjacent
0
1
1
0
0
1
0
1
0
0
1
1
F B A
Example 1(2)
$ )
%

The two cells in which "1" is entered are not positionally

adjacent and hence are not logically adjacent
K-map of F
Example 2
$
%

F = A
/
B + AB
K-map
Cells in which "1" is entered are positionally adjacent
and hence logically adjacent
Three-Variable Karnaugh Map
A three-variable (A, B and C) K-map has 2
3
= 8 cells
The numbering followed assures logical adjacency
Cell 0 (000) and the cell 4 (100) are also adjacent (cyclic
adjacency)
The boundaries on the opposite sides of a K-map are
considered to be one common side for the associated two
cells
Group of Terms
Adjacency is not merely between two cells
F = (1, 3, 5, 7)
= A
/
B
/
C + A
/
BC + AB
/
C + ABC
= A
/
C(B
/
+B) + AC(B
/
+B)
= A
/
C + AC = (A
/
+A)C = C
Cyclic Adjacency
A cyclic relationship among the
cells 1, 3, 5 and 7 can be
observed on the map
In a three-variable map other
groups of cells that are
cyclically adjacent are
0, 1, 3 and 2
2, 3, 7 and 6
6, 7, 5 and 4
4, 5, 1 and 0
0, 2, 6 and 4
Four-variable K-Map
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
C
D
Groups with cyclic adjacency:
0, 1, 5 and 4
1, 5, 7, and 3 etc.
0, 1, 3, 2, 10, 11, 9 and 8
4, 12, 13,15,14, 6, 7 and 5
etc.
Function of four variables
F = (2, 3, 8, 9, 11, 12)
5-Variable K-Map
5-Variable K-Map (2)
Simple and cyclic adjacencies are applicable to this map
They need to be applied separately to the two sections
of the map
Cell 8 and cell 0 are adjacent.
Taking the assertion and non-assertion of A into
account, cell 0 and cell 16 are adjacent.
Similarly there are 15 more adjacent cell pairs
(4-20,12-28, 8-24, 1-17, 5-21, 13-29, 9-25, 3-19, 7-23,
15-31,11-27, 2-18, 6-22, 14-30, and 10-26).
5-Variable Function
F = A
/
BC
/
DE
/
+ A
/
BCDE
/
+ A
/
BC
/
DE + ABCDE + A
/
BC
/
D
/
E
+ ABC
/
DE
/
+ ABCDE
/
+ ABC
/
DE + ABC
/
D
/
E + ABC
/
D
/
E
/
K-Map Properties
Karnaugh Map's main feature is to convert logic
adjacency into positional adjacency
Every K-map has 2
n
cells corresponding to 2
n
minterms
Combinations are arranged in a special order so as to
keep the equivalence of logic adjacency to positional
adjacency
There are three kinds of positional adjacency, namely
simple, cyclic and symmetric
Function not in canonical POS form
If the Boolean function is available in the canonical SOP
form, a "1" is entered in all those cells representing the
minterms of the expression, and "0" in all the other cells
If it is not available in the canonical form, convert the
non-canonical form into canonical SOP form
Convert the function into the standard SOP form and
directly prepare the K-map.
Example
A
D
B
C
1 1 0 0
1 1 1 0
0 1 0 0
0 1 1 0
F = A
/
B + A
/
B
/
C
/
+ ABC
/
D + ABCD
/
There are four variables in the expression
A
/
B, containing two variables represents four minterms
A
/
B
/
C
/
represents two minterms
Function in POS form
F = (0, 4, 6, 7, 11, 12, 14, 15)
0s are filled in the cells represented by the maxterms
Function in standard POS form
Initially convert the standard POS form of the expression
into its canonical form, and enter 0s in the cells
representing the maxterms
Enter 0s directly into the map by observing the sum
terms one after the other
Example in the POS form
F = (A+B+D
/
).(A
/
+B+C
/
+D).(B
/
+C)
/
Convert into canonical POS form
F = (A+B+C+D
/
).(A+B+C
/
+D
/
)(A
/
+B+C
/
+D). (A+B
/
+C+D).
(A
/
+B
/
+C+D).(A+B
/
+C+D
/
). (A
/
+B
/
+C+D
/
)
= M1 . M3 . M10 . M4 . M12 . M5 . M13
The cells 1, 3, 4, 5, 10, 12 and 13 can have 0s entered in
them while the remaining cells are filled with 1s
Example in the POS form
F = (A+B+D
/
).(A
/
+B+C
/
+D).(B
/
+C)
(A+B+D
/
) has A and B asserted and D non-asserted. The two
maxterms associated with this sum term are 0001 (M1) and 0011 (M3)
(A
/
+B+C
/
+D) is in canonical form and the maxterm associated with is
1010 (M10)
Maxterms associated with (B
/
+C) are 0100 (M4), 1100 (M12), 0101
(M5) and 1101 (M13)
1
0
1
0
0
0
1
1
1
1
0
1
0
0
1
1
A
B
C
D
Essential, Prime and Redundant
Implicants
The patterns of adjacency of 1-entered cells are referred to
as implicants.
An implicant is a group of 2
i
(i = 0, 1 ....n) minterms
(1-entered cells) that are logically (positionally) adjacent.
Implicants and Product Terms
An implicant represents a product term
Implicant 1 represents the product term AC
/
Implicant 2 represents ABD
Implicant 3 represents BCD
Implicant 4 represents A
/
B
/
CD
/
Smaller the number of implicants the smaller the number of
product terms in the simplified Boolean expression.
Many ways of identifying implicants
Implicants with properties
A prime implicant is one that is not a subset of any
other implicant
A prime implicant which includes a 1-entered cell that is
not included in any other prime implicant is called an
essential prime implicant.
A redundant implicant is one in which all the 1-entered
cells are covered by other implicants
Example
Implicants 2, 3, 4 and 5 in (a), and 1, 2 and 3 in (b) are prime implicants
Implicants 2, 4 and 5 in (a), and
1, 2 and 3 in (b) are essential prime implicants
Implicants 1 and 3 in (a) are redundant implicants
No redundant implicants in (b)
K-map minimisation
Find the smallest set of prime implicants that
includes all the essential prime implicants
If there is a choice, the simpler prime implicant
should be chosen.
Example 1
Implicants
X1 = C
/
D
/
X9 = B
/
C
/
D
/
X2 = B
/
C
/
X10 = A
/
C
/
D
/
X3 = BD
/
X11 = AC
/
D
/
X4 = ACD X12 = AB
/
D
X5 = AB
/
C
/
X13 = ABC
X6 = BCD
/
X14 = A
/
BD
/
X7 = A
/
B
/
C
/
X15 = ABD
/
X8 = BC
/
D
/
X16 = B
/
C
/
D
All are not prime implicants
X2, X3 and X4 are essential
prime implicants
Combination 1
F1 = X1 + X4 + X6 + X16
$
%
'
&
X16
X1
X4
X6
Combination 2
$
%
'
&
X8
X4
X6
X5
X7
F1 = X4 + X5 + X6 + X7 + X8
Combination 3
$
%
'
&
X3
X2
X4
F1 = X2 + X3 + X4
Combination 4
F1 = X10 + X11 + X8 + X4 + X6
$
%
'
&
X10
X11
X16
X4
X6
Example 1: Minimization
Smallest set of prime implicants that includes
all the essential prime implicants
F1 = X2 + X3 + X4
Example
Three sets of prime implicants
(a) X1 = B
/
D
/
X2 = A
/
B X3 = BD X4 = ACD
(b) X4 = ACD X5 = AB
/
D
/
X6 = A
/
B
/
D
/
X7 = ABD X8 = A
/
BC
X9 = A
/
BC
/
(c) X7 = ABD X10 = B
/
C
/
D
/
X11 = A
/
C
/
D
/
X12 = A
/
BD
X13 = A
/
C
/
D
/
X14 = AB
/
C
Example (2)
Some simplified expressions
F = X1 + X2 + X3 + X4
= X4 + X6 + X7 + X8 + X9
= X7 + X10 + X11 + X12 + X13 + X14
Standard POS form from K- map
(Example)
Four implicants are identified
Implicant 1 and it is represented by (A + B
/
)
Implicant 2 is represented by (B
/
+ D
/
)
Implicant 3 is represented by (B + D)
Implicant 4 is represented by (A
/
+ C
/
+ D
/
)
The simplified expression in the POS form is given by;
F = (A + B
/
) . (B
/
+ D
/
) . (B + D) . (A
/
+ C
/
+ D
/
)
If we choose the implicant 5 instead of 4, the simplified
expression
F = (A + B
/
) . (B
/
+ D
/
).(B + D).(A
/
+ B +C
/
)
Minimization procedure
1. Draw the K-map with 2
n
cells, where n is the
number of variables in a Boolean function.
2. Fill in the K-map with 1s and 0s as per the
function given in the algebraic form (SOP or
POS) or truth-table form.
Minimization procedure (2)
3. Determine the set of prime implicants that consist of all
the essential prime implicants as per the criteria:
All the 1-entered or 0-entered cells are covered by a
set of implicants, while making the number of cells
covered by each implicant as large as possible.
Eliminate the redundant implicants.
Identify all the essential prime implicants.
Whenever there is a choice among the prime
implicants select the prime implicant with the
smaller number of literals.
4. If the final expression is to be generated in SOP
form, the prime implicants should be identified
by suitably grouping the positionally adjacent
1-entered cells, and converting each of the
prime implicant into a product term. The final
SOP expression is the OR of all the product
terms.
5. If the final simplified expression is to be given
in the POS form, the prime implicants should
be identified by suitably grouping the
positionally adjacent 0-entered cells, and
converting each of the prime implicant into a
sum term. The final POS expression is the
AND of all sum terms.
Incompletely specified functions
All Boolean functions are not always completely specified
Consider the BCD decoder,
Only 10 outputs are decoded from 16 possible input
combinations
The six invalid combinations of the inputs never occur
We dont-care what the output is for any of these
combinations that should never occur
These dont-care situations can be used advantageously in
generating a simpler Boolean expression
Such dont-care combinations of the variables are
represented by an "X" in the appropriate cell of the K-map
Example
The decoder has three inputs A, B and C and
an output F
Input from keyboard
Input from mouse
Input from light-pen
Output to printer
Output to plotter
0
0
0
1
1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1
2
3
4
5
Description Output Input Code Mode No
Truth-table and K-map with dont
cares
X 1 1
X 0 1 1
1
1 1 0 1
1 0 0 1
0 1 1 0
0 0 1 0
0 1 0 0
X 0 0 0
F C B A
Using the three dont care conditions
K-map
SOP and POS forms
F = S (4, 5) + d (0, 6, 7)
F = P (1, 2, 3) . d (0, 6, 7)
The term d (0, 6, 7) represent the dont-care terms.
Xs can be treated either as 0s or as 1s depending on the
convenience
F = A
F = AB
/
Example
F = S (0,1,4,8,10,11,12) + d(2,3,6,9,15)
The simplified expression F = B
/
+ C
/
D
/
Multiple functions in same set of
variables
F1(A,B,C) = (0, 3, 4, 5, 6); F2(A,B,C) = (1, 2, 4, 6, 7);
F3(A,B,C) = (1, 3, 4, 5, 6)
The resultant minimal expressions
F1 = B/C/ + AC/ + AB/ + A/BC
F2 = BC/ + AC/ + AB + A/B/C
F3 = AC/ + B/C + A/C
These functions have nine product terms and twenty one literals
Multiple functions in same set of
variables (2)
Minor modifications to these expressions lead to
F1 = B/C/ + AC/ + AB/ + A/BC
F2 = BC/ + AC/ + AB + A/B/C
F3 = AC/ + AB/ + A/BC + A/B/C
This leads to seven product terms and sixteen literals
F1
A
C
B
1
0 1
1
1
1 0
0
F2
1 1 1
1 1 0
0
0
A
B
C
F3
1 1
1 1 1
0 0
0
A
B
C
Kar naugh- Map
The expressions for a logical funct ion ( right hand side of a funct ion) can be very long
and have many t erms and each t erm many lit erals. Such logical expressions can be
simplified using different propert ies of Boolean algebra. This met hod of minimizat ion
requires our abilit y t o ident ify t he pat t erns among t he t erms. These pat t erns should
conform t o one of t he four laws of Boolean algebra. However, it is not always very
convenient t o ident ify such pat t erns in a given expression. I f we can represent t he
same logic funct ion in a graphic form t hat allows us t o ident ify t he inherent pat t erns,
t hen t he simplificat ion can be performed more convenient ly.
Karnaugh Map is one such graphic represent at ion of a Boolean funct ion in t he form
of a map. Karnaugh Map is due t o M. Karnaugh, who int roduced ( 1953) his version
of t he map in his paper "The Map Met hod for Synt hesis of Combinat ional Logic
Circuit s". Karnaugh Map, abbreviat ed as K- map, is act ually pict orial form of t he
t rut h- t able. This Learning Unit is devot ed t o t he Karnaugh map and it s met hod of
simplificat ion of logic funct ions.
Karnaugh map of a Boolean funct ion is graphical arrangement of mint erms, for which
t he funct ion is assert ed.
We can begin by considering a t wo- variable logic funct ion,
F = A
/
B + AB
Any t wo- variable funct ion has 2
2
= 4 mint erms. The t rut h t able of t his funct ion is

A B F
0
0
1
1
0
1
0
1
0
1
1
0

I t can be seen t hat t he values of t he variables are arranged in t he ascending order
( in t he numerical decimal sense) .
We consider t hat any t wo t erms are logically adj acent if t hey differ only wit h respect
any one variable.
For example ABC is logically adj acent t o A
/
BC, AB
/
C and ABC
/
. But it is not logically
adj acent t o A
/
B
/
C, A
/
BC
/
, A
/
B
/
C
/
, AB
/
C
/ .

The ent ries in t he t rut h- t able t hat are posit ionally adj acent are not logically adj acent .
For example A
/
B ( 01) and AB
/
( 10) are post ionally adj acent but are not logically
adj acent . The combinat ion of 00 is logically adj acent t o 01 and 10. Similarly 11 is
adj acent t o 10 and 01. Karnaugh map is a met hod of arranging t he t rut h- t able
ent ries so t hat t he logically adj acent t erms are also physically adj acent .
The K- map of a t wo- variable funct ion is shown in t he figure. There are t wo popular
ways of represent ing t he map, bot h of which are shown in t he figure. The
represent at ion, where t he variable above t he column or on t he side of t he row in
which it is assert ed, will be followed in t his and t he associat ed unit s.

There are four cells ( squares) in t his map.
The cells labelled as 0, 1, 2 and 3 represent t he four mint erms m
0
, m
1
, m
2
and
m
3
.
The numbering of t he cells is chosen t o ensure t hat t he logically adj acent
mint erms are posit ionally adj acent .
Cell 1 is adj acent t o cell 0 and cell 3, indicat ing t he mint erm m
1
( 01) is logically
adj acent t o t he mint erm m
0
( 00) and t he mint erm m
3
( 11) .
The second column, above which t he variable A is indicat ed, has t he cells 2 and 3
represent ing t he mint erms m
2
and m
3
. The variable A is assert ed in t hese t wo
mint erms.
Let us define t he concept of posit ion adj acency. Posit ion adj acency means t wo
adj acent cells sharing one side. Such an adj acency is called simple adj acency. Cell 0
is posit ionally adj acent t o cell 1 and cell 2, because cell 0 shares one side wit h each
of t hem. Similarly, cell 1 is posit ionally adj acent t o cell 0 and cell 3, as cell 2 is
adj acent t o cell 0 and cell 3, and cell 3 is adj acent t o cell 1 and cell 2.
There are ot her kinds of posit ional adj acencies, which become relevant when t he
number of variables is more t han 3. We will explore t hem at a lat er t ime.
The main feat ure of t he K- map is t hat by merely looking at t he posit ion of a cell, it is
possible t o find immediat ely all t he logically adj acent combinat ions in a funct ion.
The funct ion F = ( A
/
B + AB) can now be incorporat ed int o t he K- map by ent ering "1"
in cells represent ed by t he mint erms for which t he funct ion is assert ed. A "0" is
ent ered in all ot her cells. K- map for t he funct ion F is

You will not ice t hat t he t wo cells in which "1" is ent ered are not posit ionally adj acent .
Therefore, t hey are not logically adj acent .
Consider anot her funct ion of t wo variables.
F = A
/
B + AB
The K- map for t his funct ion is

You will not ice t hat t he cells in which "1" is ent ered are posit ionally adj acent and
hence are logically adj acent .
Thr ee- Var i abl e Kar naugh Map:
K- map for t hree variables will have 2
3
= 8 cells as shown in t he figure.

The cells are labelled 0, 1, . . , 7, which st and for combinat ions 000, 001, . . . , 111
respect ively. Not ice t hat cells in t wo columns are associat ed wit h assert ion of A, t wo
columns wit h t he assert ion of B and one row wit h t he assert ion of C.
Let us consider t he logic adj acency and posit ion adj acency in t he map.
Cell 7 ( 111) is adj acent t o t he cells 3 ( 011) , 5 ( 101) and 6 ( 110) .
Cell 2 ( 010) is adj acent t o t he cell 0 ( 000) , cell 6 ( 110) and cell 3 ( 011) .
We know from logical adj acency t he cell 0 ( 000) and t he cell 4 ( 100) should also
be adj acent . But we do not find t hem posit ionally adj acent . Therefore, a new
adj acency called "cyclic adj acency" is defined t o bring t he boundaries of a row or
a column adj acent t o each ot her. I n a t hree- variable map cells 4 ( 100) and 0
( 000) , and cells 1 ( 001) and 5 ( 101) are adj acent . The boundaries on t he
opposit e sides of a K- map are considered t o be one common side for t he
associat ed t wo cells.
Adj acency is not merely bet ween t wo cells. Consider t he following funct ion:
F = ( 1, 3, 5, 7)
= m1 + m3 + m5 + m7
= A' B' C + A' BC + AB' C + ABC
= A' C( B' + B) + AC( B' + B)
= A' C + AC
= ( A' + A) C
= C
The K- map of t he funct ion F is

I t is shown clearly t hat alt hough t here is no logic adj acency bet ween some pairs of
t he t erms, we are able t o simplify a group of t erms. For example A
/
B
/
C, ABC, A
/
BC
and AB
/
C are simplified t o result in an expression "C". A cyclic relat ionship among
t he cells 1, 3, 5 and 7 can be observed on t he map in t he form 1 3 7 5 1
( "" indicat ing "adj acent t o") . When a group of cells, always 2
i
( i < n) in number,
are adj acent t o one anot her in a sequent ial manner t hose cells are considered be
cyclically adj acent .
Ot her groups of cells wit h cyclic adj acency
0, 1, 3 and 2
2, 3, 7 and 6
6, 7, 5 and 4
4, 5, 1 and 0
0, 2, 6 and 4
So far we not iced t wo kinds of posit ional adj acencies:
Simple adj acency
Cyclic adj acency ( I t has t wo cases, one is bet ween t wo cells, and t he ot her
among a group of 2
i
cells)
Four - var i abl e Kar naugh Map: A four- variable ( A, B, C and D) K- map will have 2
4

= 16 cells.

These cells are labelled 0, 1, . . . , 15, which st and for combinat ions 0000, 0001, . . . 1111
respect ively. Not ice t hat t he t wo set s of columns are associat ed wit h assert ion of A
and B, and t wo set s of rows are associat ed wit h t he assert ion of C and D.
We will be able t o observe bot h simple and cyclic adj acencies in a four- variable map
also. 4, 8 and 16 cells can form groups wit h cyclic adj acency. Some examples of
such groups are
0, 1, 5 and 4
0, 1, 3 and 2
10, 11, 9 and 8
14, 12, 13 and15
14, 6, 7 and 15
3, 7, 15, 11, 10, 14, 6 and 2
Consider a funct ion of four variables
F = ( 2, 3, 8, 9, 11, 12)
The K- map of t his funct ion is

Fi ve- var i abl e Kar naugh Map: Karnaugh map for five variables

I t has 2
5
= 32 cells labelled as 0, 1, 2 . . . , 31, corresponding t o t he 32
combinat ions from 00000 t o 11111.
The map is divided vert ically int o t wo symmet rical part s. Variable A is not -
assert ed on t he left side, and is assert ed on t he right side. The t wo part s of t he
map, except for t he assert ion or non- assert ion of t he variable A are ident ical wit h
respect t o t he remaining four variables B, C, D and E.
Simple and cyclic adj acencies are applicable t o t his map, but t hey need t o be
applied separat ely t o t he t wo sect ions of t he map. For example cell 8 and cell 0
are adj acent . The largest number of cells coming under cyclic adj acency can go
up t o 2
5
= 32.
Anot her t ype of adj acency, called symmet ric adj acency, exist s because of t he
division of t he map int o t wo symmet rical sect ions. Taking t he assert ion and non-
assert ion of A int o account , we find t hat cell 0 and cell 16 are adj acent . Similarly
t here are 15 more adj acent cell pairs ( 4- 20, 12- 28, 8- 24, 1- 17, 5- 21, 13- 29, 9-
25, 3- 19, 7- 23, 15- 31, 11- 27, 2- 18, 6- 22, 14- 30, and 10- 26) .
Consider a funct ion of five- variable
F = A
/
BC
/
DE
/
+ A
/
BCDE
/
+ A
/
BC
/
DE + ABCDE + A
/
BC
/
D
/
E + ABC
/
DE
/
+ ABCDE
/

+ ABC
/
DE + ABC
/
D
/
E + ABC
/
D
/
E
/

From t he st udy of t wo- , t hree- , four- and five- variable Karnaugh maps, we can
summarise t he following propert ies:
1. Every Karnaugh map has 2
n
cells corresponding t o 2
n
mint erms.
2. The main feat ure of a Karnaugh Map is t o convert logic adj acency int o
posit ional adj acency.
3. There are t hree kinds of posit ional adj acency, namely simple, cyclic and
symmet ric.
We have already seen how a K- map can be prepared provided t he Boolean funct ion
is available in t he canonical SOP form.
A "1" is ent ered in all t hose cells represent ing t he mint erms of t he expression, and
"0" in all t he ot her cells.
However, t he Boolean funct ions are not always available t o us in t he canonical form.
One met hod is t o convert t he non- canonical form int o canonical SOP form and
prepare t he K- map. The ot her met hod is t o convert t he funct ion int o t he st andard
SOP form and direct ly prepare t he K- map.
Consider t he funct ion
F = A
/
B + A
/
B
/
C
/
+ ABC
/
D + ABCD
/

We not ice t hat t here are four variables in t he expression. The first t erm, A
/
B,
cont aining t wo variables act ually represent s four mint erms, and t he t erm A
/
B
/
C
/

represent s t wo mint erms. The K- map for t his funct ion is
A
D
B
C
1 1 0 0
1 1 1 0
0 1 0 0
0 1 1 0

Not ice t hat t he second column represent s A
/
B, and similarly A
/
B
/
C
/
represent s t he
t wo t op cells in t he first column. Wit h a lit t le pract ice it is always possible t o fill t he
K- map wit h 1s represent ing a funct ion given in t he st andard SOP form.
Bool ean f unct i ons i n POS f or m
Boolean funct ions, somet imes, are also available in POS form. Let us assume t hat
t he funct ion is available in t he canonical POS form. Consider an example of such a
funct ion
F = ( 0, 4, 6, 7, 11, 12, 14, 15)
I n preparing t he K- map for t he funct ion given in POS form, 0s are filled in t he cells
represent ed by t he maxt erms. The K- map of t he above funct ion is

Somet imes t he funct ion may be given in t he st andard POS form. I n such sit uat ions
we can init ially convert t he st andard POS form of t he expression int o it s canonical
form, and ent er 0s in t he cells represent ing t he maxt erms. Anot her procedure is t o
ent er 0s direct ly int o t he map by observing t he sum t erms one aft er t he ot her.
Consider an example of a Boolean funct ion given in t he POS form.
F = ( A+ B+ D
/
) . ( A
/
+ B+ C
/
+ D) . ( B
/
+ C)
This may be convert ed int o it s canonical form as
F = ( A+ B+ C+ D
/
) . ( A+ B+ C
/
+ D
/
) ( A
/
+ B+ C
/
+ D) . ( A+ B
/
+ C+ D) . ( A
/
+ B
/
+ C+ D) .
( A+ B
/
+ C+ D
/
) . ( A
/
+ B
/
+ C+ D
/
)
= M1 . M3 . M10 . M4 . M12 . M5 . M13
The cells 1, 3, 4, 5, 10, 12 and 13 can have 0s ent ered in t hem while t he remaining
cells are filled wit h 1s.
The second met hod is t hrough direct observat ion. To det ermine t he maxt erms
associat ed wit h a sum t erm we follow t he procedure of associat ing a 0 wit h t hose
variables which appear in t heir assert ed form, and a 1 wit h t he variables t hat appear
in t heir non- assert ed form. For example t he first t erm ( A+ B+ D
/
) has A and B
assert ed and D non- assert ed. Therefore t he t wo maxt erms associat ed wit h t his sum
t erm are 0001 ( M
1
) and 0011 ( M
3
) . The second t erm is in it s canonical form and t he
maxt erm associat ed wit h is 1010 ( M
10
) . Similarly t he maxt erms associat ed wit h t he
t hird sum t erm are 0100 ( M
4
) , 1100 ( M
12
) , 0101 ( M
5
) and 1101 ( M
13
) . The result ant
K- map is

We learnt in t his Learning Unit
The logic adj acency is capt ured as posit ional adj acency in a Karnaugh Map
How t o t ranslat e logic expressions given in SOP or POS forms int o K- maps
There are t hree t ypes of logical adj acency, namely, simple, cyclic and symmet ric
adj acencies
Mi ni mi zat i on w i t h Kar naugh Map
I mpl i cant s: A Karnaugh map not only includes all t he mint erms t hat represent a Boolean
funct ion, but also ar ranges t he logically adj acent t erms in posit ionally adj acent cells. As t he
informat ion is pict or ial in nat ure, it becomes easier t o ident ify any pat t erns ( relat ions) t hat
exist among t he 1- ent ered cells ( mint erms) . These pat t erns or relat ions are referred t o as
implicant s.
Def i ni t i on 1: An implicant is a group of 2
i
( i = 0, 1 .. . . n) mint erms ( 1- ent ered cells) t hat
are logically ( posit ionally) adj acent .
A st udy of implicant s enables us t o use t he K- map effect ively for simplifying a Boolean
funct ion. Consider t he K- map

There are four implicant s: 1, 2, 3 and 4.
The implicant 4 is a single cell implicant . A single cell implicant is a 1- ent ered cell
t hat is not posit ionally adj acent t o any of t he ot her cells in map.
The four implicant s account for all groupings of 1- ent ered cells. This also means t hat
t he four implicant s describe t he Boolean funct ion complet ely.
An implicant represent s a product t erm, wit h t he number of var iables appearing in t he t erm
inversely proport ional t o t he number of 1- ent ered cells it represent s.
I mplicant 1 in t he figure represent s t he product t erm AC
/

I mplicant 2 represent s ABD
I mplicant 3 represent s BCD
I mplicant 4 represent s A
/
B
/
CD
/

The smaller t he number of implicant s, and t he larger t he number of cells t hat each
implicant represent s, t he smaller t he number of product t erms in t he simplified Boolean
expression.
I n t his example we not ice t hat t here are different ways of ident ifying t he implicant s.

Five implicant s are ident ified in t he figure ( a) and t hree implicant s in t he figure ( b) for t he
same K- map ( Boolean funct ion) . I t is t hen necessary t o have a procedure t o ident ify t he
minimum number of implicant s t o represent a Boolean funct ion.
We ident ify t hree t ypes of implicant s: "prime implicant ", "essent ial implicant " and
"redundant implicant " .
A pr i me i mpl i cant is one t hat is not a subset of any one of t he ot her implicant .
An essent i al pr i me i mpl i cant is a prime implicant which includes a 1- ent ered cell t hat is
not included in any ot her prime implicant .
A r edundant i mpl i cant is one in which all t he 1- ent ered cells are covered by ot her
implicant s. A redundant implicant r epresent s a redundant t erm in an expression.
I mplicant s 2, 3, 4 and 5 in t he figure ( a) , and 1, 2 and 3 in t he figure ( b) are prime
implicant s.
I mplicant s 2, 4 and 5 in t he figure ( a) , and 1, 2 and 3 in t he figure ( b) are essent ial prime
implicant s.
I mplicant s 1 and 3 in t he figure ( a) are redundant implicant s.
Figure ( b) does not have any redundant implicant s.
Now t he met hod of K- map minimisat ion can be st at ed as
"f i nd t he smal l est set of pr i me i mpl i cant s t hat i ncl udes al l t he essent i al pr i me
i mpl i cant s account i ng f or al l t he 1- ent er ed cel l s of t he K- map" .
I f t here is a choice, t he simpler prime implicant should be chosen. The minimisat ion
procedure is best underst ood t hrough examples.
Ex ampl e 1: Find t he minimised expression for t he funct ion given by t he K- map in t he
figure.

Fift een implicant s of t he K- map are:
X1 = C
/
D
/
X2 = B
/
C
/
X3 = BD
/
X4 = ACD
X5 = AB
/
C
/
X6 = BCD
/
X7 = A
/
B
/
C
/
X8 = BC
/
D
/

X9 = B
/
C
/
D
/
X10 = A
/
C
/
D
/
X11 = AC
/
D
/
X12 = AB
/
D
X13 = ABC X14 = A
/
BD
/
X15 = ABD
/
X16 = B
/
C
/
D
Obviously all t hese implicant s are not prime implicant s and t here are several redundant
implicant s. Several combinat ions of prime implicant s can be worked out t o represent t he
funct ion. Some of t hem are list ed in t he following.
F1 = X1 + X4 + X6 + X16
= X4 + X5 + X6 + X7 + X8
= X2 + X3 + X4
= X10 + X11 + X8 + X4 + X6
The k- maps wit h t hese four combinat ions are

Among t he prime implicant s list ed in t he figure t here are t hree implicant s X1, X2 and X3
t hat group four 1- ent ered cells. Select ing t he smallest number of implicant s we obt ain t he
simplified expression as:
F = X2 + X3 + X4
= B
/
C
/
+ BD
/
+ ACD
I t may be not iced t hat X2, X3 and X4 are essent ial pr ime implicant s.
Ex ampl e 2: Minimise t he Boolean funct ion represent ed by t he K- map shown in t he figure.

Three set s of prime implicant s are:
( a) X1 = B
/
D
/
X2 = A
/
B X3 = BD X4 = ACD
( b) X4 = ACD X5 = AB
/
D
/
X6 = A
/
B
/
D
/
X7 = ABD
X8 = A
/
BC X9 = A
/
BC
/

( c) X7 = ABD X10 = B
/
C
/
D
/
X11 = A
/
C
/
D
/
X12 = A
/
BD
X13 = A
/
C
/
D
/
X14 = AB
/
C

Some of t he simplified expressions are shown in t he following:
F = X1 + X2 + X3 + X4
= X4 + X6 + X7 + X8 + X9
= X7 + X10 + X11 + X12 + X13 + X14
St andar d POS f or m f r om Kar naugh Map
As ment ioned earlier, POS form always follows some kind of dualit y, yet differ ent from t he
principle of dualit y. The implicant s are defined as groups of sums or maxt erms which
in t he map represent at ion are t he posit ionally adj acent 0- ent ered cells rat her t hen 1-
ent ered cells as in t he SOP case. When convert ing an implicant covering some 0- ent ered
cells int o a sum, a variable appears in complement ed form in t he sum if it is always 1
in value in t he combinat ions cor responding t o t hat implicant , a variable appears in
uncompliment ed form if it is always 0 in value, and t he variable does not appear at all if
it changes it s values in t he combinat ions corresponding t o t he implicant . We obt ain a
st andard POS form of expression from t he map represent at ion by ANDing all t he sums
convert ed fr om implicant s.
Ex ampl e 3: Consider a Boolean funct ion in t he POS form represent ed in t he K- map shown

in t he figure

I nit ially four implicant s are ident ified ( 1, 2, 3 and 4) .
I mplicant 1: B is assert ed and A is not - assert ed in all t he cells of implicant 1, where as
t he variables C and D change t heir values from 0 t o 1. I t is represent ed by t he sum
t erm ( A + B
/
) .
I mplicant 2: I t is represent ed by t he sum t erm ( B
/
+ D
/
) .
I mplicant 3: I t is represent ed by ( B + D) .
I mplicant 4: I t is represent ed by ( A
/
+ C
/
+ D
/
) .
The simplified expression in t he POS form is given by;
F = ( A + B
/
) . ( B
/
+ D
/
) . ( B + D) . ( A
/
+ C
/
+ D
/
)
I f we choose t he implicant 5 ( shown by t he dot t ed line in t he figure 19) inst ead of 4,
t he simplified expression get s modified as:
F = ( A + B
/
) . ( B
/
+ D
/
) . ( B + D) . ( A
/
+ B + C'
/
)
We may summarise t he procedure for minimizat ion of a Boolean funct ion t hrough a K- map
as follows:
1. Draw t he K- map wit h 2
n
cells, where n is t he number of variables in a Boolean funct ion.
2. Fill in t he K- map wit h 1s and 0s as per t he funct ion given in t he algebraic form ( SOP or
POS) or t rut h- t able for m.
3. Det ermine t he set of prime implicant s t hat consist of all t he essent ial prime implicant s
as per t he following crit eria:
All t he 1- ent ered or 0- ent ered cells are covered by t he set of implicant s, while
making t he number of cells covered by each implicant as large as possible.
Eliminat e t he redundant implicant s.
I dent ify all t he essent ial prime implicant s.
Whenever t here is a choice among t he prime implicant s select t he prime
implicant wit h t he smaller number of lit erals.
4. I f t he final expression is t o be generat ed in SOP form, t he prime implicant s should be
ident ified by suit ably grouping t he posit ionally adj acent 1- ent ered cells, and convert ing
each of t he prime implicant int o a product t erm. The final SOP expression is t he OR of
t he ident ified product t erms.
5. I f t he final simplified expression is t o be given in t he POS form, t he prime implicant s
should be ident ified by suit ably grouping t he posit ionally adj acent 0- ent ered
cells, and convert ing each of t he prime implicant int o a sum t erm. The final POS
expression is t he AND of t he ident ified sum t erms.
Si mpl i f i cat i on of I ncompl et el y Speci f i ed Funct i ons
So far we assumed t hat t he Boolean funct ions are always complet ely specified, which
means a given funct ion assumes st rict ly a specific value, 1 or 0, for each of it s 2
n

input combinat ions. This, however, is not always t he case.
Consider t he example is t he BCD decoders
The t en out put s are decoded from sixt een possible input combinat ions produced by
four input s represent ing BCD codes.
An encoding scheme chooses t en valid codes.
I rrespect ive of t he encoding scheme t here are always six combinat ions of t he input s
t hat would be considered as invalid codes.
I f t he input unit t o t he BCD decoder works in a funct ionally correct way, t hen t he six
invalid combinat ions of t he input s should never occur.
I n such a case, it does not mat t er what t he out put of t he decoder is for t hese six
combinat ions. As we do not mind what t he values of t he out put s are in such sit uat ions, we
call t hem "dont - care" sit uat ions. These dont - care sit uat ions can be used advant ageously in
generat ing a simpler Boolean expression t han wit hout t aking t hat advant age.
Such dont - care combinat ions of t he variables are represent ed by an "X" in t he appropriat e
cell of t he K- map.
Ex ampl e: This example shows how an incomplet ely specified funct ion can be represent ed
in t rut h- t able, Karnaugh map and canonical forms.
The decoder has t hree input s A, B and C represent ing t hree bit codes and an out put F. Out
of t he 2
3
= 8 possible combinat ions of t he input s, only five are described and hence
const it ut e t he valid codes. F is not specified for t he remaining t hree input codes, namely,
000, 110 and 111.

Funct ional descript ion of a decoder
Mode No I nput Code Out put Descript ion
1
2
3
4
5
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0
0
0
1
1
I nput from keyboard
I nput from mouse
I nput from light - pen
Out put t o print er
Out put t o plot t er

Treat ing t hese t hree combinat ions as t he dont - care condit ions, t he t rut h- t able may be
writ t en as:
A B C F
0 0 0 X
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

The K- map for t his funct ion is

The funct ion in t he SOP and POS forms may be writ t en as
F = ( 4, 5) + d ( 0, 6, 7)
F = ( 1, 2, 3) . d ( 0, 6, 7)
The t erm d ( 0, 6, 7) represent s t he collect ion of dont - care t erms.
The dont - cares bring some advant ages t o t he simplificat ion of Boolean funct ions. The Xs
can be t reat ed eit her as 0s or as 1s depending on t he convenience. For example t he above
map can be redrawn in t wo different ways as

The simplificat ion can be done, t herefore, in t wo different ways. The result ing expressions
for t he funct ion F are:
F = A
F = AB
/

We can generat e a simpler expression for a given funct ion by ut ilising some of t he dont -
care condit ions as 1s.
Ex ampl e: Simplify F = ( 0, 1, 4, 8, 10, 11, 12) + d( 2, 3, 6, 9, 15)
The K- map of t his funct ion is

The simplified expression t aking t he full advant age of t he dont cares is,
F = B
/
+ C
/
D
/

Si mpl i f i cat i on of sever al f unct i ons of t he same set of var i abl es
As t here could be several product t erms t hat could be made common t o more t han one
funct ion, special at t ent ion needs t o be paid t o t he simplificat ion process.
Ex ampl e: Consider t he following set of funct ions defined on t he same set of variables:
F1 ( A, B, C) = ( 0, 3, 4, 5, 6)
F2 ( A, B, C) = ( 1, 2, 4, 6, 7)
F3 ( A, B, C) = ( 1, 3, 4, 5, 6)
Let us first consider t he simplificat ion process independent ly for each of t he funct ions. The
K- maps for t he t hree funct ions and t he groupings are

The result ant minimal expressions are:
F1 = B
/
C
/
+ AC
/
+ AB
/
+ A
/
BC

F2 = BC
/
+ AC
/
+ AB + A
/
B
/
C
F3 = AC
/
+ B
/
C + A
/
C
These t hree funct ions have nine pr oduct t erms and t went y one lit erals.
I f t he groupings can be done t o increase t he number of product t erms t hat can be shared
among t he t hree funct ions, a more cost effect ive realisat ion of t hese funct ions can be
achieved. One may consider, at least as a first approximat ion, cost of realising a funct ion
is proport ional t o t he number of product t erms and t he t ot al number of lit erals present in
t he expression. Consider t he minimisat ion shown in t he figure

The result ant minimal expressions are;
F1 = B
/
C
/
+ AC
/
+ AB
/
+ A
/
BC
F2 = BC
/
+ AC
/
+ AB + A
/
B
/
C
F3 = AC
/
+ AB
/
+ A
/
BC + A
/
B
/
C
This simplificat ion leads t o seven product t erms and sixt een lit erals.

Digital Electronics
Module 2: Quine-McCluskey Method
N.J. Rao
Motivation
Map methods unsuitable if the number of variables is
more than six
Quine formulated the concept of tabular minimisation in
1952
Improved by McClusky in 1956
Quine-McClusky method
Can be performed by hand, but tedious, time-consuming
and subject to error
Better suited to implementation on a digital computer
Principle of Quine-McCusky Method
Quine-McClusky method is a two stage simplification process
Step 1: Prime implicants are generated by a special
tabulation process
Step 2: A minimal set of implicants is determined
Tabulation
List the specified minterms for the 1s of a function and
dont-cares
Generate all the prime implicants using logical
adjacency (AB
/
+ AB = A)
One can work with the equivalent binary number of the
product terms.
Example: A
/
BCD
/
and A
/
BC
/
D
/
are entered as
0110 and 0100
Combined to form a term 01-0
Creation of Prime Implicant Table
Selected prime implicants are combined and arranged
in a table
Example 1
F = S (1,2,5,6,7,9,10,11,14)
The minterms are tabulated as binary numbers in
sectionalised format.
7
11
14
3 0111
1011
1110
3
5
6
9
10
2 0101
0110
1001
1010
2
1
2
1 0001
0010
1
Decimal Column 1
No.of 1s Binary
Section
Example 1 (2)
Compare every binary number in each section with
every binary number in the next section
Identify the combinations where the two numbers differ
from each other with respect to only one bit.
Combinations cannot occur among the numbers
belonging to the same section
Example: 0001 (1) in section 1 can be combined with
0101 (5) in section 2 to result in 0-01 (1, 5).
Example 1 (3)
The results of such combinations are entered into
another column
The paired entries are checked off
The entries of one section in the second column can
again be combined together with entries in the next
section
Continue this process
Example 1 (4)
3 0111 7
1011 11
1110 14
3
01-1 (5,7)
011- (6,7)
-110 (6,14)
10-1 (9,11)
101- (10,11)
1-10 (10,14)
2 0101 5
0110 6
1001 9
1010 10
2
--10 (2,6,10,14)
--10 (2,10,6,14)
1-01 (1,5)
-001 (1,9)
0-10 (2,6)
-010 (2,10)
1 0001 1
0010 2
1
Column 3 Column 2 Column 1
No.of 1s Binary Decimal
Section
Note: Combination of entries in column 2 can only take place if the
corresponding entries have the dashes at the same place.
Example 1 (5)
All those terms which are not checked off constitute the
set of prime implicants
The repeated terms should be eliminated (--10 in the
column 3)
The seven prime implicants:(1,5), (1,9), (5,7), (6,7),
(9,11), (10,11), (2,6,10,14)
This is not a minimal set of prime implicants
The next stage is to determine the minimal set of prime
implicants
Selection of minimal set of implicants
Determine essential prime implicants
These are the minterms not covered by any other prime
implicant Identified by columns that have only one asterisk
Columns 2 and 14 have only one asterisk each
The associated row, CD
/
, is an essential prime implicant.
CD
/
is selected as a member of the minimal set (mark it by an
asterisk)
Remove the corresponding columns, 2, 6, 10, 14, from the prime
implicant table
A new table is prepared.
Selection of minimal set of
implicants (2)
Dominating Prime Implicants
Identified by the rows that have more asterisks than
others
Choose Row A
/
BD
Includes the minterm 7, which is the only one included in
the row represented by A
/
BC
A
/
BD is dominant implicant over A
/
BC
A
/
BC can be eliminated
Mark A
/
BD by an asterisk
Check off the columns 5 and 7
Dominating Prime Implicants (2)
Choose AB
/
D
Dominates over the row AB
/
C
Mark the row AB
/
D by an asterisk
Eliminate the row AB
/
C
Check off columns 9 and 11
Select A
/
C
/
D
Dominates over B
/
C
/
D.
B
/
C
/
D also dominates over A
/
C
/
D
Either B
/
C
/
D or A
/
C
/
D can be chosen as the dominant
prime implicant
Minimal SOP expression
If A
/
C
/
D is retained as the dominant prime implicant
F = CD
/
+ A
/
C
/
D + A
/
BD + AB
/
D
If B/C/D is chosen as the dominant prime implicant
F = CD
/
+ B
/
C
/
D + A
/
BD + AB
/
D
The minimal expression is not unique
Types of implicant tables
Cyclic prime implicant table
Semi-cyclic prime implicant table
A prime implicant table is cyclic if
it does not have any essential implicants which implies
(at least two asterisks in every column)
there are no dominating implicants (same number of
asterisks in every row
Example: Cyclic prime implicants
F = S (0,1,3,4,7,12,14,15)
Example: Possible Prime Implicants
a = A
/
B
/
C
/
(0,1) e = ABC (14,15)
b = A
/
B
/
D (1,3) f = ABD
/
(12,14)
c = A
/
CD (3,7) g = BC
/
D
/
(4,12)
d = BCD (7,15) h = A
/
C
/
D
/
(0,4)
Example: Prime implicant table
Process of simplification
All columns have two asterisks
There are no essential prime implicants.
Choose any one of the prime implicants to start with
Start with prime implicant a (mark with asterisk)
Delete corresponding columns, 0 and 1
Row c becomes dominant over row b, delete row b
Delete columns 3 and 7
Row e dominates row d, and row d can be eliminated
Delete columns 14 and 15
Choose row g it covers the remaining asterisks
associated with rows h and f
Example: Reduced Prime Implicants
Table
c
d
e
I
g
h
*
(3,7)
(7,15)
(14,15)
(12,14)
(4,12)
(0,4)
7 3 4 12 14 15
x x
x x
x x
x x
x
x
x
(a)
e
I
g
h
(14,15)
(12,14)
(4,12)
(0,4)
4 12 14 15
x
x
x x
x x
x
(b)
*
*
Example: Simplified Expression
F = a + c + e + g
= A
/
B
/
C
/
+ A
/
CD + ABC + BC
/
D
/
The K-map of the simplified function
Semi-cyclic prime implicant table
The number of minterms covered by each prime
implicant is identical in cyclic function
Not necessarily true in a semi-cyclic function
Example: Semi-cyclic Prime Implicant
Table (Function of 5 variables)
x
(0,2,8,10)
(0,2,16,18)
(8,9,10,11)
(16,17,18,19)
(11,15)
(15,31)
(23,31)
(19,23)
(17,25)
(25,9)
x
a
b
c
e
d
g
h
i
j
k
0 2
8 9 10 11 15 16 17 18 19 23 25 31
x
x x x x
x x
x x x x
x x x x
x x
x x
x x
x x
x x
x
Example: Semi-cyclic Prime Implicant
Table (Function of 5 variables) (2)
Minimised Function
F = a + c + d + e + h + j
or F = a + c + d + g + h + j
or F = a + c + d + g + j + i
or F = a + c + d + g + i + k
Simplification of Incompletely Specified
Functions
Do the initial tabulation including the dont-cares
Construct the prime implicant table
Columns associated with dont-cares need not be
included
Further simplification is similar to that for completely
specified functions
Example
F(A,B,C,D,E) =(1,4,6,10,20,22,24,26) +
d(0,11,16,27)
Pay attention to the dont-care terms
Mark the combinations among themselves (d)
Primary Implicant Table
-0-00 (0,4,16,20)
-0-00 (0,16,4,20)
----------------------
-01-0 (4,6,20,22)
-01-0 (4,20,6,22)
-------------------------
-101- (10,26,11,27)
-101- (10,11,26,27)
0000- (0,1)
00-00 (0,4)
-0000 (0,16) (d)
--------------------
001-0 (4, 6)
-0100 (4,20)
10-00 (16,20)
1-000 (16,24)
---------------------
-0110 (6,22)
-1010 (10,26)
0101- (10,11)
101-0 (20,22)
110-0 (24,26)
----------------------
1101- (26,27)
-1011 (11,27)
0
------------
1
4
16
------------
6
10
20
24
-----------
22
26
11
----------
27
00000 (d)
--------------
00001
00100
10000 (d)
---------------
00110
01010
10100
11000
--------------
10110
11010
01011 (d)
---------------
11011 (d)
Prime Implicant Table
a
b
c
d
e
g
x
(0,1)
(16,24)
(24,26)
(0,4,6,23)
(4,6,20,22)
(10,11,26,27)
1 4 6 10 20 22 24 26
x
x x
x x
x x x x
x x
Dont-cares are not included
Minimal expression
F(A,B,C,D,E) = a + c + e + g
= A
/
B
/
C
/
D
/
+ ABC
/
E
/
+ B
/
CE
/
+ BC
/
D

Qui ne- McCl usk ey Met hod of Mi ni mi zat i on
Karnaugh Map provides a good met hod of minimizing a logic funct ion. However, it depends
on our abilit y t o observe appropriat e pat t erns and ident ify t he necessary implicant s. I f t he
number of variables increases beyond five, K- map or it s variant Var iable Ent ered Map can
become very messy and t here is every possibilit y of commit t ing a mist ake. What we
require is a met hod t hat is more suit able for implement at ion on a comput er, even if it is
inconvenient for paper- and- pencil procedures. The concept of t abular minimisat ion was
originally formulat ed by Quine in 1952. This met hod was lat er improved upon by
McClusky in 1956, hence t he name Quine- McClusky.
This Learning Unit is concerned wit h t he Quine- McClusky met hod of minimisat ion. This
met hod is t edious, t ime- consuming and subj ect t o error when perfor med by hand. But it is
bet t er suit ed t o implement at ion on a digit al comput er.
Pr i nci pl e of Qui ne- McCl usk y Met hod
The Quine- McClusky met hod is a t wo st age simplificat ion process.
Generat e prime implicant s of t he given Boolean funct ion by a special t abulat ion
process.
Det ermine t he minimal set of implicant s is det ermined from t he set of implicant s
generat ed in t he first st age.
The t abulat ion process st art s wit h a list ing of t he specified mint erms for t he 1s ( or 0s)
of a funct ion and dont - cares ( t he unspecified mint erms) in a part icular format . All t he
prime implicant s are generat ed from t hem using t he simple logical adj acency t heorem,
namely, AB
/
+ AB = A. The main feat ure of t his st age is t hat we work wit h t he equivalent
binary number of t he product t erms. For example in a four variable case, t he mint erms
A
/
BCD
/
and A
/
BC
/
D
/
are ent ered as 0110 and 0100. As t he t wo logically adj acent
mint erms A
/
BCD
/
and A
/
BC
/
D
/
can be combined t o form a product t erm A
/
BD
/
, t he t wo
binary t erms 0110 and 0100 are combined t o form a t erm represent ed as "01- 0" , where -
( dash) indicat es t he posit ion where t he combinat ion t ook place.
St age t wo involves creat ing a prime implicant t able. This t able provides a means of
ident ifying, by a special procedure, t he smallest number of prime implicant s t hat represent s
t he original Boolean funct ion. The select ed prime implicant s are combined t o form t he
simplified expression in t he SOP form. While we confine our discussion t o t he creat ion of
minimal SOP expression of a Boolean funct ion in t he canonical form, it is easy t o
ext end t he procedure t o funct ions t hat are given in t he st andard or any ot her forms.
Gener at i on of Pr i me I mpl i cant s
The process of generat ing prime implicant s is best present ed t hrough an example.
Ex ampl e 1: F = ( 1, 2, 5, 6, 7, 9, 10,11, 14)
2
All t he mint erms are t abulat ed as binary numbers in sect ionalised format , so t hat each
sect ion consist s of t he equivalent binary numbers cont aining t he same number of 1s, and
t he number of 1s in t he equivalent binary numbers of each sect ion is always more t han t hat
in it s previous sect ion. This process is illust rat ed in t he t able as below.
Sect ion Column 1
No. of 1s Binary
Decimal
1 1 0001
0010
1
2
2 2 0101
0110
1001
1010
5
6
9
10
3 3 0111
1011
1110
7
11
14

The next st ep is t o look for all possible combinat ions bet ween t he equivalent binary
numbers in t he adj acent sect ions by comparing every binary number in each sect ion wit h
every binary number in t he next sect ion. The combinat ion of t wo t erms in t he adj acent
sect ions is possible only if t he t wo numbers differ from each ot her wit h respect t o only one
bit . For example 0001 ( 1) in sect ion 1 can be combined wit h 0101 ( 5) in sect ion 2 t o result
in 0- 01 ( 1, 5) . Not ice t hat combinat ions cannot occur among t he numbers belonging t o t he
same sect ion. The result s of such combinat ions are ent ered int o anot her column,
sequent ially along wit h t heir decimal equivalent s indicat ing t he binary equivalent s from
which t he result of combinat ion came, like ( 1, 5) as ment ioned above. The second column
also will get sect ionalised based on t he number of 1s. The ent ries of one sect ion in t he
second column can again be combined t oget her wit h ent ries in t he next sect ion, in a
similar manner. These combinat ions are illust rat ed in t he Table below
Sect ion Column 1
No. of 1s Binary
Decimal
Column 2 Column 3
1 1 0001 9 1
0010 9 2
2 2 0101 9 5
0110 9 6
1001 9 9
1010 9 10
3 3 0111 9 7
1011 9 11
1110 9 14
1- 01 ( 1, 5)
- 001 ( 1, 9)
0- 10 ( 2, 6) 9
- 010 ( 2, 10) 9

01- 1 ( 5, 7)
011- ( 6, 7)
- 110 ( 6, 14) 9
10- 1 ( 9, 11)
101- ( 10, 11)
1- 10 ( 10, 14) 9
- - 10 ( 2, 6, 10, 14)
- - 10 ( 2, 10, 6, 14)

All t he ent ries in t he column which are paired wit h ent ries in t he next sect ion are
checked off. Column 2 is again sect ionalised wit h respect t t he number of 1s. Column 3

is generat ed by pairing off ent ries in t he first sect ion of t he column 2 wit h t hose it ems in
t he second sect ion. I n principle t his pair ing could cont inue unt il no furt her combinat ions
can t ake place. All t hose ent ries t hat are paired can be checked off. I t may be not ed t hat
combinat ion of ent ries in column 2 can only t ake place if t he corresponding ent ries have t he
dashes at t he same place. This r ule is applicable for generat ing all ot her columns as well.
Aft er t he t abulat ion is complet ed, all t hose t erms which are not checked off const it ut e t he
set of prime implicant s of t he given funct ion. The repeat ed t erms, like - - 10 in t he column
3, should be eliminat ed. Therefore, from t he above t abulat ion procedure, we obt ain
seven prime implicant s ( denot ed by t heir decimal equivalent s) as ( 1, 5) , ( 1, 9) , ( 5, 7) ,
( 6, 7) , ( 9, 11) , ( 10, 11) , ( 2, 6, 10, 14) . The next st age is t o det ermine t he minimal set of
prime implicant s.
Det er mi nat i on of t he Mi ni mal Set of Pr i me I mpl i cant s
The prime implicant s generat ed t hrough t he t abular met hod do not const it ut e t he minimal
set . The prime implicant s are represent ed in so called "prime implicant t able". Each column
in t he t able represent s a decimal equivalent of t he mint erm. A row is placed for each prime
implicant wit h it s corresponding product appearing t o t he left and t he decimal group t o t he
right side. Ast erisks are ent ered at t hose int ersect ions where t he columns of binary
equivalent s int ersect t he row t hat covers t hem. The prime implicant t able for t he
funct ion under considerat ion is shown in t he figure.

I n t he select ion of minimal set of implicant s, similar t o t hat in a K- map, essent ial implicant s
should be det ermined first . An essent ial prime implicant in a prime implicant t able is
one t hat covers ( at least one) mint erms which are not covered by any ot her prime
implicant . This can be done by looking for t hat column t hat has only one ast erisk. For
example, t he columns 2 and 14 have only one ast erisk each. The associat ed row,
indicat ed by t he prime implicant CD
/
, is an essent ial pr ime implicant . CD
/
is select ed as a
4
member of t he minimal set ( mark t hat row by an ast erisk) . The corr esponding columns,
namely 2, 6, 10, 14, are also removed from t he prime implicant t able, and a new
t able is const ruct ion as shown in t he figure.

We t hen select dominat ing prime implicant s, which are t he rows t hat have more ast erisks
t han ot hers. For example, t he row A
/
BD includes t he mint erm 7, which is t he only one
included in t he row represent ed by A
/
BC. A
/
BD is dominant implicant over A
/
BC, and hence
A
/
BC can be eliminat ed. Mark A
/
BD by an ast erisk and check off t he column 5 and 7.
We t hen choose AB
/
D as t he dominat ing row over t he row represent ed by AB
/
C.
Consequent ly, we mark t he row AB
/
D by an ast erisk, and eliminat e t he row AB
/
C and t he
columns 9 and 11 by checking t hem off.
Similarly, we select A
/
C
/
D as t he dominat ing one over B
/
C
/
D. However, B
/
C
/
D can also be
chosen as t he dominat ing pr ime implicant and eliminat e t he implicant A
/
C
/
D.
Ret aining A
/
C
/
D as t he dominant prime implicant t he minimal set of pr ime implicant s is
{ CD
/
, A
/
C
/
D, A
/
BD and AB
/
D) . The corresponding minimal SOP expression for t he Boolean
funct ion is:
F = CD
/
+ A
/
C
/
D + A
/
BD + AB
/
D
I f we choose B
/
C
/
D inst ead of A
/
C
/
D, t hen t he minimal SOP expression for t he Boolean
funct ion is:
F = CD
/
+ B
/
C
/
D + A
/
BD + AB
/
D
This indicat es t hat if t he select ion of t he minimal set of prime implicant s is not unique,
t hen t he minimal expression is also not unique.
There are t wo t ypes of implicant t ables t hat have some special propert ies. One is referred
t o as cyclic prime implicant t able, and t he ot her as semi- cyclic prime implicant t able. A
prime implicant t able is considered t o be cyclic if

1. it does not have any essent ial implicant s which implies t hat t here are at least t wo
ast erisks in every column, and
2. There are no dominat ing implicant s, which implies t hat t here are same number of
ast erisks in every row.
Ex ampl e 2: A Boolean funct ion wit h a cyclic prime implicant t able is shown in t he figure 3.
The funct ion is given by
F = ( 0, 1, 3, 4, 7, 12, 14, 15)
All possible prime implicant s of t he funct ion ar e:
a = A
/
B
/
C
/
( 0, 1) e = ABC ( 14, 15)
b = A
/
B
/
D ( 1, 3) f = ABD
/
( 12, 14)
c = A
/
CD ( 3, 7) g = BC
/
D
/
( 4, 12)
d = BCD ( 7, 15) h = A
/
C
/
D
/
( 0, 4)

As it may be not iced from t he prime implicant t able in t he figure t hat all columns have t wo
ast erisks and t here are no essent ial prime implicant s. I n such a case we can choose any
one of t he prime implicant s t o st art wit h. I f we st art wit h prime implicant a, it can be
marked wit h ast erisk and t he cor responding columns, 0 and 1, can be delet ed from t he
t able. Aft er t heir removal, row c becomes dominant over row b, so t hat row c is select ed
and hence row b is can be eliminat ed. The columns 3 and 7 can now be delet ed. We
observe t hen t hat t he row e dominat es row d, and r ow d can be eliminat ed. Select ion of
row e enables us t o delet e columns 14 and 15.

6
I f, fr om t he reduced prime implicant t able shown in t he figure, we choose row g it covers
t he remaining ast erisks associat ed wit h rows h and f. That covers t he ent ire prime
implicant t able. The minimal set for t he Boolean funct ion is given by:

F = a + c + e + g
= A' B' C' + A' CD + ABC + BC' D'
The K- map of t he simplified funct ion is shown in t he following figure

A semi- cyclic prime implicant t able differs from a cyclic prime implicant t able in one respect .
I n t he cyclic case t he number of mint erms covered by each prime implicant is ident ical. I n
a semi- cyclic funct ion t his is not necessarily t rue.

Ex ampl e 3: Consider a semi- cyclic prime implicant t able of a five variable Boolean funct ion
shown in t he figure.

Examinat ion of t he prime- implicant t able reveals t hat rows a, b, c and d cont ain four
mint erms each. The remaining r ows in t he t able cont ain t wo ast erisks each. Several
minimal set s of prime implicant s can be select ed. Based on t he procedures present ed
t hrough t he earlier examples, we find t he following candidat es for t he minimal set :
F = a + c + d + e + h + j
or F = a + c + d + g + h + j
or F = a + c + d + g + j + i
or F = a + c + d + g + i + k
Based on t he examples present ed we may summarise t he procedure for det erminat ion of
t he minimal set of implicant s:
1. Find, if any, all t he essent ial pr ime implicant s, mark t hem wit h * , and remove t he
corresponding rows and columns covered by t hem from t he prime implicant t able.
2. Find, if any, all t he dominat ing pr ime implicant s, and remove all dominat ed prime
implicant s from t he t able marking t he dominat ing implicant s wit h * s. Remove t he
corresponding rows and columns covered by t he dominat ing implicant s.
3. For cyclic or semi- cyclic prime implicant t able, select any one prime implicant as t he
dominat ing one, and follow t he procedure unt il t he t able is no longer cyclic or semi-
cyclic.
4. Aft er covering all t he columns, collect all t he * marked prime implicant s t oget her t o
form t he minimal set , and convert t hem t o form t he minimal expression for t he
funct ion.

8
Si mpl i f i cat i on of I ncompl et el y Speci f i ed f unct i ons
The simplificat ion procedure for complet ely specified funct ions pr esent ed in t he earlier
sect ions can easily be ext ended t o incomplet ely specified funct ions. The init ial
t abulat ion is drawn up including t he dont - cares. However, when t he prime implicant t able is
const ruct ed, columns associat ed wit h dont - car es need not be included because t hey do not
necessarily have t o be covered. The remaining part of t he simplificat ion is similar t o t hat
for complet ely specified funct ions.
Ex ampl e 4: Simplify t he following funct ion:
F( A, B, C,D, E) = ( 1, 4, 6, 10, 20, 22, 24, 26) + d( 0, 11, 16, 27)
Tabulat ion of t he implicant s
00000 ( d)

00001
00100
10000 ( d)

00110
01010
10100
11000

10110
11010
01011 ( d)

11011 ( d)

0 3

1 3
4 3
16 3

6 3
10 3
20 3
24 3

22 3
26 3
11 3

27 3
0000- ( 0, 1)
00- 00 ( 0, 4) 3
- 0000 ( 0, 16) ( d)

001- 0 ( 4, 6) 3
- 0100 ( 4, 20) 3
10- 00 ( 16, 20) 3
1- 000 ( 16, 24) 3

- 0110 ( 6, 22) 3
- 1010 ( 10, 26) 3
0101- ( 10, 11) 3
101- 0 ( 20, 22) 3
110- 0 ( 24, 26)

1101- ( 26, 27) 3
- 1011 ( 11, 27) 3

- 0- 00 ( 0, 4, 16, 20)
- 0- 00 ( 0, 16, 4, 20)

- 01- 0 ( 4, 6, 20, 22)
- 01- 0 ( 4, 20, 6, 22)

- 101- ( 10, 26, 11, 27)
- 101- ( 10, 11, 26, 27)

Pay at t ent ion t o t he dont - care t erms as well as t o t he combinat ions among t hemselves, by
marking t hem wit h ( d) .
Six binary equivalent s are obt ained from t he procedure. These are 0000- ( 0, 1) , 1- 000
( 16, 24) , 110- 0 ( 24, 26) , - 0- 00 ( 0, 4, 16, 20) , - 01- 0 ( 4, 6, 20, 22) and - 101- ( 10, 11, 26, 27)
and t hey correspond t o t he following pr ime implicant s:
a = A
/
B
/
C
/
D
/
/ b = AC
/
D
/
E
/
c = ABC
/
E
/

d = B
/
D
/
E
/
e = B
/
CE
/
g = BC
/
D
The prime implicant t able is plot t ed as shown in t he figure.

I t may be not ed t hat t he dont - cares are not included.
The minimal expression is given by:
F( A, B, C,D, E) = a + c + e + g
= A' B' C' D' + ABC' E' + B' CE' + BC' D

Digital Electronics Module 3
Logic Families: Introduction
N.J. Rao
December 2006 N.J.Rao M3L1 2
Logic families
A logic family is characterized by
Its circuit configuration
Its technology
Specific optimization of a set of desirable properties
Many logic families were introduced into the market since
the introduction of integrated circuits in 1960s.
Some of the IC families had very short life spans.
Standard TTL family which dominated the IC market got
superseded by the Low Power Schottky family.
Necessary to be aware of the evolving technologies
Features of a Logic Family
Logic flexibility
Availability of complex functions
High noise immunity
Wide operating temperature range
Loading
Speed
Low power dissipation
Lack of generated noise
Input and output structures
Packaging
Low cost
Logic Flexibility
It is a measure of the capability and versatility or the
amount of work or variety of uses that can be obtained
from a logic family.
Factors that enhance the logic flexibility
Wired-logic capability
Asserted/ not-asserted outputs
Driving capability
I/O interfacing
Driving other logic families
Multiple gates
Complex Functions
A complex function represents a grouping of basic gates
requiring a relatively high level of integration.
As complexity increases, the number of input/output pins
also increases - but usually at a decreasing rate.
High pin count gives the benefit of decreasing assembly
costs per gate while increasing the reliability per gate.
The complexity is also measured in terms of gates per
chip.
Noise Immunity
High immunity to noise is desired to prevent the occurrence
of false logic signals in a system.
Common sources of noise:
Variations of the dc supply voltage,
Ground noise
Excessive coupling between signal leads
Magnetically coupled voltages from adjacent lines,
External sources (relays, circuit breakers, and power line
transients)
Radiated signals
Measures of Noise Immunity
Voltage noise immunity (noise margin) is the amount of
voltage that can be added algebraically to the worst-case
output level before a worst-case gate tied to that output
will begin to switch.
Noise immunity is specified in terms of millivolts or volts
DC Noise Margin
It is a measure of its noise immunity, a gates ability to
withstand dc input signal variations.
V
IL
: Low level input voltage
V
IH
: High level input voltage
V
OL
: Low level output voltage
V
OH
High level output voltage
Voltage levels associated with logic High and logic Low
levels are not single values but a band of values.
DC Noise Margin (2)
A gate may accept an input signal in the range of 0.0 V to
0.8 V as logic Low while it produces at its output a Low
voltage of 0.4 V under worst loading and voltage supply
conditions.
DC margin is considered to be 0.4 V (0.8 - 0.4 = 0.4 V)
The dc noise margins are defined as
Low level dc noise margin: V
ILmax
- V
OLmax
High level dc noise margin: V
OHmin
- V
IHmin
DC Noise Margin (3)
AC Noise Margin
It refers to the immunity of a gate to noise of very short
durations.
Amplitude and duration of the noise signals become
important.
The noise signal must contain enough energy to effect a
change in the state of the circuit.
AC noise margins are higher than dc noise margins.
AC Noise Margin (2)
The ability of a logic element to operate in a noisy
environment depends on
Built-in operating margins
Time required for the device to react
The ease with which a noise voltage is developed
Operating Temperature Range
For commercial and industrial needs, temperatures
usually range from 0
o
or -30
o
C to 55
o
, 70
o
or 85
o
C
The military has an universal requirement for operability
from -55
o
C to 125
o
C.
Advantages of a wide temperature specification are
offset by the increased cost
Loading
The output of a logic gate may be connected to the
inputs of several other similar gates
The fan out of a gate is the maximum number of inputs
of the same IC family that the gate can drive while
maintaining its output levels within specified limits.
Loading
The input and output loading parameters are normalized, with
regard to TTL devices
1 TTL Unit Load (U.L.) = 40 A in the High state (Logic 1)
1 TTL Unit Load (U.L.) = -1.6 mA in the Low state (Logic 0)
The output of 74LS00 will sink 8.0 mA in Low state and source
400 A in the High state.
The normalized output Low drive factor is: (8.0/1.6) = 5 U.L.
Output High drive factor is: (400 A/40 A) = 10 U.L.
Speed
The shorter the propagation delay, the higher the speed
of the circuit
Propagation delay of a gate:
time interval between the application of an input pulse
and the occurrence of the resulting output pulse.
Propagation Delays
Two propagation delays associated with a logic gate:
t
PHL
: The time between a specified reference point on the
input pulse and a corresponding reference point on the
output pulse, with the output changing from the High
level to the Low level.
t
PLH
: The time between specified reference point on the
input pulse and a corresponding reference point on the
output pulse, with the output changing from the Low level
to the High level.
Speed
The reference points are chosen as the 50% of the leading
and trailing edges of the wave forms, or the threshold
voltage (where the input and output voltages of the gate are
equal) point.
A
B
A
B
t
PHL
t
PLH
Power Dissipation
Low power dissipation is desired in large systems as it
leads to
Lower cooling costs
Lower power supply and distribution costs,
Reduction in mechanical design problems
Decrease in power dissipation on a per-gate basis with
higher integration levels
Steady state dissipation
DC supply voltage V
CC
x Average supply current I
CC
Value of I
CC
for a Low gate output is higher than for a
High output
Manufacturer's data sheet usually specifies both these
values as I
CCL
and I
CCH
.
The average I
CC
is then determined based on a 50%
duty cycle operation of the gate
Dissipation during transitions
The supply current drawn is generally very different
during the transition times
More number of active devices come into operation, and
parasitic capacitors will have to be charged and
discharged.
Power dissipation increases linearly as a function of the
frequency of switching.
Dissipation during transitions (2)
Speed-power product (SPP) is specified by the
manufacturer
SSP is specified in terms of pico Joules (symbolized
by pJ)
SPP of a 74HC CMOS gate at 100 KHz is
SPP = (8ns) x (0.17 mW) = 1.36 pJ.
Generated Noise
Switching transients either on power line or signal line
can be very serious sources of noise.
Care has to be taken to design the power, ground and
signal interconnections.
All the power supply leads in a system must be
bypassed.
Supply distribution is less expensive if the circuits
generate less noise.
Input and output structures
Effective interfacing both at the input and output are
needed
Interfacing at the input requires facility
To accept different voltage levels for the two logic states
To accept signals with rise and fall times very different
from those of the signals associated with that logic family
At the output we require
Larger current driving capability
Facility to increase the voltages associated with the two
logic levels
Ability to tie the outputs of gates to have wired logic
operations
Interfacing at the inputs and outputs
Interfacing the slow varying signals is achieved through
Schmitt triggers.
Voltage levels of the output signals can be increased by
providing open-collector configurations. Open-collector
configurations also permit us to achieve wired-logic
operations
The outputs of gates can be tied together by having
tristate outputs.
Schmitt Trigger Inputs
When a slow changing signal superposed with noise
is applied to gate
V
T
V
V
T
V
T
+
-
OUT
High
Low
a
b
OUT
High
Low
c
Three-State Outputs
Logic outputs have two normal states; Low and High
It is desirable to have another electrical state in which
the output of the circuit offers very high impedance, high-
impedance, Hi-z or floating state
In this state, the circuit is effectively disconnected at its
output, except for a small leakage current.
Three states: logic 0, logic 1, and Hi-z.
An output with three possible states is called tri-state
output.
Three-State Outputs (2)
Devices with three state outputs, should have an extra
input, called as output enable (OE) for placing a device
in low-impedance or high-impedance states.
The outputs of devices which can have three states can
be tied together, to create a three-state bus.
The control circuitry must enable that at any given time
only one output is enabled while all other outputs are
kept in high-z state.
Open-Collector (or Drain) Outputs
An IC device has a pull-up resistor at its output transistor
Such circuits prevent us from tying the outputs of two
such devices together.
If the internal pull-up elements are removed, then it allows
one to
tie up the outputs of more than one device together
connect external pull-up resistor to increase the output
voltage swing.
Devices with open-collector (open-drain) outputs are very
useful for
Creating wired logic operations, or
Interfacing loads which are incompatible with the
electrical characteristics of the logic family.
Packaging
Initially most of the digital ICs were made available in
dual-in-line packages (DIP).
Commercial ICs come in plastic DIPs
Ceramic DIPs are used for operation over a larger
temperature range
Increasing integrations lead to a wide range of chip level
packages
Cost
Often the most important one, is the cost of a logic family.
It is not sufficient to compare the cost of logic families at
gate level.
The total system cost is decided by
Cost of ICs
Cost printed wiring board
on which the ICs are
mounted
Assembly of circuit board
Programming the
programmable devices
etc.
Procurement
Testing
Power supply
Documentation
Storage
PROPERTI ES OF A LOGI C FAMI LY
Since t he int roduct ion of int egrat ed circuit s in 1960s, many logic families were
int roduced int o t he market . Each logic family is charact erised by
a circuit configurat ion
a part icular semiconduct or t echnology
a specific opt imisat ion of a set of desirable propert ies
Some of t he I C families had very short life spans. Wit h cont inuously changing
t echnologies, I Cs t hat were quit e popular suddenly become unat t ract ive and
uneconomical. For example St andard TTL family which dominat ed t he I C market
for a long period got superseded by t he Low Power Schot t ky family. A digit al
designer should not only have a good knowledge of t he exist ing digit al families but
should also be aware of t he t rends as well. The maj or requirement s and t he
desirable feat ures of a logic family are:
Logic flexibilit y
Availabilit y of complex funct ions
High noise immunit y
Wide operat ing t emperat ure range
Loading
Speed
Low power dissipat ion
Lack of generat ed noise
I nput and out put st ruct ures
Packaging
Low cost
Logi c Fl ex i bi l i t y
Logic flexibilit y is a measure of t he capabilit y and versat ilit y or t he amount of work
or variet y of uses t hat can be obt ained from a logic family, in ot her words, it is a
measure of t he ut ilit y of a logic family in meet ing various syst em needs. Fact ors
t hat enhance t he logic flexibilit y are wired- logic capabilit y, assert ed/ not - assert ed
out put s, line driving capabilit y, indicat or driving, I / O int erfacing, driving ot her logic
families and mult iple gat es.
Wired logic refers t o t he capabilit y of t ying t he out put s of gat es t oget her t o perform
addit ional logic wit hout ext ra hardware and component s. Frequent ly, assert ed/ not -
assert ed versions of a variable are required in a logic syst em. I f t he logic family has
gat es wit h not - assert ed out put s, use of invert ers can be avoided. I f t he circuit s can
drive non- st andard loads such as long signal lines, lamps and indicat or t ubes,
addit ional discret e circuit s can be avoided. The gat e count can be minimised in a
digit al syst em if AND, NAND, OR, NOR and EX- OR gat es are all available in t he
family. The logic families current ly popular, namely TTL, CMOS and t o a limit ed
ext ent ECL, in t he market have similar logic flexibilit y, and as such t his fact or does
not const it ut e a deciding issue in select ing a logic family.
Compl ex Funct i on
A complex funct ion may be described as a grouping of basic gat es requiring a
relat ively high level of int egrat ion. As complexit y increases, t he number of
input / out put pins also increases - but usually at a decreasing rat e. Gat e- t o- pin
rat ios t hat normally increase wit h complexit y give t he benefit of decreasing assembly
cost s per gat e while increasing t he reliabilit y per gat e. The complexit y is also
measured, at present , by t he number of gat es t hat can be offered in a
programmable logic device or programmable gat e array.
Noi se I mmuni t y
I n order t o prevent t he occurrence of false logic signals in a syst em, high immunit y
t o noise is desired. Common sources of noise in digit al circuit s are
Variat ions of t he dc supply volt age
Ground noise
Excessive coupling bet ween signal leads
Magnet ically coupled volt ages from adj acent lines
Ext ernal sources such as relays, circuit breakers, and power line t ransient s
I f t he noise immunit y is higher, t he number of precaut ions required t o prevent t he
false logic signals will also be less. This becomes an import ant advant age in t hose
areas, such as in indust rial logic cont rol syst ems t hat are subj ect t o high noise levels.
At present wit h increasing use of elect ronic cont rol syst ems even in household
appliances, t he ambient noise levels at homes have significant ly risen. Volt age noise
immunit y, or noise margin, is normally specified in t erms of millivolt s or volt s. The
noise immunit y is specified as t he amount of volt age t hat can be added algebraically
t o t he worst - case out put level before a worst - case gat e t ied t o t hat out put will begin
t o swit ch.
DC Noi se Mar gi n: The dc noise margin of a logic gat e is a measure of it s noise
immunit y, a gat es abilit y t o wit hst and dc input signal variat ions. The t erm dc noise
margin applies t o noise volt ages of relat ively long durat ion compared t o t he gat es
response t imes. The dc noise margin is defined in t erms of t he following volt age
levels associat ed wit h a gat e;
V
I L
: Low level input volt age
V
I H
: High level input volt age
V
OL
: Low level out put volt age
V
OH
: High level out put volt age
Volt age levels associat ed wit h logic High and logic Low levels are not single values
but a band of values.
For example, a gat e may accept an input signal in t he range of 0. 0 V t o 0. 8 V as
logic Low while it produces at it s out put a Low volt age of 0. 4 V under worst loading
and volt age supply condit ions.
I n such a sit uat ion 0. 4 V ( 0. 8 - 0. 4 = 0. 4 V) is considered t o be t he dc noise margin.
When t he out put of one gat e is connect ed t o t he input of anot her gat e, as t he out put
is limit ed t o 0. 4 V even if a noise volt age up t o 0. 4 is superimposed on it , t he second
gat e would accept it as logic Low signal.
The dc noise margins are defined as
Low level dc noise margin: V
I Lmax
- V
OLmax

High level dc noise margin: V
OHmin
- V
I Hmin
The noise margins and t he volt age levels associat ed wit h t he gat es can be
graphically shown as in t he figure.

V0H(min)
V IH(min)
VCC
VIL(max)
VIL(max)
GND
AC Noi se Mar gi n: The t erm ac noise margin refers t o t he noise immunit y of a gat e
t o noise of very short durat ions. I n short durat ion noise, bot h t he amplit ude and
durat ion of t he noise signals become import ant . The noise signal must cont ain
enough energy t o effect a change in t he st at e of t he circuit . Therefore, t he ac noise
margins are considerably higher t han dc noise margins.
The abilit y of a logic element t o operat e in a noisy environment involves more t han
t he dc and ac noise margins. To be a problem, an ext ernally generat ed noise pulse
must be received int o t he syst em and cause malfunct ion. The noise volt age must be
int roduced int o t he circuit by radiat ed or coupled means. The amount of noise power
required t o develop a given volt age is st rict ly a funct ion of t he circuit impedances.
Noise power must be t ransferred from t he noise source wit h some arbit rary
impedance, t hrough a coupling t o t he impedance of t he circuit under considerat ion.
The abilit y t o operat e in a noisy environment is, t hen, an int eract ion of t he built - in
operat ing margins, t he t ime required for t he device t o react , and t he ease wit h which
a noise volt age is developed. Therefore, t he noise rej ect ion capabilit ies of a logic
family represent a combinat ion of a number of circuit paramet ers.
Oper at i ng Temper at ur e Range
A wide operat ing range is always desired and is oft en a design requirement .
For commercial and indust rial needs, t emperat ures usually range from 0
o
C or - 30
o
C
t o 55
o
C, 70
o
C or 85
o
C.
The milit ary has a universal requirement for operabilit y from - 55
o
C t o 125
o
C.
I n most cases a logic line specified from - 55
o
C t o 125
o
C will exhibit bet t er
charact erist ics at room t emperat ure condit ions t han a line specified by commercial
requirement s. I t means performance of a logic circuit wit h regard t o fan out , noise
immunit y and t olerance t o power supply variat ions is usually bet t er, since t he circuit s
must st ill be wit hin specificat ions even when t he inherent degradat ion due t o
t emperat ure ext remes occurs. The advant ages of a wide t emperat ure specificat ion
are oft en offset by t he increased cost .
Loadi ng
I n digit al syst ems many digit al I Cs are int erconnect ed t o perform different funct ions.
The out put of a logic gat e may be connect ed t o t he input s of several ot her similar
gat es so t he load on t he driving gat e becomes an import ant fact or. The fanout of a
gat e is t he maximum number of input s of I Cs from t he same I C family t hat t he gat e
can drive while maint aining it s out put levels wit hin specified limit s. I n ot her words,
t he fanout specifies t he maximum loading t hat a given gat e is capable of handling.
The input and out put loading paramet ers are generally normalised, wit h regard t o
TTL devices, t o t he following values.
1 TTL Unit Load ( U. L. ) = 40 A in t he High st at e ( Logic 1 )
1 TTL Unit Load ( U. L. ) = - 1. 6 mA in t he Low st at e ( Logic 0 )
For example t he out put of 74LS00 will sink 8. 0 mA in Low st at e and source 400 A in
t he High st at e.
The normalised out put Low drive fact or is:
( 8. 0/ 1. 6) = 5 U. L.
The out put High drive fact or is:
( 400/ 40) = 10 U. L.

Speed
Propagat ion delay is a very import ant charact erist ic of logic circuit s because it limit s
t he speed ( frequency) at which t hey can operat e. The short er t he propagat ion
delay, t he higher t he speed of t he circuit .
The propagat ion delay of a gat e is basically t he t ime int erval bet ween t he applicat ion
of an input pulse and t he occurrence of t he result ing out put pulse.
There are t wo propagat ion delays associat ed wit h a logic gat e:
1. t
PHL
: The t ime bet ween a specified reference point on t he input pulse and a
corresponding reference point on t he out put pulse, wit h t he out put changing
from t he High level t o t he Low level.
2. t
PLH
: The t ime bet ween specified reference point on t he input pulse and a
corresponding reference point on t he out put pulse, wit h t he out put changing
from t he Low level t o t he High level.
The reference point s on t he wave forms wit h respect t o which t he t ime delays are
measured can be chosen as
The 50% of t he leading and t railing edges of t he wave forms
or
The t hreshold volt age ( where t he input and out put volt ages of t he gat e are equal)
point .
These propagat ion delays are illust rat ed in t he figure for bot h invert ed and non-
invert ed out put s, wit h 50% point t aken as t he reference.

Pow er Di ssi pat i on
Logic wit h low power dissipat ion is desired in large syst ems because it lowers cooling
cost s, and power supply and dist ribut ion cost s, t hereby reducing mechanical design
problems as well. I n an air- borne or sat ellit e applicat ion, power dissipat ion may be
t he most crit ical paramet er because of power- source limit at ions. As chip complexit y
and packaging densit y cont inue t o increase, power dissipat ion will decrease on a per-
gat e basis, but will increase per- chip basis. This is dict at ed by heat dissipat ion
rest rict ion arising from syst em design and maximum allowable semiconduct or
j unct ion t emperat ures.
The power dissipat ion of a logic gat e is
dc supply volt age V
CC
x t he average supply current I
CC

Normally, t he value of I
CC
for a Low gat e out put is higher t han for a High out put . The
manufact urer' s dat a sheet usually specifies bot h t hese values as I
CCL
and I
CCH
. The
average I
CC
is t hen det ermined based on a 50% dut y cycle operat ion of t he gat e.
The supply current drawn is generally very different during t he t ransit ion t ime t han
during t he st eady st at e operat ion in logic High or Low st at es. During t he t ransit ion
t imes more number of act ive devices is likely t o come int o operat ion, and parasit ic
capacit ors will have t o be charged and discharged. Therefore, t here is more
dissipat ion every t ime a logic circuit swit ches it s st at e. I t also means t hat t he power
dissipat ion increases linearly as a funct ion of t he frequency of swit ching. A gat e t hat
operat es at higher frequency will dissipat e more power t han t he same gat e operat ing
at a lower frequency. This phenomenon will have a significant effect on t he design of
high frequency circuit s.
A
B
A
B
t
PHL
t
PLH
I n view of t his anot her paramet er known as speed- power product ( SPP) is specified
by t he manufact urer as a measure of t he performance of a logic circuit based on t he
product of t he propagat ion delay t ime wit h t he power dissipat ion at a specified
frequency.
The speed- power product is specified in t erms of pico Joules, symbolised by pJ.
For example, t he SPP of a 74HC CMOS gat e at 100 KHz is
SPP = ( 8ns) x ( 0. 17 mW) = 1. 36 pJ.
Gener at ed Noi se
The swit ching t ransient s eit her on power line or signal line can be very serious
sources of noise. They can conduct and radiat e t hrough different channels and
influence t he funct ioning of t he near by circuit s or syst ems. Therefore, t he lack of
generat ed noise is an import ant requirement of a logic family. When t he swit ching
noise is significant , special care has t o be t aken t o design t he power, ground and
signal int erconnect ions.
All t he power supply leads in a syst em must be bypassed.
Power supply and ground dist ribut ion has t o be carefully designed.
Supply dist ribut ion is less expensive if t he logic family generat es minimal noise.
Also, t he maximum line lengt hs in t he back plane and wiring on t he print ed wiring
board are funct ions of cross t alk generat ed by t he logic family. A logic family t hat
draws const ant current in bot h logic Low and High st at es, and does not change
supply current when swit ching st at es will generat e less noise.
I nput and out put St r uct ur es
A logic family should provide feat ures for effect ive int erfacing bot h at t he input and
out put . I nt erfacing at t he input requires facilit y t o accept different volt age levels for
t he t wo logic st at es, and t o accept signals wit h rise and fall t imes very different from
t hose of t he signals associat ed wit h t hat logic family. At t he out put we require larger
current driving capabilit y, facilit y t o increase t he volt ages associat ed wit h t he t wo
logic levels, and t he abilit y t o t ie t he out put s of gat es t o have wired logic operat ions.
I nt erfacing t he slow varying signals ( signals wit h rise and fall t imes great er t han one
microsecond) is achieved t hrough Schmit t t riggers. Volt age levels of t he out put
signals can be increased by providing open- collect or ( or open- drain) configurat ions.
Such open- collect or ( open- drain) configurat ions also permit us t o achieve wired- logic
operat ions. The out put s of gat es can be t ied t oget her by having t rist at e out put s.
Schmi t t Tr i gger I nput s: When a slow changing signal superposed wit h noise is
applied t o a gat e which has a single t hreshold V
T
, t here is a possibilit y of t he out put
changing several t imes during signal t ransit ion period, as shown in t he figure ( b) .
Clearly, such a response is not accept able. When t he input signal t o a gat e has long
t ransit ion t imes, t he gat e is likely t o st ay in t he linear region of it s operat ion for a
long period. During t his period t he gat e is likely t o get int o oscillat ions because of
t he parasit ics associat ed wit h t he circuit , which are not desirable. The problems
associat ed wit h slow changing signals and t he superposed noise can be solved if t he
gat e has Schmit t t rigger t ype of input .

V
T
V
V
T
V
T
+
-
OUT
High
Low
a
b
OUT
High
Low
c

A Schmit t t rigger is a special circuit t hat uses feedback int ernally t o shift t he
swit ching t hreshold depending on whet her t he input is changing from Low t o High or
from High t o Low. For example, suppose t he input of a Schmit t - t rigger invert er is
init ially at 0 V ( solid Low) and t he out put is High close t o t he V
CC
( or V
DD
) . I f t he
input volt age is increased, t he out put will not go Low unt il t he input volt age reaches
a t hreshold volt age, V
T
. Any value of t he input volt age above t his t hreshold will
make t he out put t o remain Low. The out put of a Schmit t gat e for a slow changing
noisy signal is shown in t he figure ( c) . Every logic family should have a few gat es
which provide for Schmit t input s t o effect ively int erface wit h real world signals.
Thr ee- St at e Out put s: Logic out put s have t wo normal st at es, Low and High,
corresponding t o logic values 0 and 1. I t is desirable t o have anot her elect rical
st at e, not a logic st at e at all, in which t he out put of t he circuit offers very high
impedance. I n t his st at e, it is equivalent t o disconnect ing t he circuit at it s out put ,
except for a small leakage current . Such a st at e is called high- impedance, Hi- z or
float ing st at e. Thus we have an out put t hat could go int o one of t he t hree st at es:
logic 0, logic 1 and Hi- z. An out put wit h t hree possible st at es is called t rist at e
out put .
Devices t hat have t hree st at e out put s, should have an ext ra input signal, t hat can be
called as out put enable ( OE) for placing t he device eit her in low- impedance or
high- impedance st at es. The out put s of devices which can have t hree st at es can be
t ied t oget her, t o creat e a t hree- st at e bus. The cont rol circuit ry must enable t hat at
any given t ime only one out put is enabled while all ot her out put s are kept in Hi- z
st at e.
Open- Col l ect or ( or Dr ai n) Out put s: The collect or t erminal of a t ransist or ( or t he
drain t erminal of a MOSFET) is normally connect ed in a logic device t o a pull- up
resist or or a special pull- up circuit . Such circuit s prevent us from t ying t he out put s
of t wo such devices t oget her. I f t he int ernal pull- up element s are removed, t hen it
gives freedom t o t he designer t o t ie up t he out put s of more t han one device
t oget her, or t o connect ext ernal pull- up resist or t o increase t he out put volt age swing.
Devices wit h open- collect or ( open- drain) out put s are very useful for creat ing wired
logic operat ions or for int erfacing loads which are incompat ible wit h t he elect rical
charact erist ics of t he logic family. I t is, t herefore, desirable for a logic family t o have
devices, at least some, which have open- collect or ( or open- drain) out put s.
Pack agi ng
Unt il a few years ago most of t he digit al I Cs were made available in dual- in- line
packages ( DI P) . I f t he devices were t o be operat ed in commercial t emperat ure
range, t hey come in plast ic DI Ps, and if t hey are t o be used over a larger
t emperat ure range, t hey would be used in ceramic DI Ps. Wit h increasing
miniat urisat ion at syst ems level and int egrat ion at t he chip level t he number of
pins/ I C have been st eadily increasing. This increase in t he pin count led t o t he
int roduct ion of different packages for t he I Cs. Select ing an appropriat e package is
one of t he design decisions t odays digit al designer has t o make.

Cost
The last considerat ion, and oft en t he most import ant one, is t he cost of a given logic
family. The first approximat e cost comparison can be obt ained by pricing a common
funct ion such as a dual four- input or quad t wo- input gat e. But t he cost of a few
t ypes of gat es alone can not indicat e t he cost of t he t ot al syst em. The t ot al syst em
cost is decided not only by t he cost of I Cs but also by t he cost of
print ed wiring board on which t he I Cs are mount ed
assembly of circuit board
t est ing
programming t he programmable devices
power supply
document at ion
procurement
st orage
et c.
I n many inst ances t he cost of I Cs could become a less import ant component of t he
t ot al cost of t he syst em.
Concl udi ng Not e
The quest ion t hat arises aft er considering all t he desirable feat ures of a logic family
is why not design a family t hat best meet s t hese needs and t hen mass produce it
and drive t he cost s down? Unfort unat ely, t his can not be achieved as t here is no
universal logic family t hat a does a good j ob of meet ing all t he previously st at ed
needs. Silicon t echnology, t hough bet t er underst ood and st udied t han any ot her
solid- st at e t echnology, st ill has it s own limit at ions. Besides, t he demand for higher
and higher performance specificat ions cont inues t o grow.

El ect r i cal Char act er i st i cs of Schot t k y TTL Fami l y
Table gives t he worst case values for t he input and out put volt age levels in bot h t he
logic st at es.
TTL Families Milit ary( - 55 t o + 125
o
C) Commercial( 0t o 70
o
C)
V
I
V
I H
V
OL
V
OH
V
I L
V
I H
V
OL
V
OH

TTL St andard ( 54/ 74) 0. 8 2 0. 4 2. 4 0. 8 2 0. 4 2. 4 V
STTL Schot t ky ( 54/ 74S) 0. 8 2 0. 5 2. 5 0. 8 2 0. 5 2. 7 V
LSTTL Low- power Schot t ky
( 54/ 74LS)
0. 8 2 0. 5 2. 5 0. 8 2 0. 5 2. 7 V
ALSTTL

Advanced Low- power
Schot t ky ( 54/ 74ALS)
0. 8 2 0. 4 2. 5 0. 8 2 0. 5 2. 7 V
ASTTL Advanced Schot t ky
( 54/ 74AS)
0. 8 2 0. 5 2. 5 0. 8 2 0. 5 2. 7 V
FAST Fairchild Advanced
Schot t ky ( 54/ 74F)
0. 8 2 0. 5 2. 5 0. 8 2 0. 5 2. 5 V

The noise margins are:
dc noise margin in High st at e = V
OHmin
- V
I Hmin
= 0. 7 V
dc noise margin in Low st at e = V
I Lmax
- V
OLmax
= 0. 3 V
The noise margin levels are different in High and Low st at es and are shown in t he
following Table. These levels are lower in comparison t o t he noise levels of CMOS
circuit s.

TTL Families
Milit ary
( - 55 t o 125
o
C)
Commercial
( 0 t o 70
o
C)

Low NM High NM Low NM High NM
TTL St andard ( 54/ 74) 400 400 300 400 mV
STTL Schot t ky ( 54/ 74S) 300 500 300 700 mV
LSTTL Low- power Schot t ky
( 54/ 74LS)
300 500 300 700 mV
ALSTTL

Advanced Low-
power Schot t ky
( 54/ 74ALS)
400 500 300 500 mV
ASTTL Advanced Schot t ky
( 54/ 74AS)
400 500 300 500 mV
FAST Fairchild Advanced
Schot t ky ( 54/ 74F)
300 500 300 500 mV

Loadi ng: The load charact erist ics of Schot t ky TTL families are given in t he following Table.
TTL
Families
I nput current s Out put current s Unit s
I
I H
I
I L
I
OH
I
OL

TTL 0. 04 - 1. 6 - 0. 4 16 mA
STTL 0. 05 - 2 - 1 20 mA
LSTTL 0. 02 - 0. 4 - 0. 4 8 mA
ALSTTL 0. 02 - 0. 1 - 0. 4 8 mA
ASTTL 0. 02 - 0. 5 - 1 20 mA
FAST 0 0 - 0.4 8 mA

Fan out is a measure of t he number of gat e input s t hat are connect ed t o ( or driven by)
a single out put . The current s associat ed wit h LSTTL family are:
I
I Lmax
= - 0. 4 mA ( This current flows out of a LSTTL input . This is somet imes
called Low- st at e unit load for LSTTL)
I
I Hmax
= 20 A ( This current flows int o t he LSTTL input . This is called
High- st at e Unit load for LSTTL)
I
OLmax
= 8 mA
I
OHmax
= - 400 A
Fan out in bot h t he High and Low st at es is 20
LSTTL Dynami c El ect r i cal Behavi or
Bot h t he speed and t he power consumpt ion of LSTTL device depend on, t o a large
ext ent , AC or dynamic charact erist ics of t he device and it s load, t hat is, what happens
when t he out put changes bet ween st at es. The speed depends on t wo fact ors, t r ansit ion
t imes and propagat ion delay.
Tr ansi t i on Ti me: The amount of t ime t hat t he out put of a logic circuit t akes t o change
from one st at e t o anot her is called t he t ransit ion t ime. The ideal sit uat ion we would like
t o have is shown in t he figure ( a) .
t
f
t
r
t
f
t
r
(a)
(b)
(c)

However, in view of t he parasit ic associat ed wit h circuit s and boards, it is neit her
possible nor desirable t o have such zero t ransit ion t imes. Realist ically, an out put t akes

some finit e t ime t o t ransit from one st at e t o t he ot her. These t ransit ion t imes are also
known as rise t ime and fall t ime. The semi- idealist ic t ransit ions are shown in t he figure
( b) . But in act ualit y t he t ransit ions are never sharp in view of t he parasit ic element s,
and edges are always rounded. We may ident ify t he t ransit ion t imes as t he t imes t aken
for t he out put t o t raverse t he undefined volt age zones, as shown in t he figure ( c) .
The rise and fall t imes of a LSTTL out put depend mainly on t wo fact ors, t he ON
t ransist or r esist ance and t he load capacit ance. The load capacit ance comes from t hree
different sources: out put circuit s including a gat es out put t ransist ors, int ernal wir ing
and packaging, have capacit ances associat ed wit h t hem ( of t he or der of 2- 10 pF) ;
wiring t hat connect s an out put t o ot her input s ( about 1pF per inch or more depending
on t he wiring t echnology) ; and input circuit s including t ransist ors, int ernal wiring and
packaging ( 2- 15 pF per input ) .
Pr opagat i on Del ay: Several fact ors lead t o nonzero propagat ion delays. I n a LSTTL
device, t he rat e at which t ransist ors change st at e is influenced by t he physics of t he
device, t he circuit environment including input - signal t ransit ion rat e, input capacit ance,
and out put loading. To fact or out t he effect of rise and fall t imes, manufact urers usually
specify propagat ion delays at t he midpoint s of input and out put t ransit ions, as shown in
t he figure.

t
PHL
t
PLH

Pow er Consumpt i on: The current s drawn by t he TTL circuit s would be different in
logic 0 and 1 st at es, as different set s of t ransist ors get swit ched on in different st at es.
Hence t he designat ions of t he supply current are I
CCL
and I
CCH
. For comput ing t he power
consumed by t he gat e an average ( I
CC
) of t hese t wo current s is t aken. The power
consumed is given by
P
D
= I
CC
x V
CC

When a TTL circuit changes it s st at e, t he current drawn during t he t ransit ion t ime would
be larger t han eit her of t he st eady st at es, as larger number of t ransist ors would come
int o conduct ing st at e. The t ransit ion peak creat es a large noise signal on t he power
supply line. I f t his is not properly filt ered by using a bypass capacit ance very close t o
t he I C, it can const it ut e a maj or source of noise signals in TTL based digit al syst ems.
Therefore, t here is a component of power dissipat ion t hat is proport ional t o frequency.
However, t his frequency dependent power dissipat ion becomes significant wit h regard t o
quiescent power dissipat ion only at very high frequencies.

Table gives t he performance charact erist ics of TTL family, which also enables us t o
appreciat e how t he t echnology improvement s lead t o t he performance improvement s.

Family
Prop.
Delay

( ns)
PWR
Dissp.

( mW)
SPD. PWR
Product

( pJ)
Maximum
Flip- Flop
frequency
( MHz)
TTL 10 10 100 35
HTTL 6 22 132 50
LTTL 33 1 33 3
LSTTL 9 2 18 45
STTL 3 19 57 125
ALS 4 1. 2 4. 8 70
AS 1. 7 8 13. 6 200
FAST 3. 5 5. 4 18. 9 125

Digital Electronics
Module 3: TTL Family
N.J. Rao
TTL Family
It offered best performance-to-cost ratio at the time of its introduction
Its versatility lead to several subfamilies:
Low Power TTL
High Frequency TTL
Schottky TTL
Several sub-families have evolved in the Schottky TTL family:
Low-power Schottky TTL (LSTTL)
Fairchild Advanced Schottky TTL (FAST)
Advanced Low Power Schottky TTL (ALSTTL)
Advanced Schottky TTL (ASTTL)
Bipolar logic families
Use semiconductor diodes and bipolar junction transistor
as the basic building blocks
Simplest bipolar logic elements use diodes and resistors
to perform logic operation (diode logic)
Many TTL logic gates use diode logic internally, and
boost their output drive capability using transistor
circuits.
Some TTL gates use parallel configurations of
transistors to perform logic functions.
Diode
A diode can be modelled as
Slope = 1/R
f
V
I
V
d
Vd=0.6v
Reverse bias Forward bias
Diode (2)
It is an open circuit when it is reverse biased (we ignore
its leakage current)
It acts like a small resistance, R
f
, in series with V
d
, a
small voltage source.
R
f
is the forward resistance of the diode, about 25
V
d
is called diode drop, and is about 0.6 V
Logic operation with diodes
The circuit performs AND function
0-2 V (Low) input is considered logic 0
3-5 V (High) input is considered as logic 1.
When both A and B inputs are High, the output X is High
When any one of the inputs is at Low level the output is Low
Bipolar Junction Transistor as a
Switch
V
cc
R1
R2
I
b
Ic
I
b
+I
c
Transistor as a Switch
When the input of a saturated transistor is changed
Output does not change immediately
It takes extra time, called storage time, to come out of
saturation
Storage time accounts for a significant portion of the
propagation delay in the earlier TTL families.
This storage time is reduced by placing a Schottky diode
between the base and collector of each transistor that
might saturate.
Schottky Barrier Diode
Forward current- voltage
characteristics differences
between the SBD and p-n
junction
It is a rectifying metal-
semiconductor contact
formed between a metal and
highly doped N
semiconductor.
Schottky Transistor
The Schottky transistor makes use of two earlier concepts:
Baker clamp
Schottky-Barrier-Diode (SBD)
Basic NAND Gate
A
B
D2
D1
D5
D6
D3
D4
Q3
Q4
Q5
Q2
Q1
15K
5K
35K
28K
18K
76K
110
Vcc
FAST Schottky TTL NAND
D4
D2
D6
D5
10K 10K 4.1K
45
Q6
Q5
D7
D8
Q2
15K 2K
3K
D10 D11
Q7 Q4
D12
5K
Vcc
D9
Q8
D1
D3
75-80% power reduction compared to standard Schottky
TTL
20-40% improvement in the circuit performance using
MOSAIC process
A flatter power/frequency curve
Higher fan out
FAST devices provide
ALS NAND Gate
2 K
A
V
c c
OUTPUT
B

D 1
D 3
D 4
D 2
Q 2
Q 4
Q 3
Q 1
Q 9

Q 5
Q 7
D 8
2 5 K
Q1 1
1 0 0
D 9
D 7
D 6
Q 6
D 5
3 0 K
2 K
D1 1
5 0 K
2 6
Q 8
1 K
Q1 0
D1 0
2 k
1 k
1 0 K
ASTTL NAND Gate
5. 6K
2. 8K
A

5 K
OUTPUT
B
50
50 K
Q6
37K
D1
D5
D3
D4
D2
Q2
Q4
Q3
Q1
Q7

Q8
Q5
V
cc
Electrical Characteristics of
STTL family
V 2.5 0.5 2 0.8 2.5 0.5 2 0.8 Fairchild Advanced
Schottky (54/74F)
FAST
V 2.7 0.5 2 0.8 2.5 0.5 2 0.8 Advanced Schottky
(54/74AS)
ASTTL
V 2.7 0.5 2 0.8 2.5 0.4 2 0.8 Advanced Low- power
Schottky
(54/74ALS)
ALSTTL
V 2.7 0.5 2 0.8 2.5 0.5 2 0.8 Low-power Schottky
(54/74LS)
LSTTL
V 2.7 0.5 2 0.8 2.5 0.5 2 0.8 Schottky (54/74S) STTL
V 2.4 0.4 2 0.8 2.4 0.4 2 0.8 Standard (54/74) TTL
V
OH
V
OL
V
IH
V
IL
V
OH
V
O
V
IH
V
I
Commercial (0 to 70
o
C) Military (-55 to +125
o
C) TTL Families
Noise Margins
dc noise margin in High state
= V
OHmin
- V
IHmin
= 0.7 V
dc noise margin in Low state
= V
ILmax
- V
OLmax
= 0.3 V
Noise Margins
mV 500 300 500 300 Fairchild Advanced
Schottky (54/74F)
FAST
mV 500 300 500 400 Advanced Schottky
(54/74AS)
ASTTL
mV 500 300 500 400 AdvancedLow- power
Schottky (54/74ALS)
ALSTTL
mV 700 300 500 300 Low-power Schottky
(54/74LS)
LSTTL
mV 700 300 500 300 Schottky (54/74S) STTL
mV 400 300 400 400 Standard (54/74) TTL
High
NM
Low NM High NM Low NM
Commercial
(0 to 70
o
C)
Military
(-55 to +125
o
C
TTL Families
Loading
mA 8 -0.4 0 0 FAST
mA 20 -1 -0.5 0.02 ASTTL
mA 8 -0.4 -0.1 0.02 ALSTTL
mA 8 -0.4 -0.4 0.02 LSTTL
mA 20 -1 -2 0.05 STTL
mA 16 -0.4 -1.6 0.04 TTL
I
OL
I
OH
I
IL
I
IH
Units
Output currents Input currents
TTL Family
Fan out
I
ILmax
= -0.4 mA (This current flows out of a LSTTL input
and this is called Low-state unit load
for LSTTL)
I
IHmax
= 20 mA (This current flows into the LSTTL input,
and is called High-state Unit load for
LSTTL)
I
OLmax
= 8 mA
I
OHmax
= - 400 A
Fan out in both High and Low states is 20
Signal Representation
t
f
t
r
t
f
t
r
(a)
(b)
(c)
Transition Times
The rise and fall times depend on
ON transistor resistance and
Load capacitance
The load capacitance comes from
Internal wiring and packaging have capacitances
associated with them (about 2-10 pF)
Wiring that connects an output to other inputs (about
1 pF per inch or more depending on the wiring
technology)
Input circuits including transistors, internal wiring and
packaging (2-15 pF per input)
Propagation Delay
Manufacturers usually specify propagation delays at the
midpoints of input and output transitions
t
PHL
t
PLH
Power Consumption
The currents drawn would be different in logic 0 and 1 states
I
CC
is the average of I
CCL
and I
CCH
The power consumed is given by P
D
= I
CC
x V
CC
Current drawn during the transition time would be larger than either
of the steady states
Transition peaks create large noise signal on the power supply line.
Needs filtering by using a bypass capacitance very close to the IC
Transition component of power dissipation is proportional to
frequency.
This frequency dependent power dissipation becomes significant
with regard to quiescent power dissipation only at very high
frequencies.
Performance characteristics
125 18.9 5.4 3.5 FAST
200 13.6 8 1.7 AS
70 4.8 1.2 4 ALS
125 57 19 3 STTL
45 18 2 9 LSTTL
3 33 1 33 LTTL
50 132 22 6 HTTL
35 100 10 10 TTL
Maximum
Flip-Flop frequency
(MHz)
SPD.PWR
Product
(pJ)
PWR
Dissp.
(mW)
Prop.
Delay
(ns)
Family

TTL Fami l y
I nt r oduct i on
Transist or- Transist or Logic ( TTL) and Emit t er Coupled Logic ( ECL) are t he most commonly
used bipolar logic families. Bipolar logic families use semiconduct or diodes and bipolar
j unct ion t ransist ors as t he basic building blocks of logic circuit s. Simplest bipolar logic
element s use diodes and resist ors t o perform logic operat ion; t his is called diode logic.
Many TTL logic gat es use diode logic int ernally, and boost t heir out put drive capabilit y using
t ransist or circuit s. Ot her TTL gat es use parallel configurat ions of t ransist ors t o perform logic
funct ions.
I t t urned out at t he t ime of int roducing TTL circuit s t hat t hey were adapt able t o virt ually all
forms of I C logic and produced t he highest performance- t o- cost rat io of all logic t ypes. I n
view of it s versat ilit y a variet y of subfamilies ( Low Power, High Frequency, Schot t ky)
represent ing a wide range of speed- power product have also been int roduced. The Schot t ky
family has been select ed by t he indust ry t o furt her enhance t he speed- power product . I n
Schot t ky family circuit s, a Schot t ky diode is used as a clamp across t he base- collect or
j unct ion of a t ransist or t o prevent it from going int o sat urat ion, t hereby reducing t he
st orage t ime. Several subfamilies have evolved in t he Schot t ky TTL family t o offer several
speed- power product s t o meet a wide variet y of design requirement s. These subfamilies
are:
Low- power Schot t ky TTL ( LSTTL)
Fairchild Advanced Schot t ky TTL ( FAST)
Advanced Low Power Schot t ky TTL ( ALSTTL)
Advanced Schot t ky TTL ( ASTTL)
We will explore t he char act erist ics of t he TTL family in t his Learning Unit .
Di odes
A semiconduct or diode is fabr icat ed from t wo t ypes, p- t ype and n- t ype, of semiconduct or
mat erial t hat are brought int o cont act wit h each ot her. The point of cont act bet ween t he p
and n mat erials is called p- n j unct ion. Act ually, a diode is fabr icat ed from a single
monolit hic cryst al of semiconduct or mat erial in which t he t wo halves are doped wit h
different impurit ies t o give t hem p- t ype and n- t ype propert ies. A real diode can be modelled
as shown in t he figure 1.
I t is an open circuit when it is reverse biased ( we ignore it s leakage current )
I t act s like a small resist ance, R
f
, called t he forward resist ance, in series wit h V
d
,
called a diode drop, a small volt age source.
The forward diode drop would be about 0. 6 V and R
f
is about 25 .

Reverse bias Forwar d bias
FI G. 1: Model of a real diode
Diode act ion is exploit ed t o perform logical operat ions. The circuit shown in t he figure 2
performs AND funct ion if 0- 2 V ( Low) input is considered logic 0 and 3- 5 V ( High) input is
considered as logic 1. When bot h A and B input s are High, t he out put X will be High. I f any
one of t he input s is at Low level, t he out put will also be at Low level.

FI G. 2: Diode AND gat e
Bi pol ar Junct i on Tr ansi st or
A bipolar j unct ion t ransist or is a t hree t erminal device and act s like a current - cont rolled
swit ch. I f a small current is inj ect ed int o t he base, t he swit ch is on , t hat is, t he current
will flow bet ween t he ot her t wo t erminals, namely, collect or and emit t er. I f no current is put
int o t he base, t hen t he swit ch is off and no current flows bet ween t he emit t er and t he
collect or. A t ransist or will have t wo p- n j unct ions, and consequent ly it could be pnp
t ransist or or npn t ransist or. An npn t ransist or, found more commonly in I C logic circuit s, is
shown in t he figure 3 in it s common- emit t er configurat ion.

FI G. 3: Common emit t er configur at ion of an npn t ransist or

The relat ions bet ween different quant it ies are given as in t he following:
I
b
= ( V
I N
- 0. 6) / R1
I
C
= . I
b

V
CE
= V
CC
- I
C
. R2
= V
CC
- . I
b
. R2
= V
CC
- ( V
I N
- 0. 6) . R2/ R1
where is called t he gain of t he t ransist or and is in t he range of 10 t o 100 for t ypical
t ransist ors. Figure 4 shows a logic invert er from an npn t ransist or in t he common- emit t er
configurat ion. When t he input volt age V
I N
Low, t he out put volt age is High, and vice versa.

FI G. 4: Transist or invert er
When t he input of a sat urat ed t ransist or is changed, t he out put does not change
immediat ely; it t akes ext ra t ime, called st orage t ime, t o come out of sat urat ion. I n fact ,
st orage t ime account s for a significant port ion of t he propagat ion delay in t he earlier TTL
families. Present day TTL logic families reduce t his st orage t ime by placing a Schot t ky diode
bet ween t he base and collect or of each t ransist or t hat might sat urat e.
Schot t k y Bar r i er Di ode
A Schot t ky Barrier Diode ( SBD) is illust rat ed in figure 5. I t is a rect ifying met al-
semiconduct or cont act formed bet ween a met al and highly doped N semiconduct or.

FI G. 5: Schot t ky Barrier - Diode
The valence and conduct ion bands in a met al overlap making available a large number of
free- energy st at es. The free- energy st at es can be filled by any elect rons which are inj ect ed
int o t he conduct ion band. A finit e number of elect rons exist in t he conduct ion band of a
semiconduct or. The number of elect rons depends mainly upon t he t hermal energy and t he
level of impurit y at oms in t he mat erial. When a met al- semiconduct or j unct ion is formed,
free elect rons flow acr oss t he j unct ion from t he semiconduct or, via t he conduct ion band,
and fill t he free- energy st at es in t he met al. This flow of elect rons builds a deplet ion
pot ent ial across t he barrier. This deplet ion pot ent ial opposes t he elect ron flow and,
event ually, is sufficient t o sust ain a balance where t here is no net elect ron flow across t he
barrier. Under t he forward bias ( met al posit ive) , t here are many elect rons wit h enough
t hermal energy t o cross t he barrier pot ent ial int o t he met al. This forward bias is called hot
inj ect ion. Because t he barrier widt h is decreased as forward bias V
F
increases, forward
current will increase rapidly wit h an increase in V
F
.
When t he SBD is reverse biased, elect rons in t he semiconduct or require great er energy t o
cross t he barrier. However, elect rons in t he met al see a barrier pot ent ial from t he side
essent ially independent of t he bias volt age and small net reverse current will flow. Since
t his current flow is relat ively independent of t he applied reverse bias, t he reverse current
flow will not increase significant ly unt il avalanche breakdown occurs. A simple met al/ n-
semiconduct or collect or cont act is an ohmic cont act while t he SBD cont act is a rect ifying
cont act . The difference is cont rolled by t he level of doping in t he semiconduct or mat erial.
Current in SBD is carried by maj orit y carriers. Current in a p- n j unct ion is carried by
minorit y carriers and t he result ant minorit y carrier st orage causes t he swit ching t ime of a p-
n j unct ion t o be limit ed when swit ched from forward bias t o reverse bias. A p- n j unct ion is
inherent ly slower t han an SBD even when doped wit h gold. Anot her maj or difference
bet ween t he SBD and p- n j unct ion is forward volt age drop. For diodes of t he same surface
area, t he SBD will have a larger forward curr ent at t he same forward bias regardless of t he
t ype of met al used. The SBD forward volt age drop is lower at a given current t han a p- n
j unct ion. Figure 6 illust rat es t he forward current - volt age charact erist ic differences bet ween
t he SBD and p- n j unct ion.

FI G. 6: Charact erist ics of SBD and pn j unct ion diodes
Schot t k y Tr ansi st or
The Schot t ky t ransist or makes use of t wo earlier concept s: Baker clamp and t he Schot t ky-
Barrier- Diode ( SBD) . The Schot t ky clamped t ransist or is responsible for incr easing t he
swit ching speed. The use of Baker Clamp, shown in t he figure 7, is a met hod of avoiding
sat urat ion of a discret e t ransist or.

FI G. 7: Baker Clamp
The germanium diode forward volt age is 0. 3 V t o 0. 4 V as compared t o 0. 7 V for t he base-
emit t er j unct ion silicon diode. When t he t ransist or is t urned on, base current drives t he
t ransist or t oward sat urat ion. The collect or volt age drops, t he germanium diode begins t o
conduct for ward current , and excess base drive is divert ed from t he base- collect or j unct ion
of t he t ransist or. This causes t he t ransist or t o be held out of deep sat urat ion, t he excess
base charge not st ored, and t he t urn- off t ime t o be dramat ically reduced. However, a
germanium diode cannot be incorporat ed int o a monolit hic silicon int egrat ed circuit .
Therefore, t he germanium diode must be replaced wit h a silicon diode which has a lower
forward volt age drop t han t he base- collect or j unct ion of t he t ransist or. A normal p- n diode
will not meet t his requirement . An SBD can be used t o meet t he requirement as shown in
t he figure 8.

FI G. 8: The Schot t ky- Clamped Transist or
The SBD meet s t he requirement s of a silicon diode which will clamp a silicon npn t ransist or
out of sat ur at ion.
BASI C NAND GATE
The familiarizat ion wit h a logic family is acquired, in general, t hrough underst anding t he
circuit feat ures of a NAND gat e. The circuit diagram of a t wo- input LSTTL NAND gat e,
74LS00, is shown in t he figure 9.
D1 and D2 along wit h 18 K resist or perform t he AND funct ion. Diodes D3 and D4 do
not hing in normal operat ion, but limit undesirable negat ive excursions on t he input s t o a
signal diode drop. Such negat ive excursions may occur on High- t o- Low input t ransit ions as
a result of t ransmission- line effect s. Transist or Q1 serves as an invert er, so t he out put at it s
collect or represent s t he NAND funct ion. I t also, along wit h it s resist ors, forms a phase
split t er t hat cont rols t he out put st age. The out put st at e has t wo t r ansist ors, Q3 and Q4,
only one of which is on at any t ime. The TTL out put st at e is somet imes called a t ot em- pole
out put . Q2 and Q5 provide act ive pull- up and pull- down t o t he High and Low st at es,
respect ively. Transist or Q5 regulat es current flow int o t he base of Q4 and aids in t urning Q4
off rapidly. Transist ors Q3 and Q2 const it ut e a Darlingt on driver, wit h Q3 not being
permit t ed t o sat urat e. The net work consist ing of Schot t ky diodes D3 and D4 and a 5 K
resist or is connect ed t o t he out put and aids in charging and discharging load capacit ance
when Q3 and Q4 are changing st at es. Transist or Q4 conduct s when t he out put is in Low
st at e.

FI G. 9: Low Power Schot t ky NAND ( 74LS00)
The FAST Schot t ky TTL family provides a 75- 80% power reduct ion compared t o st andard
Schot t ky TTL and yet offers 20- 40% improved circuit performance over t he st andard
Schot t ky due t o t he MOSAI C process. Also, FAST circuit s cont ain addit ional circuit ry t o
provide a flat t er power/ frequency curve. The input configurat ion of FAST uses a lower input
current which t ranslat es int o higher fanout . The NAND gat e of FAST family is shown in t he
figure 10.
The F00 input configurat ion ut ilises a p- n diodes ( D1 and D2) rat her t han pnp- t ransist or.
The p- n diode offers a much smaller capacit ance and result s in much bet t er ac noise
immunit y at t he expense of increased input

current

FI G. 10: FAST NAND ( 74F00)
Figure 11 shows one gat e in 74ALS00A quad 2- input NAND gat e parallel- connect ed pnp
t ransist ors Q1 and Q2 are used at t he input . These t ransist ors reduce t he current flow, I
R
,
when t he input s are low and t hus increase fan out . I f input s A, B, or bot h are low, t hen t he
respect ive pnp t ransist ors t urn on because t heir emit t ers are t hen more posit ive t han t heir
bases. I f at least one of t he input s is low, t he corresponding pnp t ransist or conduct s,
making t he base of Q3 low and keeping Q3 off. I f bot h t he input s A and B are high, bot h
swit ches ar e open and Q3 t urns on. Q3 drives Q4 ( by emit t er follower act ion) , and Q4
drives t he out put t ot em pole. Schot t ky diodes D3, D4 and D5 are used t o speed t he
swit ching and do not affect t he logic. Not e t hat t he out put and t he input s have Schot t ky
prot ect ive diodes. Figur e 12 shows one gat e in 74AS00 gat e.

FI G. 11: ALS NAND gat e
( 74ALS00A)

FI G. 12: ASTTL NAND gat e ( 74AS00)
Not e t hat t he input logic circuit ry is essent ially t he same as t hat in 74ALS00 gat e, as is t he
out put t ot em pole. The addit ional circuit ry bet ween input and out put improves swit ching
speeds using sophist icat ed drivers and feedback net works
The ALS and AS families incorporat e t he following feat ures:
1. Full Schot t ky clamping of all sat urat ing t ransist ors virt ually eliminat ing st oring
excessive base charge and significant ly enhancing t urn- off t ime of t he t ransist or s.
2. Eliminat ion of t ransist or st orage t ime provides st able swit ching t imes across t he
t emperat ure range.
3. An act ive t urn- off is added t o square up t he t ransfer charact erist ic and provide
improved high- level noise immunit y.
4. I nput and out put clamping is implement ed wit h Schot t ky diodes t o reduce negat ive-
going excur sions on t he input s and out put s. Because of it s lower forward volt age
drop and fast recovery t ime, t he Schot t ky input diode provides improved clamping
act ion over a convent ional p- n j unct ion diode.
5. The ion implant at ion process allows small geomet ries giving less parasit ic
capacit ances so t hat swit ching t imes are decreased.
6. The reduct ion of t he epi- subst rat e capacit ance using oxide isolat ion also decreases
swit ching t imes.
Digital Electronics
Module 3: CMOS Family
N.J. Rao
CMOS Family
CMOS has often been called the ideal technology.
It has
Low power dissipation
High noise immunity to power supply noise
Symmetric switching characteristics
Large supply voltage tolerance
CMOS Family
Reducing power requirements leads to
Reduction in the cost of power supplies
Simplifies power distribution
Possible elimination of cooling fans
A denser PCB
Ultimately lower cost of the system
History of CMOS
Operation of a MOS transmission was understood long
before bipolar transistor was invented
As its fabrication could not be monitored, development of
MOS circuits lagged bipolar circuits considerably
Initially they were attractive only in selected applications.
At present CMOS circuits are used from SSIs to VLSIs
MOS transistor
The basic building blocks in CMOS logic circuits are MOS
transistors.
A MOS transistor can be viewed as a 3-terminal device
that acts like a voltage-controlled resistance
Vin
MOS transistor
An input voltage, applied to one terminal, controls the
resistance between the remaining two terminals.
In digital applications, a MOS transistor is operated so
that its resistance is always either very high (and the
transistor off) or very low (and the transistor is always
on).
Types of MOS transistors
There are two types of transistors
NMOS transistor that uses n-channel
PMOS transistor that uses p-channel
NMOS Transistor
V
GS
in NMOS device is normally zero or positive.
If V
GS
= 0 then the resistance from drain to source (R
DS
) is
very high, of the order of mega ohm or more.
When V
GS
is made positive R
DS
can decrease to a very low
value, of the order of 10 ohms.
PMOS Transistor
V
GS
is normally zero or negative.
If V
GS
is zero, then the resistance from source to drain
(R
DS
) is very large
When V
GS
is negative R
DS
can decrease to a very low
value.
Gate
Drain
V
GS
Source
Gate of a MOS transistor
It has very high impedance
Gate is separated from the source and drain by an
insulating material with a very high resistance.
Gate voltage creates an electric field that enhances or
retards the flow of current between source and drain.
This is the field effect in a MOSFET.
The high resistance between the gate and the other
terminals keeps the gate current to values lower than a
microampere irrespective of the gate voltage.
Gate of a MOS transistor (2)
The gate current is called leakage current.
The gate of a MOS transistor is capacitively coupled to
the source and drain.
In high speed circuits, the power needed to charge and
discharge these capacitances on each input signal
transition accounts for a non trivial portion of a circuits
power consumption.
Basic CMOS Inverter circuit
NMOS and PMOS transistors are used together in a
complementary way to form CMOS logic
The power supply voltage V
DD
, typically is in the range of
2- 6 V, and is most often set at 5.0 V for compatibility
with TTL circuits.
Basic CMOS Inverter circuit (2)
0V On Off 5.0
5V Off On 0.0
V
OUT
Q2 Q1 V
IN
When V
IN
is at 0.0 V, the lower n-channel MOSFET Q1 is OFF since its
V
GS
is 0, but the upper p-channel MOSFET Q2 is ON since its V
GS
would be -5.0 V
V
OUT
at the output terminal would be +5.0 V.
Similarly when V
IN
is at 5.0 Q1 will be ON presenting a small
resistance, while Q2 will be OFF presenting a large resistance.
V
OUT
would be 0 V
Inverter as per the bubble convention
CMOS NAND Gate
L OFF OFF ON ON H H
H ON OFF OFF ON L H
H OFF ON ON OFF H L
H ON ON OFF OFF L L
X Q4 Q3 Q2 Q1 B A
CMOS NOR Gate
L OFF OFF ON ON H H
L ON OFF OFF ON L H
L OFF ON ON OFF H L
H ON ON OFF OFF L L
X Q4 Q3 Q2 Q1 B A
Non-inverting Gates
A X = A
V
DD
Buffer AND Gate
Buffering
Unbuffered NAND
Most of the CMOS families are buffered.
Buffered NAND
Advantages of buffering
Output characteristics of all devices are more easily
made identical.
Multistage gates will have better noise immunity due to
their higher gain caused by having several stages from
input to output.
Output impedance of buffered gates is unaffected by
input conditions
Advantages of buffering (2)
Single stage gates implemented would require large
transistors due to the large output drive requirements.
Large devices would have a large input capacitance
associated with them. This would affect the speed of
circuits driving into an unbuffered gate, especially when
driving large fan outs.
Buffered gates have small input transistors and
correspondingly small input capacitance.
Internal stages are much faster than the output stage
and speed lost by buffering is relatively small.
Transmission Gates
A p-channel and n-channel transistor pair can be used
as a logic-controlled switch.
When EN is High there is a low impedance connection
(as low as 5 W) between points A and B.
When EN is Low, points A and B are disconnected.
Propagation delay from A to B is very short.
2-input multiplexer with
transmission gate
When S is Low, the B is connected to X, and
when S is High, A is connected to X.
CMOS Input and Output Structures
CMOS family offers a Hex inverter with Schmitt inputs
(74HC14).
It offers a hysterisis of 1.5 V when operated at 5 V.
CMOS tri-state buffer
H ON OFF H H
L OFF ON L H
Hi-Z OFF OFF H L
Hi-Z OFF OFF L L
OUT Q2 Q1 A EN
Open-drain CMOS NAND gate

A
B
X
A B Q1 Q2 X
L L
L
H
H
H
L on off open
H
off off open
off on open
on on L
A
B
X
Open-drain CMOS NAND gate
driving a load
A
B C
D
X
Y
R = 1.5 K
CMOS Logic Families
4000-series
High Speed CMOS (75HC CMOS)
High Speed TTL compatible CMOS (75HCT CMOS)
HC CMOS can use any power supply voltage between 2
and 6 V.
Lowering the supply voltage is effective, since most
CMOS power dissipation is CV
2
f
CMOS Logic Families (2)
AC (Advanced CMOS) ACT (Advanced CMOS, TTL
compatible) were introduced in mid-1980s.
FCT (Fast CMOS, TTL compatible) introduced in 1990s
The family combines circuit innovations with smaller
transistor geometries to produce devices that are even
faster than AC and ACT while reducing power
consumption and maintaining full compatibility with TTL.
Subfamilies of FCT CMOS
FCT-T and FCT2-T
These families represent a technology crossover point
that occurred when the performance achieved using
CMOS technology matched that of bipolar technology,
and typically one third the power.
Both the logic families are TTL compatible
Logical Levels

2
3
V C
1
3
V
C
V 0.4 0.2 0.5 2.4 0.7 2 FCT
V 2.4 0.7 0.1 V
CC
-0.1 0.8 2 ACTMOS
V 1.4 1.4 0.1 V
CC
-0.1 1.5 3.5 ACMOS
V 2.4 0.7 0.1 V
CC
-0.1 0.8 2 HCTMOS
V 1.4 1.4 0.1 V
CC
-0.1 1.5 3.5 HCMOS
V 1.6 1.6 0.01 V
CC
-0.1 4000B
NM HIGH
@V
CC
=5V
NM LOW
@V
CC
=5V
V
OLMAX
V
OHMIN
V
ILMAX
V
IHMIN
Family
Noise Margins
Voltage levels associated with CMOS gates
V
IL(max)
= 30% VDD
V
OH(min)
= VDD - 0.1 V
V
IH(min)
= 70% VDD
Input and Output Current Levels
mA 48 @0.5 V -15 @ 2.4 V -0.005 0.005 74FCT
mA 24 @0.4 V -24@V
CC
-0.8 -0.001 0.001 74ACT
mA 24 @0.4 V -24@V
CC
-0.8 -0.001 0.001 74AC
mA 4 @ 0.4 V -4 @V
CC
-0.8 0.001 0.001 74HCT
mA 4 @0.4 -4 @V
CC
-0.8 -0.001 0.001 74HC
mA 0.4@0.4 V -1.6 @2.5 V 0.001 0.001 4000b +5
I
OL
I
OH
I
IL
I
IH
Output currents Input currents CMOS
Families
Fan out
For HCMOS
I
ILmax
is +1 A in any state
I
OHmax
= -20 A and I
OLmax
= 20 A
Low-state fan out is 20
High-state fan out is 20
If we are willing to work with slightly degraded output
voltages, which would reduce the available noise
margins, we can go for a much larger fan out
Dynamic Electrical Behavior
Speed depends on transition times and propagation delay
The rise and fall times of an output of CMOS IC depend on
ON transistor resistance
Load capacitance
Dynamic Electrical Behavior (2)
Load capacitance comes from
Output circuits including a gates output transistors
Internal wiring and packaging, have capacitances
associated with them (of the order of 2-10 pF)
Wiring that connects an output to other inputs (about 1pF
per inch or more depending on the wiring technology)
Input circuits including transistors, internal wiring and
packaging (2-15 pF per input).
Dynamic Electrical Behavior (3)
OFF transistor resistance would be about 1 M,
ON resistance of p-channel transistor would be of the
order of 200
ON resistance of n-channel resistance would be about
100
We can compute the rise and fall times from the
equivalent circuits.
Propagation Delay
In a CMOS device, the rate at which transistors change
state is influenced by
Physics of the device
Circuit environment including input-signal transition rate,
input capacitance, and output loading
Speed Characteristics
60 5.8 (138) FCTMOS
45 8 ACTMOS
45 8.5 ACMOS
25 24 HCTMOS
25 22 HCMOS
5 160 4000B
Flip-Flop frequency
(MHz)
Prop. Delay
(ns)
Family
Device outputs in AC and ACT families have very fast rise and fall times.
Input signals should have rise and fall times of 3.0 ns (400 ns for HC and
HCT devices) and signal swing of 0V to 3.0V for ACT devices or 0V to
V
DD
for AC devices.
Power Consumption
A CMOS circuit consumes significant power only during
transition
Sources of dynamic power dissipation
Partial short-circuiting of the CMOS output structure
Capacitive load (C
L
) on the output
Partial short-circuiting
The amount of power consumed during transition
depends on
the value of V
DD
the frequency of output transitions
Equivalent dissipation capacitance C
PD
as given by the
manufacturer
PT = C
PD
. V
2
DD
. f
C
PD
for a gate of HCMOS is about 24 pF
Dissipation due to capacitive loading
During Low-to-High transition, current passes through
the p-channel transistor to charge the load capacitance.
During High-to-Low transition, current flows through the
n-channel transistor to discharge the load capacitor.
During the transitions the voltage across the capacitor
changes by V
DD
.
For each pulse there would be two transitions.
Dissipation due to capacitive
loading (2)
As the currents are passing through the transistors, and
capacitor itself would not be dissipating any power, the
power dissipated due to the capacitive load is
2
L L DD
P = C .V .f
Total dynamic power dissipation
P
D
= P
T
+ P
L
=
=
2 2
PD DD L DD
C .V .f+C .V .f
2
PD L DD
(C +C ).V .f
FCT does not have a C
PD
specification
I
CCD
specification gives the same information in a different
way.
The internal power dissipation due to transition at a given
frequency f can be calculated by the formula
P
T
= V
CC
. I
CCD
. f
Power Dissipation Characteristics
pF 60 60 85 85 138
pF 30 30 24 24 00
Power dissipation (capacitance)
mW 7.5 0.04 0.04 0.04 0.04 138
mW 0.005 0.005 0.0025 0.0025 00
Quiescent power dissipation
Units FCT ACT AC HCT HC Parameter
Power Dissipation Characteristics (2)
mW 30 21.04 21.04 21.04 21.04 138 at 10 MHz
mW 9 1.54 1.54 2.14 2.14 138 at 1 MHz
mW 7.5 0.19 0.19 0.25 0.25 138 at 100KHz
mW 7.505 7.505 6.0025 6.0025 00 at 10 MHz
mW 0.755 0.755 0.6025 0.6025 00 at I MHz
mW 0.08 0.08 0.0625 0.0625 00 at 100KHz
Total power dissipation
mW 1.5 1.5 1.5 2.1 2.1 138 at 1 MHz
mW 0.75 0.75 0.6 0.6 00 at 1 MHz
Dynamic power dissipation
Units FCT ACT AC HCT HC Parameter

CMOS FAMI LY
CMOS has oft en been called t he ideal t echnology. I t has low power dissipat ion,
high noise immunit y t o power supply noise, symmet ric swit ching charact erist ics
and large supply volt age t olerance. Reducing power requirement s leads t o
reduct ion in t he cost of power supplies, simplifies power dist ribut ion, possible
eliminat ion of cooling fans and a denser PCB, ult imat ely leading t o lower cost of t he
syst em. Though t he operat ion of a MOS t ransmission was underst ood long before
bipolar t ransist or was invent ed, it s fabricat ion could not be monit ored.
Consequent ly development of MOS circuit s lagged bipolar circuit s considerably, and
init ially t hey were at t ract ive only in select ed applicat ions. I n recent years,
advances in t he design of MOS circuit s have vast ly increased t heir performance and
popularit y. By far maj orit y of t he large scale int egrat ed circuit s such as
microprocessors and memories use CMOS. The usage of CMOS logic is increasing in
applicat ions t hat use small and medium scale int egrat ed circuit s as CMOS circuit s,
while offering funct ionalit y and speed similar t o bipolar logic circuit s, consume very
much less power.
CMOS LOGI C CI RCUI TS
The basic building blocks in CMOS logic circuit s are MOS t ransist ors. A MOS
t ransist or can be received as a 3- t erminal device t hat act s like a volt age- cont rolled
resist ance, as shown in t he figure 1.
Vin

FI G. 1: MOS t ransist or as a volt age cont rolled resist ance
An input volt age applied t o one t erminal cont rols t he resist ance bet ween t he
remaining t wo t erminals. I n digit al applicat ions, a MOS t ransist or is operat ed so it s
resist ance is always eit her very high ( and t he t ransist or off ) or very low ( and t he
t ransist or is always on ) . There are t wo t ypes of MOS t ransist ors n- channel and p-
channel. The circuit symbols for NMOS and PMOS t ransist ors are shown in t he
figure 2.
Drain
Source
Gate
Gate
+ +
_-
_-
Vgs
Vgs
Drain
Source

NMOS t ransist or PMOS t ransist or
FI G. 2: Circuit symbols of MOSFETs

The t erminals are called gat e, source and drain. The volt age from gat e t o source
( V
GS
) in NMOS device is normally zero or posit ive. I f V
GS
= 0 t hen t he resist ance
from drain t o source ( R
DS
) is very high, of t he order of mega ohm or more. When
V
GS
is made posit ive R
DS
can decrease t o a very low value, of t he order of 10 ohms.
I n t he PMOS t ransist or V
GS
is nor mally zero or negat ive. I f V
GS
is zero, t hen t he
resist ance from source t o drain ( R
DS
) is very large, and when V
GS
is negat ive R
DS

can decrease t o a very low value. The gat e of a MOS t ransist or has very high
impedance, as it is separat ed from t he source and drain by an insulat ing mat erial
wit h a very high resist ance. However, t he gat e volt age creat es an elect ric field t hat
enhances or ret ards t he flow of current bet ween source and drain. This is t he field
effect in a MOSFET. The high resist ance bet ween t he gat e and t he ot her t erminals
keeps t he gat e current t o values lower t han a microampere irrespect ive of t he gat e
volt age. This current is called leakage current . The gat e of a MOS t ransist or is
capacit ively coupled t o t he source and drain. I n high speed circuit s, t he power
needed t o charge and discharge t hese capacit ances on each input signal t ransit ion
account s for a non t rivial port ion of a circuit s power consumpt ion.
Basi c CMOS I nver t er ci r cui t : NMOS and PMOS t ransist ors are used t oget her in a
complement ary way t o form CMOS logic, as shown in t he figure 3. The power
supply volt age V
DD
, t ypically is in t he range of 2- 6 V, and is most oft en set at 5. 0
V for compat ibilit y wit h TTL circuit s.

V
DD
V
V
P Channel
N Channel
Q
Q
1
2
IN
OUT
0.0
5.0
Q
Q V
On
Off
Off
On
5V
0V
V
IN 1 2 OUT

FI G. 3: CMOS I nvert er
When V
I N
is at 0. 0 V, t he lower n- channel MOSFET Q1 is OFF since it s V
GS
is 0, but
t he upper p- channel MOSFET Q2 is ON since it s V
GS
would be - 5. 0 V. Consequent ly
Q2 present s a small r esist ance while Q1 present s a lar ge resist ance. V
OUT
at t he
out put t erminal would be + 5. 0 V. Similarly when V
I N
is at 5. 0 Q1 will be ON
present ing a small resist ance t o ground while Q2 will be OFF present ing a large
resist ance. The out put t erminal volt age ( V
OUT
) would be 0 V. Obviously t his circuit
behaves as an invert er.
As we associat ed a logic st at e 0 or 1 wit h a volt age, we can say when t he input
signal is assert ed Q1 is ON and Q2 is OFF, and when t he input signal is not
assert ed Q1 is OFF and Q2 is ON. We make use of t his int erpret at ion t o furt her

simplify t he circuit represent at ion of MOSFETs, as shown in t he figure 4. The
bubble convent ion goes along wit h t he convent ion followed in drawing logic
diagrams.
Q1
Q2
V
DD
V
IN
V
OUT

FI G. 4 CMOS invert er drawn as per logic convent ion
CMOS NAND and NOR gat es: Logic gat es can be realised using CMOS circuit s. A
k- input gat e uses k p- channel MOSFETs and k n- channel MOSFETs. Figure 5 shows
a 2- input NAND gat e. I f eit her input is Low, t he out put X is High wit h low impedance
connect ion t o V
DD
t hrough t he corresponding p- channel t ransist or, and t he pat h t o
t he ground is blocked by t he corresponding OFF n- channel MOSFET. I f bot h input s
are High, t he t wo n- channel MOSFETs are ON and t he t wo p- channel MOSFETs are
OFF. This is t he operat ion required for t he circuit t o funct ion as a NAND gat e.

A B Q1 Q2 Q3 Q4 X
L L OFF OFF ON ON H
L H OFF ON ON OFF H
H L ON OFF OFF ON H
H H ON ON OFF OFF L

FI G. 5: 2- input CMOS NAND gat e
A 2- input NOR gat e is shown in figure 6. Only when A and B are Low t he out put X
is High and for all ot her combinat ion of input levels t he out put is Low.
A B Q1 Q2 Q3 Q4 X
L L OFF OFF ON ON H
L H OFF ON ON OFF L
H L ON OFF OFF ON L
H H ON ON OFF OFF L

FI G. 6: 2- input CMOS NOR gat e

X
V
DD
Q2
Q1
Q4 Q3
A
B A
B
x
A
B
X
VDD
Q2 Q1
Q3
Q4
B
A

Non I nver t i ng Gat es: I n all logic families, t he simplest gat es are invert ers, and
t he next simplest are NAND and NOR gat es. I t is t ypically not possible t o design a
noninvert ing gat e wit h a smaller number of t ransist or s t han an invert ing one.
CMOS noninvert ing buffers and AND and OR gat es are obt ained by connect ing an
invert er t o t he out put of t he corresponding invert ing gat e. Figure 7 shows a non
invert ing buffer and an AND gat e

Buffer AND gat e
FI G. 7: Non invert ing Buffer and AND gat e
Buf f er i ng: Most of t he CMOS families are buffered. Buffering CMOS logic merely
denot es designing t he I C so t hat t he out put is t aken from an invert ing buffer st age.
An unbuffer ed and buffered NAND gat es are illust rat ed in t he figure 8.

FI G. 8: Unbuffered and buffered NAND gat es
There are several advant ages t o buffering. By using t he st andardised buffer, t he
out put char act erist ics of all devices are more easily made ident ical. Mult ist age
gat es will have bet t er noise immunit y due t o t heir higher gain caused by having
several st ages from input t o out put . Also, t he out put impedance of an unbuffer ed
gat e may change wit h input logic level volt age and input logic combinat ion,
whereas buffered out put are unaffect ed by input condit ions. Single st age gat es
implement ed would require large t ransist ors due t o t he large out put drive
requirement s. These large devices would have a large input capacit ance associat ed
A X = A
V
DD
A
B
V
DD
A
B
X = A.B
X
V
DD
Q2
Q1
Q4 Q3
A
B
A
B
X = /(A.B)

wit h t hem. This would affect t he speed of circuit s driving int o an unbuffered gat e,
especially when driving large fan out s. Buffered gat es have small input t ransist ors
and correspondingly small input capacit ances. One may t hink t hat a maj or
disadvant age of buffered circuit s would be speed loss. I t would seem t hat a t wo or
t hree st age gat e would be t wo t o t hree t imes slower t han a buffered one. However,
int ernal st ages are much fast er t han t he out put st age and speed lost by buffering
is relat ively small.
Tr ansmi ssi on Gat es: A p- channel and n- channel t ransist or pair can be used as a
logic- cont rolled swit ch. This circuit , shown in t he figur e 9, is called a CMOS
t ransmission gat e.
/EN
EN
A B

FI G. 9: CMOS t ransmission gat e
A t ransmission gat e is operat ed so t hat it s input signals EN and / EN are always at
opposit e levels. When EN is High and / EN is Low, t here is a low impedance
connect ion ( as low as 5 ) bet ween point s A and B. When EN is Low and / EN is
High, point s A and B are disconnect ed. Once t ransmission gat e is enabled, t he
propagat ion delay from A t o B ( or vice versa) is very short . Because of t heir short
delays and concept ual simplicit y, t ransmission gat es are oft en used int ernally in
larger- scale CMOS devices such as mult iplexers and flip- flops. For example, figure
10 shows how t ransmission gat es can be used t o creat e a 2- input mult iplexer
A
B
S
X
VDD
.
FI G. 10: Two- input mult iplexer using CMOS t ransmission gat es
When S is Low, t he B is connect ed t o X, and when S is High, A is connect ed
t o X. While it may t ake some nanoseconds for t he t ransmission gat e t o
change it s st at e, t he propagat ion delay from input t o out put of t he gat e
would be very small.

CMOS I nput and Out put St r uct ur es: CMOS family like ot her logic families has
provision for accept ing slow changing input s, offering t hree- st at e out put s, and for
wired logic connect ion. CMOS family offers a Hex invert er wit h Schmit t input s
( 74HC14) . I t offers a hyst erisis of 1. 5 V when operat ed at 5 V. I t can t ransform
slowly changing input signals int o sharply defined, j it t er- free out put signals. I n
addit ion, t hey have a great er noise margin t han convent ional invert ers.
A circuit diagram ( including schemat ics for gat es) for a CMOS t hree- st at e buffer is
shown in t he figure 11. When enable ( EN) is Low, bot h out put t ransist ors are off,
and t he out put is in t he Hi- Z st at e. Ot herwise, t he out put is High or Low as
cont rolled by t he dat a input A. The figure also shows logic symbol for a t hree-
st at e buffer. There is a leakage current of up t o 10 A associat ed wit h a CMOS
t hree- st at e out put in it s Hi- Z st at e. This current , as well as t he input current s of
receiving gat es, must be t aken int o account when calculat ing t he maximum
number of devices t hat can be placed on a t hree- st at e bus. That is, in t he Low or
High st at e, an enabled t hree- st at e out put must be capable of sinking or sourcing
10A of leakage current for every ot her t hree- st at e out put on t he bus, as well as
sinking t he current required by every input on t he bus.

EN A Q1 Q2 OUT
L L OFF OFF Hi- Z
L H OFF OFF Hi- Z
H L ON OFF L
H H OFF ON H

FI G. 11: CMOS t hree- st at e buffer
The p- channel t ransist ors in CMOS out put st ruct ures provide act ive pull- up.
These t ransist ors are omit t ed in gat es wit h open- drain out put s, such as t he
NAND gat e in figure 12.

A
B
X
A B Q1 Q2 X
L L
L
H
H
H
L on off open
H
off off open
off on open
on on L
A
B
X

FI G. 12: Open- drain CMOS NAND gat e
V
DD
OUT
EN
A
Q1
Q2
EN
A
OUT

The drain of t he t opmost n- channel t ransist or is left unconnect ed int ernally,
so if t he out put is not Low it is open , as indicat ed in t he figure 13. The
underscored diamond in t he symbol is somet imes used t o indicat e an open-
drain out put . This is similar t o t he open- collect or out put in TTL logic
families. An open- drain out put requires an ext ernal pull- up resist or t o provide
passive pull- up t o t he High level. For example, figure 13 shows an open drain
CMOS NAND gat e, wit h it s pull- up resist or, dr iving a load.

A
B C
D
X
Y
R = 1.5 K

FI G. 13: Open- drain CMOS NAND gat e driving a load

CMOS LOGI C FAMI LI ES
The first commercially successful CMOS family was 4000- series CMOS.
Alt hough 4000- series circuit s offered t he benefit of low power dissipat ion,
t hey were fair ly slow and were not easy t o int erface wit h t he most popular
logic family of t he t ime, bipolar TTL. Thus, t he 4000 series was supplant ed in
most of applicat ions by CMOS families t hat had bet t er performance
charact erist ics. The first t wo 74- series CMOS families are HC ( High- speed
CMOS) and HCT ( High- speed CMOS, TTL compat ible) . HC and HCT bot h have
higher speed and bet t er current sinking and sourcing capabilit y. The HCT
family uses a power supply volt age V
DD
of 5 V and can be int ermixed wit h TTL
device, which also use a 5- V supply.
The HC is mainly opt imised for use in syst ems t hat use CMOS logic
exclusively, and can use any power supply volt age bet ween 2 and 6 V. A
higher volt age is used for higher speed, and lower volt age for lower power
dissipat ion. Lowering t he supply volt age is especially effect ive, since most
CMOS power dissipat ion is proport ional t o t he square of t he volt age ( CV
2
f) .
Even when used wit h a 5 V power supply, HC devices are not quit e
compat ible wit h TTL. I n part icular , HC circuit s are designed t o recognise
CMOS input levels. The out put levels produced by TTL devices do not quit e
mat ch t his range, so HCT devices use t he different input levels. These levels
are est ablished in t he fabricat ion process by making t ransist ors wit h different
swit ching t hreshold, producing t he different t ransfer charact erist ics.

Two more CMOS families, known as AC ( Advanced CMOS) and ACT
( Advanced CMOS, TTL compat ible) were int roduced in mid- 1980s. These
families are fast , comparable t o ALSTTL, and t hey can source or sink more
current t han most of t he TTL circuit s can. Like HC and HCT, t he AC and ACT
families differ only in t he input levels t hat t hey recognise; t heir out put
charact erist ics are t he same. Also like HC/ HCT, AC/ ACT out put s have
symmet ric out put dr ive.
I n t he early 1990s, yet anot her CMOS family was launched. The FCT ( Fast
CMOS, TTL compat ible) family combines circuit innovat ions wit h smaller
t ransist or geomet ries t o produce devices t hat are even fast er t han AC and
ACT while reducing power consumpt ion and maint aining full compat ibilit y
wit h TTL. There are t wo subfamilies, FCT- T and FCT2- T. These families
represent a t echnology crossover point t hat occurred when t he performance
achieved using CMOS t echnology mat ched t hat of bipolar t echnology, and
t ypically one t hird t he power. Bot h t he logic families are TTL compat ible,
which means t hat t hey conform t o t he indust ry- st andard TTL volt age levels
and t hreshold point ( 1. 5 V) , and operat e from a 5 Volt V
CC
power source. All
input s are designed t o have a hyst erisis of 200 mV ( low- t o- high t hreshold of
1. 6 V and high- t o- low t hreshold of 1. 4V) . This hyst eresis increases bot h t he
st at ic and dynamic noise immunit y, as well as reducing t he sensit ivit y t o
noise superimposed on slowly rising or falling input s. I ndividual logic gat es
are not manufact ured in t he FCT families. Just about t he simplest FCT logic
element is a 74FCT138/ 74FCT138T decoder, which has six input s, eight
out put s and cont ains t he equivalent of about t welve 4- input gat es int ernally
ELECTRI CAL BEHAVI OUR OF CMOS CI RCUI TS
This sect ion present s t he elect rical charact erist ics of CMOS families. The
elect rical charact erist ics refer t o DC noise margins, fan out , speed, power
consumpt ion, noise, elect rical discharge, open drain out put s and t hree st at e
out put s.
Logi cal Lev el s and Noi se Mar gi ns: The generat ed volt age levels given by
t he manufact uring dat a sheet for HCMOS circuit s operat ing at V
DD
= 5 V, are
given in t he Table 1. The input paramet ers are mainly det ermined by t he
swit ching t hreshold of t he t wo t ransist ors, while t he out put paramet ers are
det ermined by t he ON resist ance of t he t ransist ors. These paramet ers apply
when t he device input s and out put s are connect ed only t o ot her CMOS
devices. The dc volt age levels and noise margins of CMOS families are given
in t he Table 1.

TABLE 1: DC Charact erist ics of CMOS Families
Family V
I HMI N
V
I LMAX
V
OHMI N
V
OLMAX
NM LOW
@V
CC
= 5V
NM HI GH
@V
CC
= 5V
Unit s
4000B

2
3 V C

1
3
V
C

V
CC
- 0. 1 0. 01 1. 6 1. 6 V
HCMOS 3. 5 1. 5 V
CC
- 0. 1 0. 1 1. 4 1. 4 V
HCTMOS 2 0. 8 V
CC
- 0. 1 0. 1 0. 7 2. 4 V
ACMOS 3. 5 1. 5 V
CC
- 0. 1 0. 1 1. 4 1. 4 V
ACTMOS 2 0. 8 V
CC
- 0. 1 0. 1 0. 7 2. 4 V
FCT 2 0. 7 2. 4 0. 5 0. 2 0. 4 V

These dc noise margins are significant ly bet t er t han t hose associat ed wit h
TTL families. As CMOS circuit s can be operat ed wit h V
DD
= 2 V t o V
DD
= 6 V
t he volt age levels associat ed wit h CMOS gat es may be expressed as
V
I L( max)
= 30% V
DD

V
OH( min)
= V
DD
- 0. 1 V
V
I H( min)
= 70% V
DD

Regardless of t he volt age applied t o t he input of a CMOS invert er, t he input
current s are very small. The maximum leakage current t hat can flow,
designat ed as I
I max
, is + 1A for HCMOS wit h 5 V power supply. As t he load
on a CMOS gat e could vary, t he out put volt age would also vary. I nst ead of
specifying t he out put impedance under all condit ions of loading t he
manufact ur ers specify a maximum load for t he out put in each st at e, and
guarant ee a worst - case out put volt age for t hat load. The load is specified in
t erms of current s. The input and out put current s are given in t he Table 2.
TABLE 2: I nput and Out put Current Levels of CMOS Families
CMOS
Families
I nput current s Out put current s Unit s
I
I H
I
I L
I
OH
I
OL

4000b + 5 0.001 0. 001 - 1.6@2.5 V 0. 4@0. 4 V mA
74HC 0. 001 - 0. 001 - 4 @V
CC
- 0. 8 4@0. 4 mA
74HCT 0. 001 0. 001 - 4@V
CC
- 0. 8 4@ 0. 4 V mA
74AC 0. 001 - 0. 001 - 24 @V
CC
- 0. 8 24@0. 4 V mA
74ACT 0. 001 - 0. 001 - 24 @V
CC
- 0. 8 24 @0. 4 V mA
74FCT 0. 005 - 0. 005 - 15@ 2. 4 V 48@0. 5 V mA

These specificat ions are given at volt ages which are nor mally associat ed wit h TTL
gat es. I f t he current drawn by t he load is smaller, t he volt age levels would improve
significant ly. This happens when CMOS gat es are connect ed t o CMOS loads.

I t is import ant t o not e t hat in a CMOS circuit t he out put st ruct ure by it self
consumes very lit t le current in eit her st at e, High or Low. I n eit her st at e, one of t he
t ransist ors is in t he high impedance OFF st at e. When no load is connect ed t he only
current t hat flows t hr ough t he t ransist ors is t heir leakage current . Wit h a load,
however, current flows t hrough bot h t he load and t he ON t ransist or, and power is
consumed in bot h.
Fan out : The fan out of a logic gat e is t he number of input s t hat t he gat e can drive
wit hout exceeding it s worst - case loading specificat ions. The fan out depends not
only on t he charact erist ics of t he out put , but also on t he input s t hat it is driving.
When a HCMOS gat e is driving HCMOS gat es, we not e t hat I
I Lmax
is + 1 A in any
st at e, and I
OHmax
= - 20 A and I
OLmax
= 20 A. Therefore, t he Low- st at e fan out is
20 and High- st at e fan out is 20 for HCMOS gat es. However, if we are willing t o
work wit h slight ly degraded out put volt ages, which would reduce t he available
noise margins, we can go for I
OHmax
and I
OLmax
of 4. 0 mA. This would mean t hat an
HCMOS gat e can drive as many as 4000 HCMOS gat es. But in act ualit y t his would
not be t rue, as t he current s we are considering are only t he st eady st at e current s
and not t he t ransit ion current s. The act ual fan out under degraded load condit ions
would be far less t han 4000. During t he t ransit ions, t he CMOS out put must charge
or discharge t he capacit ance associat ed wit h t he input s t hat it derives. I f t his
capacit ance is t oo large, t he t ransit ion from Low t o High ( or vice versa) may be t oo
slow causing improper syst em operat ion.
CMOS DYNAMI C ELECTRI CAL BEHAVI OUR
Bot h t he speed and t he power consumpt ion of CMOS devices depend on t o a large
ext ent on AC or dynamic charact erist ics of t he device and it s load, t hat is, what
happens when t he out put changes bet ween st at es. The speed depends on t wo
fact ors, t ransit ion t imes and propagat ion delay.
The rise and fall t imes of an out put of CMOS I C depend mainly on t wo fact ors, t he
ON t ransist or resist ance and t he load capacit ance. The load capacit ance comes
from t hree different sources: out put circuit s including a gat es out put t ransist ors,
int ernal wir ing and packaging, have capacit ances associat ed wit h t hem ( of t he
order of 2- 10 pF) ; wiring t hat connect s an out put t o ot her input s ( about 1pF per
inch or more depending on t he wir ing t echnology) ; and input circuit s including
t ransist ors, int ernal wiring and packaging ( 2- 15 pF per input ) . The OFF t ransist or
resist ance would be about 1 M, t he ON resist ance of p- channel t ransist or would
be of t he order of 200 , and t he ON resist ance of n- channel resist ance would be
about 100 . We can comput e t he rise and fall t imes from t he equivalent circuit s.
Several fact ors lead t o nonzero propagat ion delays. I n a CMOS device, t he rat e at
which t ransist ors change st at e is influenced bot h by t he semiconduct or physics of

t he device and by t he circuit environment including input - signal t ransit ion rat e,
input capacit ance, and out put loading. The speed charact erist ics of CMOS families
are given in t he Table 3.
TABLE 3: Speed Charact erist ics of CMOS families
Family Prop. Delay
( ns)
Flip- Flop
frequency
( MHz)
4000B 160 5
HCMOS 22 25
HCTMOS 24 25
ACMOS 8. 5 45
ACTMOS 8 45
FCTMOS 5. 8( 138) 60

Device out put s in AC and ACT families have very fast rise and fall t imes. I nput
signals should have rise and fall t imes of 3. 0 ns ( 400 ns for HC and HCT devices)
and signal swing of 0V t o 3. 0V for ACT devices or 0V t o V
DD
for AC devices.
Obviously such signal t ransit ion t imes are a maj or source of analog problems,
including swit ching noise and ground bounce .
Pow er Consumpt i on: A CMOS circuit consumes significant power only dur ing
t ransit ion, t hat is dynamic power dissipat ion is more. One source of dynamic power
dissipat ion is t he part ial short - circuit ing of t he CMOS out put st ruct ure. When t he
input volt age is changing from one st at e t o t he ot her, bot h t he p- channel and n-
channel out put t ransist ors may be part ially ON, creat ing a series resist ance of 600
or less. During t his t ransit ion period, current flows t hr ough t he t ransist ors fr om
V
DD
t o ground. The amount of power consumed in t his way depends on t he value of
V
DD
, t he frequency of out put t ransit ions, and an equivalent dissipat ion capacit ance
C
PD
as given by t he manufact urer.
P
T
= C
PD
. V
2
DD
. f
P
T
is t he int ernal power dissipat ion given in wat t s, V
DD
is t he supply volt age in
volt s, f is frequency of out put t ransit ions in Hz, and C
PD
is t he power dissipat ion
capacit ance in farads. C
PD
for a gat e of HCMOS is about 24 pF. This relat ionship is
valid only if t he rise and fall t imes of t he input signal are wit hin t he recommended
maximum values.
Second source of dynamic power dissipat ion is t he CMOS power consumpt ion due
t o t he capacit ive load ( C
L
) on t he out put . During t he Low- t o- High t ransit ion,
current passes t hrough t he p- channel t ransist or t o charge t he load capacit ance.
Likewise, during t he High- t o- Low t ransit ion current flows t hrough t he n- channel
t ransist or t o discharge t he load capacit or. During t hese t ransit ions t he volt age

across t he capacit or changes by + V
DD
. For each pulse t here would be t wo
t ransit ions. As t he current s are passing t hrough t he t ransist ors, and capacit or it self
would not be dissipat ing any power, t he power dissipat ed due t o t he capacit ive
load is

2
DD
L L
V
P = C . .2f
2

2
L L DD
P = C .V .f
The t ot al dynamic power dissipat ion of a CMOS circuit is t he sum of P
T
and P
L
:
P
D
= P
T
+ P
L

=
2 2
PD DD L DD
C .V .f+C .V .f
=
2
PD L DD
(C +C ).V .f
I n most applicat ions of CMOS circuit s, CV
2
f power is t he main t ype of power
dissipat ion. While CV
2
f t ype of power dissipat ion is also consumed by t he bipolar
circuit s like TTL, but at low t o moderat e frequencies it is insignificant compared t o
t he st at ic power dissipat ion of bipolar circuit s.
Unlike ot her CMOS families, FCT does not have a C
PD
specificat ion. However, I
CCD

specificat ion gives t he same informat ion in a different way. The int ernal power
dissipat ion due t o t ransit ion at a given frequency f can be calculat ed by t he formula
P
T
= V
CC
. I
CCD
. f
This family also makes different speed grades of t he same funct ion available.
Power dissipat ion charact erist ics of CMOS families operat ed at 5V are given in t he
Table 4.

TABLE 4: Power Dissipat ion Charact erist ics of CMOS Families
Paramet er HC HCT AC ACT FCT Unit s
Quiescent power
dissipat ion

00 0. 0025 0. 0025 0. 005 0. 005 mW
138 0. 04 0. 04 0. 04 0. 04 7. 5 mW
Power dissipat ion
capacit ance

00 24 24 30 30 pF
138 85 85 60 60 pF
Dynamic power
dissipat ion

00 at 1 MHz 0. 6 0. 6 0. 75 0. 75 mW
138 at 1 MHz 2. 1 2. 1 1. 5 1. 5 1. 5 mW
Tot al power
dissipat ion

00 at 100KHz 0. 0625 0. 0625 0. 08 0. 08 mW
00 at I MHz 0. 6025 0. 6025 0. 755 0. 755 mW
00 at 10 MHz 6. 0025 6. 0025 7. 505 7. 505 mW
138 at 100KHz 0. 25 0. 25 0. 19 0. 19 7. 5 mW
138 at 1 MHz 2. 14 2. 14 1. 54 1. 54 9 mW
138 at 10 MHz 21. 04 21. 04 21. 04 21. 04 30 mW

Digital Electronics
Module 3: ECL Family
N.J. Rao
ECL Family
Bipolar families prevent saturating transistors using
Schottky diodes across the base-collector junctions
Current Mode Logic (CML) structure can be used to
prevent saturation
CML produces a small voltage swing, less than a volt,
between low and high levels
CML switches current between two possible paths
depending on the output state
Introduced by General Electric in 1961
The concept was refined by Motorola and others to
produce present days 10K, 100K (ECL) families
ECL Family (2)
They offer propagation delays as short as 1 ns
They are not as popular as TTL and CMOS mainly
because they consume too much power
High power consumption has made the design of ECL
super computers, such as CRAY as a challenge in
cooling technology
ECL has poor power-speed product, does not provide a
high level of integration
ECL signals have fast edge rates requiring design for
special transmission line effects
ECL circuits are not directly compatible with TTL and
CMOS
Basic CML Circuit
V
R2
330
R1
300
Q1 Q2 V
V
V
R3
1.3K
OUT1
OUT2
IN
IN
BB
E
V
EE
= 0
= 5V
= 4V
Two transistors are connected as a differential amplifier with a
common emitter resistor R3.
Input Low and High levels, are defined to be 3.6 and 4.4 V.
It produces output Low and High levels 0.6 V higher (4.2 and 5.0 V)
2-input OR/NOR gate
Q1 Q2
V
V
R3
EE
BB
V
E
= 4V
Q3
V
V
V
A
B
R1 R2
OUT2
OUT1
CC
= 5V
A
B
OUT1
OUT2
This circuit shown cannot meet the input/ output
loading requirements effectively
ECL 10K OR/NOR gate (ECL10102)
Q1 Q2
V
R3
E E
V
E
Q3
A
B
R1 R2
V
CC 1
=0
D1
D2
R8
4.9k
V
CC
2
=0
R6
6.1k
779
50k
R2
R1
50k
245
220

RL1
RL2
V
out1
V
out2
ECL Families (Motorola)
MECL I in 1962
It offered 8 ns gate propagation delay and 30 MHz toggle
rates
MECL II in 1966
This family offered 4 ns propagation delay for the basic
gate, and 70 MHz toggle rates
MECL III in 1968
It offered 1 ns gate propagation delays and flip-flop
toggle rates higher than 500 MHz
ECL Families (Motorola)
MECL 10K series in 1971
It offered circuits with 2 ns propagation delays. Edge
speed was slowed down to 3.5 ns.
MECL 10KH in 1981
It provides a propagation delay of 1 ns with edge
speed at 1.8 ns and used process called MOSAIC.
MECL 100K
This family offers functions different from those offered
by 10K series. This family operates with a reduced
power supply voltage -4.5 V, has shorter propagation
delay of 0.75 ns, and transition time of 0.7 ns. The
power consumption per gate is about 40 mW.
Subfamilies of MECL 10K
10100 and 10500 series (propagation delay of 2 ns,
edge speed of 3.5 ns and flip-flop toggle rate of 160
MHz)
10200 and 10600 series (propagation delay of 1.5 ns,
edge speed of 2.5 ns and flip-flop toggle rate of 250
MHz)
10800 series (propagation delay of 1 - 2.5 ns and edge
speed of 3.5 ns)
Electrical Characteristics
Values are specified at T
A
= 25
o
C and the nominal power supply
voltage of V
EE
= -5.2 V.
Its common-mode-rejection feature offers immunity against
power-supply noise injection.
130 150 -1.03 -1.62 -1.47 -1.16 ECL 100K
150 150 -0.98 -1.63 -1.48 -1.13 ECL 10KH
125 155 -0.98 -1.63 -1.475 -1.105 ECL 10K
125 155 -0.98 -1.63 -1.475 -1.105 MECL III
NM High
mV
NM Low
mV
V
OLmax
V
V
OH max
V
V
ILmax
V
V
IHmin
V
Family
Loading Characteristics
55 55 265 0.5 ECL 100K
22 22 265 0.5 ECL 10KH
22 22 265 0.5 ECL 10K
25 25 350 0.5 MECL III
I
OHmax
mA
I
OLmax
mA
I
IHmax
mA
I
ILmax
mA
Family
Transition Times/ Propagation Delays
300 0.75 0.75 ECL 100K
250 1.8 1 ECL 10KH
NA 3.5 1 - 2.5 ECL 10K (10800)
250 2.5 1.5 ECL 10K
(10200&10600)
160 3.5 2 ECL 10K
(10100&10500)
500 1 1 MECL III
Flip-flop toggle rate
MHz
Edge speed
ns
Prop. delay
ns
Family
Power Consumption
30 40 ECL 100K
25 25 ECL 10KH
4.6 2.3 ECL 10K (10800)
37 25 ECL 10K
(10200&10600)
50 25 ECL 10K
(10100&10500)
60 60 MECL III
Power-speed
product
pJ
Power dissipation
per gate
mW
Family
Key aspects of ECL
Fast and balanced output edges
Low output impedance
High drive capability
Differential or single-ended operation
Limiting factors of ECL
Negative rails
incompatibility with other devices
Need for the terminating rail (V
TT
)
Higher power dissipation
1
ECL Fami l y
The key t o propagat ion delay in bipolar logic family is t o prevent t he t ransist ors in
a gat e from sat urat ing. Schot t ky families prevent t he sat urat ing using Schot t ky
diodes across t he base- collect or j unct ions of t ransist ors. I t is also possible t o
prevent sat urat ing by using a st ruct ure called Current Mode Logic ( CML) . Unlike
ot her logic families considered so far, CML does not produce a large volt age swing
bet ween low and high levels. I nst ead, it has a small volt age swing, less t han a
volt , and it int ernal swit ches current bet ween t wo possible pat hs depending on
t he out put st at e.
The first CML logic family was int roduced by General Elect ric in 1961. The concept
was refined by Mot orola and ot hers t o produce t odays 10K, 100K Emit t er
Coupled Logic ( ECL) families. These ECL families are fast and offer propagat ion
delays as short as 1 ns. I n fact , t hrough out t he evolut ion of digit al circuit
t echnology, some t ype of CML has always been t he fast est commercial logic
family. However commercial ECL families are not nearly as popular as TTL and
CMOS mainly because t hey consume t oo much power. I n fact , high power
consumpt ion has made t he design of ECL super comput ers, such as CRAY as
much of a challenge in cooling t echnology as in digit al design. I n addit ion, ECL
has poor power- speed product , does not provide a high level of int egrat ion, has
fast edge rat es requiring design for special t ransmission line effect , and is not
direct ly compat ible wit h TTL and CMOS. But ECL family cont inues t o survive and
in applicat ions which require maximum speed regardless of cost .
ECL Ci r cui t s
Basi c CML Ci r cui t : The basic idea of current mode logic is illust rat ed by t he
invert er/ buffer circuit in t he figure 1. This circuit has bot h invert ing ( OUT1) and
noninvert ing out put ( OUT2) . Two t ransist ors are connect ed as a different ial
amplifier wit h a common emit t er resist or R3. Let t he supply V
CC
= 5 V, V
BB
= 4 V
and V
EE
= 0 V. I nput Low and High levels are defined t o be 3. 6 and 4. 4 V. This
circuit produces out put Low and High levels 0. 6 V higher ( 4. 2 and 5. 0 V) . When
V
I N
is high t ransist or Q1 is ON, but not sat urat ed, and t ransist or Q2 is OFF. When
Q1 is ON V
E
is one diode drop lower t han V
I N
, or 3. 8 V. Therefore, current t hrough
R3 is ( 3. 8/ 1. 3 K) 2.92 mA. I f Q1 has a of 10, t hen 2. 65 mA of t his cur r ent
comes t hrough t he collect or and R1, so V
OUT1
is 4. 2V ( Low) since t he volt age
across Q1 ( = 4. 2 - 3. 8= 0.4 V) is great er t han V
CEsat ,
,

Q1 is not sat ur at ed Q2 is off
because of it s base t o emit t er volt age ( 4. 0 - 3.8 = 0. 2 V) is less t han 0. 6 V. Thus
V
OUT2
is at 5. 0 V ( High) as no current passes t hrough R2.

2
V
R2
330
R1
300
Q1 Q2 V
V
V
R3
1.3K
OUT1
OUT2
IN
IN
BB
E
V
EE
= 0
= 5V
= 4V

FI G. 1: Basic CML invert er/ buffer circuit
When V
I N
is Low, t ransist or Q1 is OFF, and Q2 is ON but not sat urat ed. V
E
will be
one diode drop below V
BB
( 4. 0 - 0. 6 = 3. 4 V) . The current t rough R3 is ( 3. 4/ 1. 3
K = ) 2. 6 mA. The collect or current of Q2 is 2. 38 mA for a of 10. The volt age
drop across R2 is ( 2. 38 x 0. 33 = ) 0. 5 V, and V
OUT2
is about 4. 2 V. Since t he
collect or emit t er volt age of Q2 is ( 4. 2 - 3. 4 = ) 0. 8V, it is not sat urat ed. Q1 is off
because it s base- emit t er volt age is ( 3. 6 - 3. 4 = ) 0. 2 and is less t han 0. 6 V. Thus
V
OUT1
is pulled up t o 5. 0 V t hrough R1.
To perform logic wit h t he basic unit of figure 1, we simply place addit ional
t ransist ors in par allel wit h Q1. Figure 2 shows a 2- input OR/ NOR gat e. I f any
input is High, t he corresponding input t ransist or is act ive, and V
OUT1
is Low ( NOR
out put ) . At t he same t ime, Q3 is off, and V
OUT2
is High ( OR out put ) . However, t he
circuit shown in figure 2 cannot meet t he input / out put loading requirement s
effect ively.
3

FI G. 2: CML 2- input OR/ NOR gat e
ECL 10K Fami l y: The most popular ECL family is designat ed as t he ECL10K as it
has 5- digit designat ions t o it s I Cs. The ECL 10K OR/ NOR gat e is shown in t he
figure 3

Q1 Q2
V
R3
E E
V
E
Q3
A
B
R1 R2
V
CC 1
=0
D1
D2
R8
4.9k
V
CC2
=0
R6
6.1k
779
50k
R2
R1
50k
245
220

RL1
RL2
V
out1
V
out2

FI G. 3: Two- input ECL 10K OR/ NOR gat e ( 10102)
I n t his circuit , an emit t er follower out put st age shift s t he out put levels t o mat ch
t he input levels and provides very high current driving capabilit y, up t o 50 mA per
out put . An int ernal ( R7, D1, D2, R8 and Q4) t emperat ure, and volt age-
compensat ed bias net work provides V
BB
( - 1. 29V) wit hout t he need for separat e
ext ernal power supply. The family is designed t o operat e wit h V
CC
= 0 ( GND) and
V
EE
= - 5. 2V. This improves noise immunit y t o power supply noise, because noise
4
on V
EE
is a common mode signal t hat is rej ect ed by t he input st ruct ures
different ial amplifier.
A pull down resist or on each input ensures t hat of t he input is left unconnect ed, it
is t reat ed as Low. The emit t er- follower out put s used in ECL 10K require ext ernal
pull- down resist ors as shown in t he figure. This is because of t he fast
t ransmission t imes ( t ypically 2ns) . The short t ransmission t imes require special
at t ent ion as any int erconnect ion longer t han a few cent imet res must be t reat ed
as a t ransmission line. By removing t he int ernal pull- down resist or, t he designer
can now select a resist or t hat sat isfies t he pull- down requirement s as well as
t ransmission line t erminat ion requirement s. The simplest t erminat or for shor t
connect ions is t o use a resist or in t he range of 270 t o 2 K.
ECL SUBFAMI LI ES
Mot orola has offered MECL circuit s in five logic families: MECL I , MECL I I , MECL
I I I , MECL 10000 ( MECL 10K) , and MECL 10H000 ( MECL 10KH) . The MECL I family
was int roduced in 1962, offering 8 ns gat e propagat ion delay and 30 MHz t oggle
rat es. This was t he highest performance from any logic family at t hat t ime.
However, t his family r equired a separat e bias driver package t o be connect ed t o
each logic funct ion. The t en pin packages used by t his family limit ed t he number
of gat es per package and t he number of gat e input s. MECL I I was int roduced in
1966. This family offered 4 ns propagat ion delay for t he basic gat e, and 70 MHz
t oggle rat es. MECL I I circuit s have a t emperat ure compensat ed bias driver
int ernal t o t he circuit s, which simplifies circuit int erconnect ions.
MECL I I I was int roduced in 1968. They offered 1 ns gat e propagat ion delays and
flip- flop t oggle rat es higher t han 500 MHz. The 1 ns rise and fall t imes required a
t ransmission line envir onment for all but t he smallest syst ems. For t his reason, all
circuit out put s are designed t o drive t ransmission lines and all out put logic levels
are specified when driving 50- ohm loads. For t he first t ime wit h MECL, int ernal
input pull down resist ors are included wit h t he circuit s t o eliminat e t he need t o t ie
unused input s t o V
EE
. .
Mot orola int roduced MECL 10K series in 1971 wit h 2 ns propagat ion delays. I n
order t o make t he circuit s comparat ively easy t o use, edge speed was slowed
down t o 3. 5 ns. Subsequent ly, t he basic MECL 10K series has been expanded by
a subset of devices wit h even great er speed. These subfamilies are 10100 and
10500 series ( propagat ion delay of 2 ns, edge speed of 3. 5 ns and flip- flop t oggle
rat e of 160 MHz) , 10200 and 10600 series ( propagat ion delay of 1. 5 ns, edge
5
speed of 2. 5 ns and flip- flop t oggle rat e of 250 MHz) , and 10800 LSI family
( propagat ion delay of 1 - 2. 5 ns and edge speed of 3. 5 ns)
MECL 10KH family was int roduced in 1981. This family provides a propagat ion
delay of 1 ns wit h edge speed at 1. 8 ns. These speeds, which were at t ained wit h
no increase in power over MECL 10K, are due t o bot h advanced circuit design
t echniques and new oxide isolat ed process called MOSAI C. To enhance t he
exist ing syst ems, many of t he MECL 10KH devices are pin- out / funct ional
duplicat ions of t he MECL 10K family. Also, MECL 10K/ 10KH are provided wit h
logic levels t hat are complet ely compat ible wit h MECL I I I . Anot her import ant
feat ure of MECL 10K/ 10KH is t he significant power reduct ion over bot h MECL I I I
and t he older MECL I I . Because of t he power reduct ions and advanced circuit
design t echniques, t he MECL 10KH family has many new funct ions not available
wit h t he ot her families.
The lat est ent rant t o t he ECL family is ECL 100K, having 6- digit part numbers.
This family offers funct ions, in general, different from t hose offered by 10K series.
This family operat es wit h a reduced power supply volt age - 4. 5 V, has short er
propagat ion delay of 0.75 ns, and t ransit ion t ime of 0. 7 ns. However, t he power
consumpt ion per gat e is about 40 mW.
ELECTRI CAL CHARACTERI STI CS OF ECL FAMI LY
The input and out put levels, and noise margins of ECL gat es are given in t he
Table 1. These values are specified at T
A
= 25
o
C and t he nominal power supply
volt age of V
EE
= - 5. 2 V.
TABLE 1: Volt age levels and noise margins of ECL family I Cs

The noise margin levels are slight ly different in High and Low st at es. This
specificat ion by it self does not give complet e pict ure regarding t he noise
immunit y of a syst em built wit h a part icular set of circuit s. I n general, noise
immunit y involves line impedances, circuit out put impedances, and propagat ion
delay in addit ion t o noise- margin specificat ions.
Family V
I Hmin

V
V
I Lmax

V
V
OH

max

V
V
OLmax

V
NM Low
mV
NM High
mV
MECL I I I - 1. 105 - 1. 475 - 1. 63 - 0. 98 155 125
ECL 10K - 1. 105 - 1. 475 - 1. 63 - 0. 98 155 125
ECL 10KH - 1. 13 - 1. 48 - 1. 63 - 0. 98 150 150
ECL 100K - 1. 16 - 1. 47 - 1. 62 - 1. 03 150 130
6
Loadi ng Char act er i st i cs: The different ial input t o ECL circuit s offers several
advant ages. I t s common- mode- rej ect ion feat ure offers immunit y against power-
supply noise inj ect ion, and it s relat ively high input impedance makes it possible
for any circuit t o drive a relat ively large number of input s wit hout det eriorat ion of
t he guarant eed noise margin. Hence, DC fan out wit h ECL circuit s does not
normally pr esent a design problem. Graphs given by t he vendor showing t he
out put volt age levels as a funct ion load current can be used t o det ermine t he
act ual out put volt ages for loads exceeding nor mal operat ion.
Family I
I Lmax

A
I
I Hmax

mA
I
OLmax

mA
I
OHmax

mA
MECL I I I 0. 5 350 25 25
ECL 10K 0. 5 265 22 22
ECL 10KH 0. 5 265 22 22
ECL 100K 0. 5 265 55 55

Tr ansi t i on Ti mes and Pr opagat i on Del ays: The t ransit ion t imes and delays
associat ed wit h different ECL families are given in t he following.

Family Prop. delay
ns
Edge speed
ns
Flip- flop
t oggle rat e
MHz
MECL I I I 1 1 500
ECL 10K
( 10100&10500)
2 3. 5 160
ECL 10K
( 10200&10600)
1. 5 2. 5 250
ECL 10K
( 10800)
1 - 2. 5 3. 5 NA
ECL 10KH 1 1. 8 250
ECL 100K 0. 75 0. 75 300

The rise and fall t imes of an ECL out put depend mainly on t wo fact ors, t he
t erminat ion resist or and t he load capacit ance. Most of t he ECL circuit s t ypically
have a 7 ohm out put impedance and are relat ively unaffect ed by capacit ive
loading on posit ive going out put signal. However, t he negat ive- going edge is
dependent on t he out put pull down or t erminat ion resist or. Loading close t o a ECL
out put pin will cause an addit ional propagat ion delay of 0. 1 ns per fanout load
7
wit h 50 ohm resist or t o - 2. 0 V
dc
or 270 ohms t o - 5. 2 V
dc
. The input loading
capacit ance of an ECL 10K gat e is about 2. 9 pF. To allow for t he I C connect or or
solder connect ion and a short st ub lengt h 5 t o 7 pF is commonly used in loading
calculat ions.
Pow er Consumpt i on: The power dissipat ion of ECL funct ional blocks as
specified by t he manufact urer does not include power dissipat ed in t he out put
devices due t o out put t erminat ion. The omission of int ernal out put pull- down
resist ors permit s t he use of ext ernal t erminat ions designed t o yield best syst em
performance. To obt ain t ot al operat ing power dissipat ion of a part icular funct ional
block in a syst em, t he dissipat ion of t he out put t ransist or, under load, must be
added t o t he circuit power dissipat ion. The power dissipat ion and power- speed
product s of various ECL families are given in t he Table 4

Family
Power dissipat ion
per gat e
mW
Power- speed
product
pJ
MECL I I I 60 60
ECL 10K
( 10100&10500)
25 50
ECL 10K
( 10200&10600)
25 37
ECL 10K ( 10800) 2. 3 4. 6
ECL 10KH 25 25
ECL 100K 40 30

Digital Electronics
Module 4: Combinational Circuits:
An Introduction
N.J. Rao
We are familiar with
How to express a verbal logical statement as a logical
expression
How to simplify a given logical expression using a variety
of tools
How to pictorially represent a logical function in terms of
basic logic functions like AND, OR etc.
How to perform a logical function using electronic circuits
when the binary variables are presented by voltage
levels
Digital electronic circuits
Classified as:
Combinational Circuits
Sequential Circuits
Combinational circuits
The output can be expressed as a logical expression in
terms of the input variables
The present value of the output is dependent only on the
present values of the inputs
All logical expressions consist of logical operations AND,
OR and NOT.
Any logical expression can be realized using these three
types of electronic gates.
Sequential Circuits
In a sequential circuit the outputs depend on
The present inputs
The sequence of all the past inputs
Early era of digital design
logic gates
were built with discrete devices
were expensive
consumed considerable power
occupied significant amount of space on the printed
circuit board.
minimisation of the number of gates was one of the
major design objectives
Present day semiconductor
technology
The integration levels are very high
The delay times are very low and coming down all the
time
Power consumed by them has been coming down.
Minimization of printed circuit board area is the major
design objective
Traditional minimisation methods
Can help in locating problems like hazards and
racing
Combinational SSI, MSI and LSIs
Gates
Multiplexers
Demultiplexers
Arithmetic Units
Encoders and Code Converters
Comparators
Multipliers
Programmable Logic Devices (PLDs)
Hardware aspects: Electrical
Parameters
propagation delays
power consumption
supply voltage levels
currents
tolerances (voltages and currents)
loading
margins (noise)
Hardware aspects: Mechanical
Parameters
Foot print
Type of package
Pin pitch (distance between two adjacent pins)
Thermal resistance
Present day context of
combinational circuits
Interfacing (propagation delay should be minimum)
The number of ICs of SSI and MSI level to be
considerably restricted
Learning Objectives
Analyse and design combinational circuits using
commercially available ICs belonging to LSTTL and
HCMOS/HCTMOS families
Resolve issues related to interfacing
Learn to use Polarized Mnemonic Conventions
Polarized Mnemonic
Convention
Learning objectives
Explain the polarized mnemonic conventions of IEEE for
representing logic variables and signals used in
combinational circuits.
Implement different logic functions with different logic
gates.
Explain the method of representing Mode signals and
binary data unambiguously.
State the advantages of polarized mnemonic convention.
Standard Convention
Polarised Mnemonic Convention and logic symbology as
per IEEE Std. 91/ ANSI Y32.14
The standard convention has two components:
logic notation including signal designation,
symbols for digital functional units, available as SSI and
MSI packages
What is Truth Table?
$ % ;

Consider the OR function of two binary variables
Algebraic representation: Y = A + B
Truth table Logic Symbol
It is simply a listing of the possible combinations of A and B
Has nothing to do with truth or falsehood of the variables
Appropriate to treat it as the input-output relation
Logic variables represent Action
Examples of digital signals: START, LOAD, CLEAR etc.
These are indicative of actions to be performed
We do not establish Truth or Falsehood of something
It is appropriate to say
when the signal LOAD is Asserted, the intended action
of loading takes place
Asserted/ Not Asserted qualification is more
appropriate
Interpretation of Truth Table
Entry 0: The variable Not Asserted
Entry 1: The variable Asserted
A B X
0 0 1
0 1 0
1 0 0
1 1 0
Read the first entry as
"X is Asserted when A AND B are Not Asserted" or
"X is Asserted when A is Not Asserted AND B is Not
Asserted".
Reading Logic Expressions
Consider Y = A. B
/
. C + A. B. C + A. B
/
. C
/
The first term A.B
/
.C is to be read as "A B prime C",
It is to be interpreted as "A Asserted AND B Not
Asserted AND C Asserted"
A Not Asserted variable is shown in a logical expression
with a prime (
/
) next to the mnemonic for the variable.
Electronic Circuits and Logic
Functions
Electronic circuits are used to implement logic functions
Currents and voltages are associated with these circuits
Assertion and Not Assertion are associated with voltages
Need to have a convention to associate voltages with
logic variables
Signal Convention
The voltage levels associated with logic variables are not
of a single value
Normally a band of few hundred milli volts or even a few
volts are associated with a logic state
The more positive of the two voltage levels (voltage
ranges) is designated as High Voltage (H)
The less positive of the two is designated as Low
Voltage (L)
The intended action can take place at either of the
voltage level
This choice can be given to the designer
Signal Convention(2)
Asserted High Signal
It is Asserted when the voltage level is High (H) and Not
Asserted when the voltage level is Low (L)
Asserted Low Signal
It is Asserted when its voltage level is Low (L) and Not
Asserted when the voltage level is High (H)
Convention
No qualifying symbol or letter is added if the variable is
Asserted High
LOAD, CLR etc.
/ is added before the mnemonic if the variable is
Asserted Low
/LOAD, /CLR
Logic Gates
Refer to physical electronic units that generate output
voltage levels in a well-defined relationship to the input
voltage levels
A given gate may perform a variety of logical functions
2-Input AND Gate
H H H
L L H
L H L
L L L
Y B A
&
AND Gate with AH variables
1 1 1
0 0 1
0 1 0
0 0 0
Y B A
The Truth-Table gets modified as
X is Asserted only when A AND B are Asserted
This AND gate performs AND operation on the two input variables
which are Asserted High to produce an output that is Asserted High
AND Gate with AL variables
0 0 0
1 1 0
1 0 1
1 1 1
/Y /B /A
/Y is Asserted when /A is Asserted OR /B is Asserted
This AND gate performs OR operation on the two input variables
which are Asserted Low to produce an output that is Asserted Low
2-Input OR Gate
H H H
H L H
H H L
L L L
Y B A
>
OR Gate with AH variables
1 1 1
1 0 1
1 1 0
0 0 0
Y B A
X is Asserted only when A OR B are Asserted
This OR gate performs OR operation on the two input variables
which are Asserted High to produce an output that is Asserted High
OR Gate with AL variables
0 0 0
0 0 1
0 1 0
1 1 1
/Y /B /A
/Y is Asserted when /A is Asserted AND /B is Asserted
This OR gate performs AND operation on the two input variables
which are Asserted Low to produce an output that is Asserted Low
Logic Convention
Positive Logic Convention: When all variables are
treated as Asserted High
Negative Logic Convention: When all variables are
treated as Asserted Low
Polarised Mnemonic Convention permits the designer to
have complete freedom in defining the Assertion levels
of all signals
Negation/Polarity Indicator
As per the IEEE Standard "o" (bubble) or a (small
triangle) is used as a negation/polarity indicator
We use the bubble to represent polarity
Output Signals
Incorrect examples
Presence of the polarity indicator at the output: The signal
is as Asserted Low
Absence of the indicator at the output: The signal is as
Asserted High
Correct examples
Input Signals
Polarity indicator at the input of a logic unit
If an Asserted High (AH) variable is given as input to a
logic unit without polarising indicator, that variable
appears Asserted in the output logic expression.
If an Asserted Low (AL) signal connected through a
polarity indicator, that variable appears as Asserted in
the output logic expression.
Input Signals (2)
Asserted Low signal /LOCK and an Asserted High
signal PTRL are ANDed to generate an Asserted Low
output signal /STRT.
Input Signals (3)
An AL variable connected to a logic unit without a
polarity indicator appears as Not Asserted variable in the
logic expression for the output.
An AH variable connected through a polarity indicator
appears as Not Asserted variables in the logic
expression for the output.
Examples of Input Signal
Designations
/PRINCA = MINI
/
.CLR
/
.SEQ A CLR
SEQ A

MINI
PRINCA = MINI.MA.CLR
/

MINI
MA
CLR
/PRIN1
/PRIN2
PRIN=PRIN1
/
+PRIN2
Logic symbols in the Polarised
Mnemonic Notation
The presence or absence of polarity indicators at
the outputs.
The presence or absence of polarity indicators at
the inputs.
Each symbol has three distinct elements:
Distinctive shaped logic symbol indicative of the logic
operation being performed,
for AND for OR
Example
The unit performs AND operation.
The output variable is Asserted Low.
The AND operation is performed on the Asserted Low
input signals
Some good practices
The use of symbols as shown should be avoided.
Exceptions
Mode Signals
Assigning Assertion levels is not meaningful
These signals are indicative of more than one action.
Different actions take place in both the states of the
signals.
The two actions are mutually exclusive and one of the
actions is always implied
Examples are R/W
/
, U/D
/
and IO/M
/
.
Read/Write (R/W) signal
R/W
/
:
when the signal takes `High voltage' (H) it is indicative of
READ operation
when it takes `Low voltage' (L) it is indicative of WRITE
operation
Binary Data
We can not use Asserted or Not Asserted conventions
with binary data
Data line will either convey a numerical value of 0 or 1.
A data line, designated with mnemonics like DBIT-4
When it takes High voltage it is considered having a
numerical value of 1
When it takes Low voltage it is considered having a
numerical value of `0'.
Unused Inputs
All inputs of an IC may not be utilized
Unused inputs will have to be tied at known states.
In a 3-input OR gate that is used only as a 2-input OR
gate, the unused input should be kept in Not Asserted
state.
A high voltage input is shown by the letter H and a low
voltage input is shown by the letter L.
Examples of unused inputs
The voltage level at which the unused inputs get tied
to will depend on the assertion level of the signal.
COMBI NATI ONAL CI RCUI TS
I NTRODUCTI ON
We explored in t he earlier learning unit s
How t o express a verbal logical st at ement as a logical expression
How t o simplify a given logical expression using a variet y of t ools
How t o pict orially represent a logical funct ion in t erms of basic logic funct ions like
AND, OR et c.
How t o perform a logical funct ion using elect ronic circuit s when t he binary
variables are present ed by volt age levels
An elect ronic circuit can perform a logical funct ion in ext remely short periods of t ime
( t ime t aken from t he applicat ion of input s t o t he appearance of out put s) . These
periods are of t he order of nanoseconds. We mainly use elect ronic circuit s t o perform
logic funct ions because of t heir high speeds.
The elect ronic circuit s t hat perform logical funct ions are seen under t wo broad
cat egories:
o Combinat ional
o Sequent ial
The out put of a combinat ional circuit can be expressed as a logical expression in
t erms of t he input variables. The present value of t he out put of a combinat ional
circuit is dependent only on t he present values of t he input s.
The logical expressions mainly consist of logical operat ions AND, OR and NOT.
Therefore, it is possible t o physically realise any logical expression using t hese t hree
t ypes of elect ronic gat es.
I n t he early era of digit al design logic gat es built wit h discret e devices, were
expensive, consumed considerable power and occupied significant amount of space
on t he print ed circuit board on which t hese devices were mount ed. I n t hose early
days t he minimisat ion of t he number of gat es was one of t he maj or design obj ect ives
of Logic and Swit ching Theory. The semiconduct or t echnology, however, made t hese
gat es available in I C packages t hat occupy very lit t le space and at very low cost s. As
t he t echnologies improved
The delay t imes associat ed wit h t he logical devices have been coming down
Power consumed by t hem has been coming down.
More and more logic funct ions are get t ing int egrat ed int o a single package.
This has drast ically reduced t he number of I Cs needed t o realise a given funct ion.
But t he proport ional cost of t he print ed circuit board on which t hese devices were
get t ing assembled has been increasing. Therefore, one of t he main obj ect ives of t he
present day combinat ional circuit design is t o reduce t he print ed circuit board area
needed for t he logic circuit s. This implies reduct ion of t he number of I C packages
used rat her t han t he number of gat es.
Because of t hese changes in t echnologies, t he design and minimisat ion met hods
evolved by t he t radit ional Logic and Swit ching Theory are not t hat relevant . I t may
not be necessary t o mast er t he finer aspect s of t hese met hods, but a good working
knowledge of t hese met hods is st ill needed t o analyse and design combinat ional
circuit s, even as per t he new crit eria. Besides minimisat ion, t hese met hods can
great ly help in locat ing problems like hazards and racing, which are mainly t he
consequence of variat ions in t he elect rical charact erist ics of t he physical devices
used.
Combinat ional int egrat ed circuit s are available in a wide funct ional and complexit y
range in SSI , MSI and LSI packages. These may be classified as:
Gat es
Mult iplexers
Demult iplexers
Arit hmet ic Unit s
Encoders and code convert ers
Comparat ors
Mult ipliers
Programmable Logic Devices ( PLDs)
A digit al designer must get himself t horoughly familiar wit h t he funct ional and
hardware aspect s of t hese combinat ional I Cs. The hardware aspect s relat e t o
elect rical paramet ers
propagat ion delays
power consumpt ion
supply volt age levels
current s
t olerances ( noise, volt ages and current s)
loading
Mechanical paramet ers are also import ant . These include
foot print
t ype of package
pin pit ch ( dist ance bet ween t wo adj acent pins)
t hermal resist ance
The design of any digit al circuit is not merely limit ed t o t he funct ional aspect s. For
example t he combinat ional circuit s find applicat ions, in t he cont ext of t he present
day microprocessors, mainly for t he int erfacing applicat ions. I n such applicat ions t he
propagat ion delay should be made minimum. The designer will have t o use less
number of levels of gat ing and choose t he appropriat e logic family. Wit h t he real
est at e at t he print ed circuit board level becoming more and more expensive t he
number of I Cs of SSI and MSI level have t o be considerably rest rict ed.
I n t his module you will mainly learn t o analyze and design combinat ion circuit s using
commercially available Gat es, Arit hmet ic Unit s, Mult iplexers, and Demult iplexers
belonging t o bot h LSTTL and HCMOS/ HCTMOS families. The issues relat ed t o
int erfacing bet ween circuit s belonging t o different logic families, as well as
int erfacing wit h ext ernal world are also addressed.
As t here are t wo logic st at es and t wo volt age levels t o represent t hem elect rically,
communicat ion among digit al designers can become very confusing if well- accept ed
convent ions do not exist . I EEE evolved st andards for Logic Convent ion and
Dependency Not at ion for Medium Scale I nt egrat ed Circuit s. While t hese convent ions
and not at ions have limit ed ut ilit y when working wit h t he present day PLDs and
FPGAs, it is advant ageous t o adhere t o t hem whenever it is possible.
I nit ially we will clarify issues relat ed t o logic and signal convent ions, and t hen
proceed t o designing a variet y of combinat ional circuit s.
The obj ect ives of t his learning unit are
Explain t he polarized mnemonic convent ions of I EEE for represent ing logic
variables and signals used in combinat ional circuit s.
I mplement different logic funct ions wit h different logic gat es.
Explain t he met hod of represent ing mode signals and binary dat a
unambiguously.
St at e t he advant ages of polarized mnemonic convent ion.
POLARI ZED MNEOMONI C CONVENTI ON
You need t o present your solut ion t o a design problem in t he form of a schemat ic
diagram. This schemat ic diagram will be used by t he packaging designer t o convert it
int o product ion document at ion. The schemat ic will also be used by t he t est ing and
maint enance engineers. This int eract ion among many people concerned wit h a
digit al syst em requires t hat all of t hem have t he same underst anding of t he
funct ionalit y of t he circuit . Therefore, we need a st andard convent ion t hat
unambiguously conveys t he int ent ions of t he designer t o all t he concerned while
giving sufficient flexibilit y t o t he designer. Many such convent ions were evolved in
different t ext books and by different organisat ions. However, no universally accept ed
convent ion exist s even t oday for drawing digit al schemat ic diagram.
Polarised Mnemonic Convent ion and logic symbology as per I EEE St d. 91/ ANSI
Y32. 14, which is based on Dependency Not at ion, is t he only int ernat ional St andard
t hat has evolved. Here we get ourselves familiar wit h t his convent ion.
Any st andard convent ion has t wo component s:
logic not at ion including signal designat ion,
symbols for digit al funct ional unit s, available as SSI and MSI packages
You are only familiar wit h t he simple logic funct ions and logic gat es. You are urged
t o make effort s t o confine t o t he convent ions present ed here, rat her t han resort ing
t o except ions. The reward for t his addit ional effort is t he abilit y t o communicat e
your design t o ot hers. As you work out more and more examples from t he lat er
Modules, you should feel more comfort able wit h t he convent ion.
Consider an OR funct ion of t wo binary variables A and B.
I t s algebraic represent at ion is
Y = A + B
I t s t rut h t able represent at ion is
A B X
0 0 0
0 1 1
1 0 1
1 1 1
The symbolic represent at ion is

The t rut h t able present s a simple list ing of t he possible combinat ions of A and B
rat her t han having anyt hing t o do wit h t rut h or falsehood of t he variables concerned.
I t will be more appropriat e if t he t rut h t able can be int erpret ed more as t he input -
out put relat ion of a logic funct ion. Wit h t his underst anding we will cont inue t o use
t he word t rut h t able.
A digit al syst em may more convenient ly be considered as a unit t hat processes
binary input act ions and generat es binary out put act ions. Most hardware responses
generally are eit her responses t o some physical operat ion or some condit ions
result ing from physical act ion. For example many of t he signals t hat you come
across in digit al syst ems are of t he t ype
START
LOAD
CLEAR
These signals are indicat ive of act ions t o be performed rat her t han est ablishing t he
Trut h or Falsehood of somet hing.
For example, t o say when LOAD is t rue does not convey t he int ended meaning. I t
appears more appropriat e t o say when t he signal LOAD is Assert ed, t he int ended
act ion, namely, loading t akes place.
Therefore, Assert ed/ Not Assert ed qualificat ion is more meaningful and appropriat e
t han t he True/ False qualificat ion in t he case of signals t hat clearly indicat e act ion.
The ent ries in t he t rut h t able can now be int erpret ed in a different manner.
The ent ry 0 is t o be read as t he corresponding variable Not Assert ed
The ent ry 1 is t o be read as t he corresponding variable Assert ed
Consider t he Trut h Table given in t he following.
A B X
0 0 1
0 1 0
1 0 0
1 1 0

We read t he first ent ry in t he t able as
"X is Assert ed when A AND B are Not Assert ed" or "X is Assert ed when A is Not
Assert ed AND B is Not Assert ed".
Consider anot her example
Y = A. B
/
. C + A. B. C + A. B
/
. C
/

The first t erm A. B
/
. C, t o be read as "A B prime C", is t o be int erpret ed as "A Assert ed
AND B Not Assert ed AND C Assert ed"
Try int erpret ing t he ot her t erms of t he expression.
A Not Assert ed variable will t herefore be shown in a logical expression wit h a prime
(
/
) next t o t he mnemonic for t he variable. Tradit ionally t his is referred t o as
complement at ion. Let us not e t hat it sounds right , and is appropriat e t o say a
variable is Assert ed or Not Assert ed rat her t han Uncomplement ed or Complement ed.
El ect r oni c Ci r cui t s and Logi c Funct i ons
We use elect ronic circuit s t o implement logic funct ions. There are current s and
volt ages associat ed wit h t hese circuit s. We now explore t he issues relat ed t o
associat ing elect rical variables wit h logic variables.
Si gnal Conv ent i ons
I n an act ual digit al circuit t he logic variables are represent ed as volt age levels.
However t hese volt age levels are not of a single value. Normally a band of few
hundred millivolt s or even a few volt s will be associat ed wit h a logic st at e.
The more posit ive of t he t wo volt age levels ( volt age ranges) is designat ed as High
Volt age ( H)
The less posit ive of t he t wo is designat ed as Low Volt age ( L) .
The int ended act ion associat ed wit h a variable can t ake place at eit her of t he volt age
levels. This can be given as a choice t o t he designer. I f t he choice is t o be made
available, it is necessary t o evolve a convent ion t hat unambiguously st at es at what
volt age level a variable get s Assert ed.
I f a signal is considered Assert ed when t he volt age level is High ( H) and Not Assert ed
when t he volt age level is Low ( L) , it is designat ed as Assert ed High signal.
Similarly if a signal is considered Assert ed when it s volt age level is Low ( L) and Not
Assert ed when t he volt age level is High ( H) , it is designat ed as Assert ed Low signal.
We will follow a simple convent ion:
No qualifying symbol or let t er is added if t he variable is Assert ed High, for example
LOAD, CLR et c.
/ is added before t he mnemonic if t he variable is Assert ed Low, for example / LOAD,
/ CLR

Logi c Gat es
Logic gat e refers t o a unit of hardware t hat generat es out put volt age levels in a well-
defined relat ionship t o t he input volt age levels. A given gat e may perform a variet y
of funct ions depending upon t he Assert ion levels of t he input and out put signal
levels.
Consi der an AND Gat e
Figure shows a t wo input AND gat e and t he relat ionship bet ween t he input and
out put volt age levels.

Let us assume t he input and out put variables are Assert ed High. The corresponding
t rut h t able can be writ t en as;
A B X
0 0 0
0 1 0
1 0 0
1 1 1

We can draw t he following conclusions from t his t rut h t able:
X is Assert ed only when A AND B are Assert ed
This AND gat e performs AND operat ion on t he t wo input variables which are Assert ed
High t o produce an out put t hat is Assert ed High.
I f A, B and X are Assert ed Low variables, t hen t he t rut h- t able for t he same gat e
would be
/ A / B / X
1 1 1
1 0 1
0 1 1
0 0 0

From t he t rut h t able we not ice t hat
/ X is Assert ed when / A is Assert ed OR / B is Assert ed.
This AND gat e performs OR operat ion on it s input variables which are Assert ed Low.
Consi der an OR gat e
Figure shows a t wo input OR gat e and t he relat ionship bet ween t he input and out put
volt age levels

I f A, B and X are Assert ed High, t hen t he t rut h- t able can be writ t en as
A B X
0 0 0
0 1 1
1 0 1
1 1 1

We can draw t he following conclusions from t his t rut h t able:
X is Assert ed when A OR B is Assert ed,
This gat e performs OR operat ion on t he Assert ed High variables.
When t he variables A, B and X are Assert ed Low, t he Trut h Table can be writ t en as

/ A / B / X
1 1 1
1 0 0
0 1 0
0 0 0

/ X is Assert ed only when / A AND / B are Assert ed
This gat e performs AND operat ion on Assert ed Low variables.
I n a similar manner each one of t he available hardware gat es can be used t o
perform more t han one logic operat ion. From t hese t wo examples it is clear t hat t he
name given t o t he hardware gat e corresponds t o t he funct ion it performs on
Assert ed High input s t o generat e an Assert ed High out put .
Exercises:
1. Find out t he funct ion performed by a 2- input NAND gat e if it s input and
out put variables are Assert ed High?
2. Find out t he funct ion performed by a 2- input NAND gat e if it s input and
out put variables are Assert ed Low?
3. Find out t he funct ion performed by a 2- input NAND gat e if it s input variables
are Assert ed High and it s out put variable is Assert ed Low?
4. Find out t he funct ion performed by a 2- input NOR gat e if it s input and out put
variables are Assert ed High?
5. Find out t he funct ion performed by a 2- input NOR gat e if it s input and out put
variables are Assert ed Low?
6. Find out t he funct ion performed by a 2- input NOR gat e if it s input variables
are Assert ed High and it s out put variable is Assert ed Low?
7. Find out t he funct ion performed by a 2- input Ex- NOR gat e if it s input and
out put variables are Assert ed High?
8. Find out t he funct ion performed by a 2- input EX- NOR gat e if it s input and
out put variables are Assert ed Low?
9. Find out t he funct ion performed by a 2- input NOR gat e if one of it s input
variables is Assert ed High and t he ot her is Assert ed Low, and it s out put
variable is Assert ed High?

LOGI C CONVENTI ON
Logic variables can be Assert ed High or Assert ed Low. Therefore, depending on our
preference we can have different convent ions.
I f all variables are t reat ed as Assert ed High, we call it as Posit ive Logic
Convent ion. Tradit ionally digit al circuit s were most ly designed wit h Posit ive
Logic Convent ion.
I f all variables are t reat ed as Assert ed Low, we call it as Negat ive Logic
Convent ion. Somet imes designers found it convenient t o design some part s of
a digit al circuit using Negat ive Logic Convent ion.
Whenever it became necessary t o combine circuit s designed under different
convent ions t here were always possibilit ies of confusions in handling t he int erface.
I f t he Assert ion level a signal can be chosen by t he designer we call it Polarised
Mnemonic Convent ion.
Negat ion/ Polarit y I ndicat or: As per t he I EEE St andard "o" ( bubble) or a ( small
t riangle) is used as a negat ion/ polarit y indicat or as shown in t he figure 1.

FI G. 1: Convent ion for indicat ing t he negat ion of t he out put
We prefer t o use t he "o" ( bubble) as t he negat ion/ polarit y indicat or.
Out put Si gnal s:
The absence of t he polarit y indicat or at t hat out put of a logic unit defines t hat
signal at t hat point as Assert ed High.
The presence of t he polarit y indicat or at t he out put of a logic unit defines t he
signal at t hat point as Assert ed Low
Typical correct examples are shown in t he figure 2.

/CLR STRT

FI G 2: Correct met hod of indicat ing t he polarit ies of t he out put s
I t is incorrect
To designat e an out put signal as Assert ed High if t he polarit y indicat or is
present
To designat e a signal as Assert ed Low if no polarit y indicat or is present
Examples of incorrect designat ion, which should never be used, are given in t he
figure 3.
/CLR STRT

FI G. 3: I ncorrect met hod of indicat ing t he out put polarit ies
I nput Si gnal s:
The usage of polarit y indicat or at t he input of a logic unit depends on whet her t he
variable connect ed t o t hat input appears in t he logic expression for t he out put
variable, as Assert ed or Not Assert ed.
I f an Assert ed High ( AH) variable is given as input t o logic unit wit hout polarising
indicat or, t hat variable appears Assert ed in t he out put logic expression.
I f an Assert ed Low ( AL) signal connect ed t hrough a polarit y indicat or, t hat
variable appears as Assert ed in t he out put logic expression.
I n t he example shown in t he figure an Assert ed Low signal / LOCK and an Assert ed
High signal PTRL are ANDed t o generat e an Assert ed Low out put signal / STRT.
/STRT
/LOCK
PTRL

An AL variable connect ed t o a logic unit wit hout a polarit y indicat or appears as
Not Assert ed variables in t he logic expression for t he out put .
An AH variable connect ed t hrough a polarit y indicat or appears as Not Assert ed
variables in t he logic expression for t he out put .
Some examples are shown in t he figure 4.

/PRINCA = MINI
/
.CLR
/
.SEQ A CLR
SEQ A

MINI
PRINCA = MINI.MA.CLR
/

MINI
MA
CLR
/PRIN1
/PRIN2
PRIN=PRIN1
/
+PRIN2

FI G. 4: Examples of logic funct ions drawn as per polarized mnemonic convent ion
I n int erpret ing t he logic symbols in t he Polarised Mnemonic Not at ion each symbol
can be considered t o have t hree dist inct element s:
Dist inct ive shaped logic symbol indicat ive of t he logic operat ion being
performed,

for AND for OR.
y The presence or absence of polarit y indicat ors at t he out put s.
y The presence or absence of polarit y indicat ors at t he input s.
Consider t he following symbol;

The unit performs AND operat ion.
The out put variable is Assert ed Low.
The AND operat ion is performed on t he Assert ed Low input signals.
Some good pr act i ces:
Though incompat ibilit y at t he input s of any logic funct ional unit is permissible, it s
usage should be avoided in t he case of invert ers as it is likely t o lead t o unnecessary
confusions wit hout offering any advant age. The use of symbols shown in t he
following figure should be avoided.

CLR
/CLR
/LOAD LOAD

Ex cept i ons:
Mode Si gnal s: There is one class of signals, designat ed as MODE signals, for which
assigning Assert ion levels is not meaningful. These signals are indicat ive of more
t han one act ion. Different act ions t ake place in bot h t he st at es of t he signals.
Typical examples are R/ W
/
, U/ D
/
and I O/ M
/
.
I n t he case of R/ W' , when t he signal t akes ` High volt age' ( H) it is indicat ive of READ
operat ion, and when it t akes ` Low volt age' ( L) it is indicat ive of WRI TE operat ion.
These t wo operat ions are mut ually exclusive and one of t he operat ions is always
implied.
UP/ DOWN
/
signal is encount ered in t he count ers. When U/ D' t akes H t he count er
count s up, and when it t akes L t he count er count s down.
Usage of such signals should be kept t o a minimum. A more convenient way of
designat ing such signals is t o say MODE 0, MODE 1 et c.
Bi nar y Dat a: Digit al syst ems process binary dat a besides binary signals. I t does
not sound appropriat e t o st at e t hat a dat a bit is Assert ed or Not Assert ed. The line
will assume High or Low volt age values as per t he numerical value of t hat dat a bit .
I n t his sense it is more like t he mode signal, which implies different act ions in
different st at es of t he signal. I n t his case of dat a line it will eit her convey a
numerical value of 0 or 1. A dat a line, designat ed wit h mnemonics like DBI T- 4, is
always Assert ed High signal, i. e. , when it t akes High volt age it is considered having a
numerical value of 1 and when it t akes Low volt age it is considered having a
numerical value of ` 0' .
Unused I nput s: I nt egrat ed circuit s are available in st andard SSI and MSI packages.
These I Cs are designed t o have widest possible applicabilit y. Therefore, all t he
input s and capabilit ies may not be used every t ime an I C is incorporat ed int o a
circuit . The unused input s of such I C gat es as well as sequent ial circuit s will have t o
be t ied at known st at es. For example, if a 3- input OR gat e is used only as a 2- input
OR gat e, t he unused input should be kept in Not Assert ed st at e. This may
correspond t o a high volt age or a low volt age. A high volt age input is shown by t he
let t er H and a low volt age input is shown by t he let t er L. A few examples wit h gat es
are shown in t he figure 5.
L
A1
B2
L
/A2
/B1

H
A1
B1

FI G. 5: Examples of designat ing unused input s
The volt age level at which t he unused input s get t ied t o will depend on t he assert ion
level of t he signal.

Digital Electronics
Logic Functions
N.J. Rao
Implementation of Logic Functions
Logic functions can be implemented in any one of the
available logic families
LSTTL and HCMOS family ICs are used for the medium
frequency applications
FAST series and Schottky series ICs are used at higher
frequencies
With
LSIs are becoming popular
Cost per gate coming down drastically
Need for conventional type of minimisation is much less
Tractability of the design becomes more important
Combinational ICs
Gates are available as SSIs
Adders, multiplexers, comparators and encoders are
available as MSIs
SSI gates are mainly used for realising simple logic
functions normally encountered in interconnecting LSI
and MSI circuits.
Available Gates
LSTTL FAST HCMOS
54/74LS 54/74F 54/74HC
NAND Gates
Quad 2-input NAND 00 00 00A
Triple 3-input NAND 10 10 10
Dual 4-input NAND 20 20 20
8-input NAND 30 --- 30
13-input NAND 133 --- 133
NOR Gates
Quad 2-input NOR 02 02 02A
Triple 3-input NOR 27 --- 27
Available Gates (2)
LSTTL FAST HCMOS
54/74LS 54/74F 54/74HC
AND Gates
Quad 2-input AND 08 08 08A
Triple 3-input AND 11 11 11
Dual 4-input AND 21 21 ---
OR Gates
Quad 2-input OR 32 32 32A
Inverters
Hex inverter 04 04 04A
Gate level implementation of logic
functions
Logical expressions are available either in the SOP form
POS form.
Consider the expression:
STRT = PTRL.IGNI.NEUTR
/
.KICK + PTRL.IGNI.SLOP.
NEUTR
/
.LOCK
/
It is not in canonical form
It can be realized by AND, OR and INVERT gates
Realization by AND, OR and invert
Gates
Using commercially AND,OR and
NOT gates
1(875
,*1,
375/
/2&.
6/23
.,&.
6757
+
We need a 3-level gating and it increases delay
Realization by AO gates
AOI gates
Dual 2-wide 2-input AOI 7451/LS51/S51/
HC51
Expandable Dual 2-input 2-wide AOI 7450
Expandable 2-wide 4-input AOI 74LS55
4-wide 2-input AOI 7454/LS54
Triple 3-input Expander 7461
Dual 4-input Expander 7460
4-2-3-2 input AOI 74S64
Realization by AOI gates
It does not necessarily reduce the chip count
LSTTL family does not offer many varieties of AO or AOI
gates.
Realization of SOP form by NANDs
NAND and INVERTER realization
Realization of POS form by NOR
gates
STRT = PTRL+IGNI+NEUTR+KICK) .
(PTRL+IGNI+SLOP+NEUTR+LOCK)
Ex-OR realization
Parity checker
EP = A B C D E
Its canonical version
EP =A B C D E + A B C
/
D
/
E + A B C
/
D E
/
+ A B
C D
/
E
/
+ A
/
B
/
C
/
D
/
E + A
/
B
/
C
/
D E
/
+
A
/
B
/
C D
/
E
/
+ A
/
B
/
C D E +A B
/
C
/
D
/
E
/
+
A B
/
C D E
/
+ A B
/
C D
/
E + A B
/
C
/
D E +
A
/
B C
/
D
/
E
/
+ A
/
B C D E
/
+ A
/
B C D
/
E +
A
/
B C
/
D E
Parity checker with Ex-OR
74LS86/HC86s (Quad 2-input EX-OR)
Multiple levels
At this stage of design
Choice of gates in realising logical expressions should be
based on
number of chips needed to realize the expression
number of varieties of chips to be kept in the inventory
number of levels of gating (the maximum number of
gates that an input signal has to pass through in a
circuit) needed to realize the expression
Delay
Input-Output relationship of an inverter
Manufacturers specifications
74LS04
TYP MAX
t
PHL
- 9.5 15 ns
t
PLH
- 9.5 15 ns
Typical value is not a guaranteed value and hence
cannot be used as a design parameter
The designer has to work with the worst case values for
these propagation delays
Manufacturers do not guarantee any minimum delay
Problems of minimum delay
Digital differentiator
What will be the width of the output pulse?
With typical values: 9.5 x 3 = 28.5 ns.
With maximum values: 15 x 3 = 45 ns.
It can be any value from 0 to 45 ns.
Such a circuit cannot be used
Delays and different realizations
Expression in SOP form can be realized
By 2-level gating if the variables are available in their
Asserted High and Asserted Low versions
By 3-level gating if the variables are not available in their
Asserted High and Asserted Low versions
In all other forms the delay is likely to be more
Expression in non-canonical form
STRT = PTRL. IGNI. ([NEUTR.KICK] +
[SLOPE.NEUTR
/
.KICK
/
])
Minimization of propagation delay may not always be
a design objective.
The form of the expression may be chosen to make
the design more easily understandable.
Specification of delay
Normally the delays for LSTTL family are defined at
T = 25o C, V = 5 volts, C = 15 pF, and R = 2 K
For HCMOS family the delay times are specified at nine
operating points (three voltages and three temperatures)
V
CC
= 2.0 V, T: 25o C to -55o C, < 85
o
C, and < 125
o
C,
C
L
= 50 pF, Input t
r
= t
f
= 6 ns
V
CC
= 4.5 V, T: 25o C to -55o C, < 85
o
C, and < 125
o
C,
C
L
= 50 pF, Input t
r
= t
f
= 6 ns
V
CC
=6.0 V, T: 25o C to -55o C, < 85
o
C, and < 125
o
C,
C
L
= 50 pF, Input t
r
= t
f
= 6 ns
Test circuit
Test circuit with which these delays are measured
V
cc
V
cc
V
out
D
DUT
Load capacitance
Depends on
PCB track width and the length,
material of the laminate.
It varies from 20 pF to 150 pF.
Its effect is
to increase the propagation delay
to increase supply current spike amplitude during the
transients
Depending on the load circuit, capacitive loading and
temperature the propagation delays can increase by as
much as 15 ns.
Dependence of the propagation
delay
Its dependence on the load capacitance
2 0 6 0 100 140
180
p F
1 0
2 0
3 0
C Load Capaci tance
T
t
t
PHL
PLH
( 25
o
(25 C)
o
D
e
l
t
a

T
u
r
n

o
n

d
e
l
a
y

(
n
s
e
c
)

C)
Glitches in the outputs
The output is considered only after all the transients that
are likely to be produced when the state of the inputs
signals change.
Finite delays make the transient response of a logic
circuit different from steady state behaviour.
These transients occur because different paths from
input to output may have different propagation delays.
These differences in the propagation delays can produce
short pulses, known as glitches.
The steady state analysis does not predict this
behaviour.
Hazard
A hazard is said to exist when a circuit has the possibility
of generating a glitch.
The actual occurrence of the glitch and its pulse width
depend on the exact delays associated with the actual
devices used in the circuit.
Designer has no control over this parameter
It is necessary to design that avoids the occurrence of
glitches.
One simple method is not to look at the outputs until they
settle down to their final value.
Example
Consider the expression X = A B
/
+ BC
/
D
/
Detection of hazard
Hazard is caused by the propagation delay associated with the gate-1
Let A and B be Asserted and C and D are Not-asserrted.
When B changes from its Asserted state to its Not-asserted state with
the other variables remaining the same the output should remain in its
Asserted state.
When B changes from 1-to-0 the output of the gate-5 changes from
1-to-0.
The output of the gate-4 should change from 0-to-1 at the same time.
But the delay associated with the gate-1 makes this transition of the
gate-4 output to happen a little later than that of gate-5.
This can cause brief transition of X from 1-to-0 and then from 0-to-1
Types of Hazards
Static-1 hazard: When the output is expected to
remain in state 1 as per the steady state analysis it
makes a brief transition to 0
Static-0 hazard: When the output is expected to
remain in state 0 as per the steady state analysis it it
makes a brief transition to 1.
Dynamic hazard: When the output is supposed to
change from 0 to 1 (or 1 to 0), the circuit may go
through three or more transients to produce more
than one glitch
Analysis using K-Map
X = A B
/
+ BC
/
D
/
Hazard associated with the
1-to-1 transition occurred
when the change of state of
the variable B caused the
transition from one grouping
BC
/
D
/
to another grouping
AB
/
.
Detection of other hazards
It is more difficult to detect the other three transitions.
One result from Logic and Switching Theory states that a
two level gate implementation of a logical expression will
be hazard free for all transitions of the output if it is free
from the hazard associated with 1-to-1 transition.
When the input variables change in such manner as to
cause a transition from one grouping to another
grouping, the 1-to-1 transition can occur
Eliminating hazards
In a two level gating realization of a
logical expression include all 1s which
are unit distance apart at least in one
grouping
Group the terms ABC
/
D
/
and AB
/
C
/
D
/
together
This would lead to an additional gate
The added gate defines the output
during the transition of B from one state
to the other
Hazard free realization
X = AB
/
+ BC
/
D
/
X = AB
/
+ BC
/
D
/
+ AC
/
D
/
Loading
A logic gate has limited capacity to source and sink
current at its output.
The output current capability of LSTTL gate is
I
OH
= - 400 mA at V
OH
= 2.7 volts
I
OL
= 4 mA at V
OL
= 0.4 volts
= 8 mA at V
OL
= 0.5 volts
I
IH
= 20 mA
I
IL
= -0.4 mA
At V
OL
= 0.4 V LSTTL gates have 2.5 UL capability and
can drive 10 LSTTL gates
At V
OL
= 0.5 V LSTTL gates have 5UL capability and can
drive 20 LSTTL gates
HCMOS gates
I
in
= + 0.1 A at V
CC
= 6.0 V
I
OH
= - 4.0 mA at V
OH
= 3.98 V with V
CC
= 4.5 V and T: -55
o
to 25
o
C
at V
OH
= 3.84 V with V
CC
= 4.5 V and T: < 85
o
C
at V
OH
= 3.70 V with V
CC
= 4.5 V and T: < 125
o
C
= - 5.2 mA at V
OH
= 5.48 V with V
CC
= 6.0 V and T: -55
o
to 25
o
C
at V
OH
= 5.34 V with V
CC
= 6.0 V and T: < 85
o
C
at V
OH
= 5.20 V with V
CC
= 6.0 V and T: < 125
o
C
I
OL
= 4.0 mA at V
OL
= 0.26 V with V
CC
= 4.5 V and T: 25
o
to -55
o
C,
at V
OL
= 0.33 V with V
CC
= 4.5 V and T: < 85
o
C
at V
OL
= 0.40 V with V
CC
= 4.5 V and T: < 125
o
C
= 5.2 mA at V
OL
= 0.26 V with V
CC
= 6.0 V and T: 25
o
to -55
o
C
at V
OL
= 0.33 V with V
CC
= 6.0 V and T: < 85
o
C
Buffers
Quad 2 - input NAND Buffer - 74LS37
Dual 4 - input NAND Buffer - 74LS40
These have an output current capability of
I
OL
= 24 mA
I
OH
= - 1200mA
They can drive as many as 60 LSTTL loads.
Propagation delay: t
PHL
= t
PLH
= 24 n secs against the
usual 15 n secs
To drive a load beyond the capability of a buffer, discrete
components have to be used.
Output Voltages
The worst case V
OH
= 2.7 V in LSTTL family
= 5.5 V in case of HCMOS if 6.0 V is
used as power supply
If larger output voltages are required use open-collector gates
A
B
v c c
Open collector terminal can be connected to the
desired supply voltage(< V
OH(max)
) through a suitable load resistor
Available open collector LSTTL
gates
Quad 2-input NAND(OC) - 74LS03 [V
OH
(max) = 5.5 V, I
OL
= 8 mA]
Quad 2-input NAND(OC) - 74LS26 [V
OH
(max) = 15 V, I
OL
= 18 mA]
Hex Inverter (OC) - 74LS38 [V
OH
(max) = 5.5 V, I
OL
= 24 mA]
Hex Inverter/Buffer (OC) - 7406 [V
OH
(max) = 30 V, I
OL
= 40 mA]
Hex Buffer (OC) - 7407 [V
OH
(max)= 30 V, I
OL
= 40 mA]
The HCMOS and HCTMOS families do not offer many open drain
circuits
Delay associated with OC gate
74LS26 operated at V
CC
of 5 V, R
L
= 2 K and C
L
= 15 pF
has t
PLH
= 32 ns (max) and a t
PHL
= 28 ns (max) against t
PHL
= t
PLH
= 15 ns (max)
A
B
vcc
v
C
Tristate Gates
OC gates have limitations
with regard to the speed
the distance between the modules,
every signal line requires the usage of a suitable load
resistor
Tristate logic elements provide a solution to the
problems of speed and power in bus organized digital
systems.
TSL buffers
LSTTL HCMOS HCTMOS
Quad 3-state noninverting buffer 74LS125A 74HC125A
Quad 3-state noninverting buffer 74LS126A 74HC125A
Octal 3-state inverting buffer/
line driver/line receiver 74LS240 74HC240A 74HCT240A
Octal 3-state Noninverting buffer/
line driver/line receiver 74LS241 74HC241 74HCT241A
Octal 3-state inverting bus
transceiver 74LS242 74HC242
Octal 3-state noninverting buffer/
line driver/line receiver 74LS244 74HC244A 74HCT244A
Octal 3-state noninverting bus
transceiver 74LS245 74HC245A 74HCT245
TSL buffers
Hex 3-state noninverting buffer
with common enables 74LS365A 74HC365
Hex 3-state inverting buffer
with common enables 74LS366A 74HC366
Hex 3-state noninverting buffer
with 2-bit and 4-bit sections 74LS367A 74HC367
Hex 3-state inverting buffer
with 2-bit and 4-bit sections 74LS368A 74HC368
Octal 3-state inverting buffer/
line driver/line receiver 74LS540 74HC540 74HCT540
Octal 3-state noninverting buffer/
line driver/line receiver 74LS541 74HC541 74HCT541
Octal 3-state inverting bus
transceiver 74LS640 74HC640A 74HCT640
TSL Gate: Characteristics
In Hi-z state the maximum leakage current at the output,
which occurs when it is tied to a gate whose output is
low-impedance High state, is +20 A
sources 2.6 mA at a V
OH
of 2.7 V, and
sinks 24 mA at V
OL
of 0.5 V and 12 mA at a
V
OL
of 0.4 V.
This will permit as many as 128 tristate logic (TSL) outputs
to be tied to a common bus and still provide enough
sourcing current to drive three LSTTL loads.
TSL Gate: Characteristics
If one device is ON and 127 are OFF the following is valid:
127 x 20A = 2.54 mA
2.6 mA - 2.54 mA = 60A
= 3 x 20 A (LSTTL)
The TSL output will be able to drive reliably a line over 3
meters long
Provides a far superior High level noise immunity
Delay from Inhibit to Output Disable, 20 ns(max)
Delay from Enable to Low State, 25 ns(max)
I NTRODUCTI ON
Logic funct ions t hat represent combinat ional funct ions can be implement ed as
hardware in any one of t he several logic families t hat are commercially available. The
logic families t hat are widely used for t he medium frequency ( up t o about 25 MHz)
applicat ions are
LSTTL
HCMOS
Higher frequency requirement s are met by
FAST series
Schot t ky series
74LSTTL I Cs are designed t o operat e over t he commercial t emperat ure range,
namely, from 0
o
C t o 70
o
C.
54LS TTL I Cs are funct ionally and pin- t o- pin compat ible wit h 74LS unit s, but operat e
over t he Milit ary t emperat ure range, namely, - 55
o
C t o + 125
o
C.
HCMOS family I Cs are also available in t he same t emperat ure range.
Before t he advent of t he microprocessors and programmable LSI combinat ional
circuit s ( PROMs, PLAs and PALs) digit al designers had t o be cont ent wit h gat es t o
realise complex combinat ional circuit s. I t was, t herefore, necessary t o simplify t he
expressions t o reduce t he number of gat es or t he number of I Cs. When t he number
of variables was smaller, designers used Karnaugh Maps or Variable Ent ered
Karnaugh Maps ( VEM) . When t he variables were large in number it was necessary t o
use comput er based minimisat ion t echniques.
Wit h LSI combinat ional circuit s becoming popular and t he cost per gat e coming down
drast ically, t he need for convent ional t ype of minimisat ion is much less, t he
t ract abilit y of t he design became more import ant . The given logical expressions can
now be implement ed, however complex t hey are, using programmable combinat ional
LSI circuit s, and keep t he chip count low.
Cert ain st andard combinat ional funct ions like adders, mult iplexers, comparat ors and
encoders are available in MSI packages. Therefore, realisat ion of t hese commonly
encount ered combinat ional funct ions need not be done by gat es. I n view of t he
availabilit y of cert ain st andard MSI and LSI circuit s t he SSI gat es are mainly used for
realising simple logic funct ions normally encount ered in int erconnect ing LSI and MSI
circuit s. Design wit h t hese gat es, t herefore, is done predominant ly on an int uit ive
basis, and occasionally using K- Maps or VEMs.
Gat es available in t he 74 series of LS and HCMOS/ HCTMOS families are list ed in t he
following.
LSTTL FAST HCMOS HCTMOS
54/ 74LS 54/ 74F 54/ 74HC 54/ 74HCT
NAND Gat es
Quad 2- input NAND 00 00 00A - - -
Triple 3- input NAND 10 10 10 - - -
Dual 4- input NAND 20 20 20 - - -
8- input NAND 30 - - - 30 - - -
13- input NAND 133 - - - 133 - - -
NOR Gat es
Quad 2- input NOR 02 02 02A - - -
Triple 3- input NOR 27 - - - 27 - - -
AND Gat es
Quad 2- input AND 08 08 08A - - -
Triple 3- input AND 11 11 11 - - -
Dual 4- input AND 21 21 - - - - - -
OR Gat es
Quad 2- input OR 32 32 32A - - -
I nv er t er s
Hex invert er 04 04 04A 04A

GATE LEVEL I MPLEMENTATI ON OF LOGI C EXPRESSI ONS
Logical expressions are available in
Sum- of- Product ( SOP) form
Product - of- Sum ( POS) form
But t he expressions we have may or may not be in canonical form. By canonical
form we mean sum of Mint erms in t he case of SOP form, and product of Maxt erms in
t he case of POS form. I f t hey are not in t he canonical form t hey would have been
arrived at eit her heurist ically or aft er simplificat ion t hrough a K- Map or a Variable
Ent ered Map. Consider t he following expression:
STRT = PTRL. I GNI . NEUTR
/
. KI CK + PTRL. I GNI .SLOP. NEUTR
/
. LOCK
/

I t may be not iced t hat t his expression is not in canonical form. I t can be realized by
AND, OR and I NVERT gat es as shown in t he figure 1.

KI CK
PTRL
IGNI
SLOP
NEUTR
LOCK
STRT

FI G. 1: AND- OR- I NVERT realizat ion of a logical expression
We have several problems in realizing t his circuit using commercially available gat es.
AND gat es wit h five input s are not available in LSTTL and HCMOS families.
We can add an ext ra AND gat e wit h t hree input s t o overcome t he problem of 5- input
AND gat e. Consider t he circuit shown in t he figure 2. We now have an ext ra level of
gat ing. An ext ra level of gat ing would always add t o t he input t o out put delay. We
will address t his problem of delay at a lat er st at e.

FI G. 2: I mplement at ion of t he expression for STRT wit h commercially available gat es
Any logic expression in SOP form can essent ially be considered t o be ANDing of
different groups of variables and ORing t he out put s of t he AND gat es. Therefore, it
was considered convenient t o make available in t he same package and AND and OR
gat es suit ably int erconnect ed as shown in t he figure 3.
KICK
PTRL
IGNI
SLOP
NEUTR
LOCK
STRT
H

KICK
PTRL
IGNI
SLOP
NEUTR
LOCK
STRT
H
L
H
L
H
U1
U1
U1
U1
U1
U2
U2
U3

FI G. 3: AO realizat ion of logical expression for START
I n some cases t he invert ed out put is made available by incorporat ing an I NVERTER
along wit h AND and OR gat es in t he same package. Such gat e packages are known
as AO ( AND- OR) or AOI ( AND- OR- I NVERT) gat es. I n fact several such gat es were
made commercially available. They include
Dual 2- wide 2- input AOI 7451/ LS51/ S51/ HC51
4- wide 2- input AOI 7454/ LS54
4- 2- 3- 2 input AOI 74S64
But t here is problem here. I t is not always possible t o have t he required number of
input s or AND groupings in a given AO or AOI gat e. I t was, t herefore, t hought some
provision could be made t o expand t he number of input s t o t he OR funct ion. AO
gat es wit h expansion facilit y and t he expander gat es include
Expandable Dual 2- input 2- wide AOI 7450
Expandable 2- wide 4- input AOI 74LS55
Triple 3- input Expander 7461
Dual 4- input Expander 7460
Consider AOI implement at ion of t he logical expression for STRT, as in t he figure 3.
We not ice t hat AOI realizat ion does not necessarily reduce t he chip count .
We considered earlier t hat a NAND gat e can be used t o realize eit her an AND
funct ion or an OR funct ion according t o t he assert ion levels of t he input signals.
Therefore, any logical expression in SOP form can be realized by t wo levels of NAND
gat es.
The first level NAND gat es perform t he AND operat ion and produce Assert ed
Low out put s.
The second level NAND gat e performs OR operat ion on Assert ed Low input s t o
generat e an Assert ed High out put .
The realizat ion of t he expression for START, in t he polarized mnemonic not at ion, is

STRT U1
U2
IGNI
NEUTR
H
U1
L
L
KICK
H
H
SLOP
/LOCK
PTRL
/NEUTR
IGNI
PTRL

FI G. 4: NAND realizat ion of a logical expression in SOP form
I f variables are available bot h in Assert ed High and Assert ed Low versions, any
logical expression can be realized in it s SOP form t hrough t wo level NAND gat es. I f
variables are not available in bot h t he versions t hen an addit ional level of gat ing,
wit h NANDS used as I NVERTERS, would become necessary. Such a realizat ion of t he
expression for START is shown in t he figure 5.

STRT U1
U1
IGNI
NEUTR
H
U1
U3
U3
L
L
KICK
H
H
SLOP
LOCK
PTRL

FI G. 5: NAND and I NVERTER realizat ion of a logical expression in SOP form wit h
variables in AH form
The maj or advant age of realizing logical expressions t hrough NAND gat es is t hat t he
invent ory in an organizat ion can be kept t o a single variet y of gat es.
I f t he expression is available in t he POS form t hen it is bet t er t o realize it using NOR
gat es. Consider t he expression for STRT in t he POS form as given below.
STRT = ( PTRL+ I GNI + NEUTR+ KI CK) . ( PTRL+ I GNI + SLOP+ NEUTR+ LOCK)
Realizat ion using t he commercially available NOR gat es is shown in t he figure 6.

U1
STRT
U4
U4
U1
U1
U3
U3
U2
U2
U2
U2
U1
PTRL
IGNI
NEUTR
KICK
SLOP
LOCK

FI G. 3. 6: NOR realizat ion of a logical expression in POS form
We observe t hat t he number of gat ing levels had t o be increased as NOR gat es wit h
larger number of input s are not available. Besides, logical expressions are more
commonly expressed in SOP form t han in POS form. Hence implement at ion of
expressions t hrough NOR gat es is not part icularly popular.
Some logical expressions are more convenient ly expressed in t erms of EX- OR
operat ions rat her t han in t he st andard form. For example t he expression for parit y
checking is given by.
EP = A B C D E
This is more convenient ly realized in t his form rat her t han realizing it in it s canonical
version. The logical expression for t he parit y checking, in it s canonical form is
EP = A B C D E + A B C' D' E + A B C' D E' + A B C D' E' +
A' B' C' D' E + A' B' C' D E' + A' B' C D' E' + A' B' C D E +
A B' C' D' E' + A B' C D E' + A B' C D' E + A B' C' D E +
A' B C' D' E' + A' B C D E' + A' B C D' E.+ A' B C' D E.

I t s implement at ion using 74LS86/ HC86s ( Quad 2- input EX- OR) is shown in t he figure
7. Not ice t hat while t his realizat ion appears simple, t he number of levels of gat ing is
considerably more. This would mean more delay t o generat e t he out put variable.
A
B
C
D
E
EP

FI G. 7: Realizat ion wit h EX- OR gat es
At t his st age of design, t he choice of gat es in realizing logical expressions should be
based on t he following fact ors:
Number of chips needed t o realize t he expression
Number of variet ies of chips t o be kept in t he invent ory
Number of levels of gat ing ( t he maximum number of gat es t hat an input
signal has t o pass t hrough in a circuit )
Each expression may lead t o t he usage of a unique combinat ion of gat es in
minimizing t he chip count . I n such a case one has t o keep all t he available gat es in
t he invent ory. However, if one wishes t o minimize t he invent ory it is more
convenient t o limit t he realizat ion of logical expressions t o NANDs and I NVERTERs.
This is part icularly advant ageous as t he expressions are more commonly available in
t he SOP form. The number of levels of gat ing depends on t he number of variables,
t he form in which t he variables are available and t he fan- in of t he available gat es,
which in t urn det ermines t he delay in generat ing t he out put .

DELAY
Any hardware logic unit will have some propagat ion delay associat ed wit h it . The
out put appears wit h a t ime delay aft er t he applicat ion of input s. The t ime
relat ionship bet ween t he input and out put of an I NVERTER is shown in t he figure 1.
Two different t ime delays are ident ified in t he figure,
t
PHL
represent s t he propagat ion delay when t he out put makes a t ransit ion
from high volt age t o low volt age,
t
PLH
indicat es t he propagat ion delay associat ed when t he out put makes a
t ransit ion from low volt age t o high volt age.
These t wo propagat ion delays are not necessarily t he same. When t hey are not t he
same t hey should be considered independent ly, and no averaging should be done.
The I C manufact urers ment ion t ypical and maximum values in t heir specificat ion
sheet s. For example t he propagat ion delays of 74LS04 are:
TYP MAX
t
PHL
- 9. 5 15 ns
t
PLH
- 9. 5 15 ns

A /A
VT
/A
A
PLH
t
t
PHL
VT

FI G. 1: I nput - out put t iming relat ionship in an I NVERTER
The t ypical values of t hese propagat ion delays are used by t he manufact urers t o
indicat e t he speed of t he circuit s. Possibly most of t he I Cs in a given lot will act ually
have delays equal t o or even less t han t hese t ypical values. But t he t ypical value is
not a guarant eed value and hence cannot be used as a design paramet er. You have
t o always work wit h t he worst case values for t hese propagat ion delays, which
happen t o be t he maximum values in t his case.
I t should also be not ed t hat t he manufact urers of LSTTL family I Cs do not guarant ee
any minimum delay. This can creat e problems in cert ain t ypes of circuit s. Consider
t he digit al different iat or shown in t he figure 2.

/X
A B
A
B
X

FI G. 2: Digit al different iat or
The t iming diagram shows t hat t he out put is a pulse of widt h T. What will be t he
widt h of t he out put pulse?
I f we t ake t ypical values for t he associat ed gat es it would be 9. 5 x 3 = 28. 5
ns.
I f we consider maximum values t he widt h would be 15 x 3 = 45 ns.
While we may agree it would be some nonzero value we cannot guarant ee
any minimum value t o t his pulse. I t can be any value from almost 0 t o 45 ns.
I f we want t o generat e a pulse wit h a guarant eed widt h of 30 ns, t his circuit cannot
be used. Therefore, you will have t o be careful in applicat ions similar t o t his in
assuring t he performance of t he circuit .
Propagat ion delay is an import ant paramet er in a digit al circuit , as it is indicat ive of
t he speed wit h which t he given t ask would be done. One of t he aims of digit al
syst ems is t o do more and more in less and less t ime. Therefore, in applicat ions
where speed is an import ant crit erion, you will have t o keep a close wat ch on t he
propagat ion delays and make at t empt s t o reduce t hem as much as possible.
When a logical expression is given in a SOP eit her in canonical or non- canonical form
and t he variables are available in t heir Assert ed High and Assert ed Low versions, it
can be realised by t wo level NAND gat ing, if t he number of input s do not exceed 13
( 74S134) .
I f t he variables are available only in one form t hen t he expression in it s canonical
form can be realized t hrough t hree levels of gat es.
I f t he expression is t o be realised in any ot her form t he delay is likely t o be more.
Consider t he expression for STRT as given below:
STRT = PTRL. I GNI . ( [ NEUTR. KI CK] + [ SLOPE. NEUTR
/
.KI CK
/
] )
Obviously, t his expression is not in it s canonical form. I t s realisat ion is shown in t he
figure 3. The propagat ion delay of t his realisat ion is equal t o t hat of five st ages.

NEUTR
SLOPE
NEUTR
PETR
IGNI
STRT
KICK
KICK

FI G. 3: Realisat ion of t he logic expression for START in it s non- canonical form
You should not e t hat t he minimizat ion of propagat ion delay may not always t he
design obj ect ive. I n such cases you may use ot her forms of t he logical expression if
t hey do not increase t he chip count . The form of t he expression may be chosen t o
make t he design more easily underst andable.
Let us consider some hardware aspect s of propagat ion delay. The value given for t
PHL

and t
PLH
are not t he guarant eed maximums under all operat ing condit ions. Normally
t he delays for LSTTL family are defined at t he following operat ing condit ions:
T = 25
o
C, V = 5 volt s, C = 15 pF, and R = 2 K
For HCMOS family t he delay t imes are defined at many operat ing condit ions, as
t hese devices can be operat ed at volt age levels below 6 volt s. The dc and ac
charact erist ics including t he t ime delays are specified at nine operat ing point s ( t hree
volt ages and t hree t emperat ures)

1. V
CC
= 2. 0 V, T: 25
o
C t o - 55
o
C, < 85
o
C, and < 125
o
C, C
L
= 50 pF, I nput t
r
=
t
f
= 6 ns
2. V
CC
= 4. 5 V, T: 25
o
C t o - 55
o
C, < 85
o
C, and < 125
o
C, C
L
= 50 pF, I nput t
r
=
t
f
= 6 ns
3. V
CC
= 6. 0 V, T: 25
o
C t o - 55
o
C, < 85
o
C, and < 125
o
C, C
L
= 50 pF, I nput t
r
=
t
f
= 6 ns

As HCTMOS family is compat ible wit h LSTTL family t he AC elect rical charact erist ics
are defined only at one volt age, namely, at V
CC
= 5 V in t he following manner.
V
CC
= 5. 0 V, T: 25
o
C t o - 55
o
C, < 85
o
C, and < 125
o
C, C
L
= 50 pF,
I nput t
r
= t
f
= 6 ns.
The t est circuit wit h which t hese delays are measured is given in t he figure 4. The
propagat ion delays change wit h t emperat ure, load capacit ance and t ype of load
circuit . The circuit shown in t he figure 4 simulat es t he input of a LSTTL and HCMOS
gat es.
V
cc
V
cc
V
out
D
DUT

FI G. 4: Test circuit s for LSTTL I Cs wit h t ot em- pole out put s and for HCMOS I Cs
Ot her t ypes of load circuit s, we are likely t o encount er, are shown in t he figure 5.

R
V V
R
R C
T E
L L
C
T
CC CC

FI G. 5: Load circuit s encount ered in digit al syst ems
The load capacit ance will, in t urn, depend on t he PCB t rack widt h and t he lengt h, and
on t he mat erial of t he laminat e. The capacit ance encount ered in act ual pract ice can
vary from 20 pF t o 150 pF. The effect of t his capacit ance is t o increase t he
propagat ion delay and supply current spike amplit ude during t he t ransient s.
Depending on t he load circuit , capacit ive loading and t emperat ure t he propagat ion
delays can increase by as much as 15 ns. The nat ure of dependence of t he
propagat ion delay on t he load capacit ance is shown in t he figure 6.

.
2 0 6 0 100 140 180
p F
1 0
2 0
3 0
C Load Capaci tance
T
t
t
PHL
PLH
( 25
o
(25 C)
o
D
e
l
t
a

T
u
r
n

o
n

d
e
l
a
y

(
n
s
e
c
)

C)

FI G. 6: Dependence of t urn- on delay on t he load capacit ance
The designer is required t o pay special at t ent ion t o t he PCB layout t o minimize t he
capacit ive loading, t he designer is advised t o consult t he performance curves
published by t he manufact urer when t he circuit s are t o be designed at high/ low
t emperat ures and/ or under high capacit ive load condit ions.

HAZARDS
The analysis and minimisat ion met hods present ed so far predict t he behaviour of
combinat ional circuit s under st eady st at e. This means t hat t he out put of t he circuit is
considered only aft er all t he t ransient s t hat are likely t o be produced when t he st at e
of t he input s signals change. However, t he finit e delays associat ed wit h gat es makes
t he t ransient response of a logic circuit different from st eady st at e behaviour. These
t ransient s occur because different pat hs t hat exist from input t o out put may have
different propagat ion delays. Because of t hese differences in t he propagat ion delays
combinat ional circuit s, as we will demonst rat e, can produce short pulses, known as
glit ches, under cert ain condit ions, t hough t he st eady st at e analysis does not predict
t his behaviour. A hazard is said t o exist when a circuit has t he possibilit y of
generat ing a glit ch. However, t he act ual occurrence of t he glit ch and it s pulse widt h
depend on t he exact delays associat ed wit h t he act ual devices used in t he circuit .
Since t he designer has no cont rol over t his paramet er it is necessary for him t o
design t he circuit in a manner t hat avoids t he occurrence of glit ches. While a given
circuit can be analysed for t he presence of glit ches, it is necessary t o design t he
syst em in a manner t hat hazard analysis of t he circuit would not be necessary. One
simple met hod is not t o look at t he out put s unt il t hey set t le down t o t heir final value.
Consider t he realizat ion of logical expression X = A B' + BC' D' as shown in t he figure
3. 14. I n t his circuit t he hazard is caused by t he propagat ion delay associat ed wit h
t he gat e- 1. Let A and B be Assert ed and C and D are Not - asserrt ed. When B changes
from it s Assert ed st at e t o it s Not - assert ed st at e wit h t he ot her variables remaining
t he same t he out put should remain in it s Assert ed st at e. However, when B changes
from 1- t o- 0 t he out put of t he gat e- 5 changes from 1- t o- 0. The out put of t he gat e- 4
should change from 0- t o- 1 at t he same t ime. But t he delay associat ed wit h t he
gat e- 1 makes t his t ransit ion of t he gat e- 4 out put t o happen a lit t le lat er t han t hat of
gat e- 5. This can cause brief t ransit ion of X from 1- t o- 0 and t hen from 0- t o- 1, as
A
B
B
C
D
X
1
2
3
4
5
6

FI G. 1: Relaisat ion of t he expression X = AB
/
+ BC
/
D
/

A hazard of t his nat ure is known as st at ic- 1 hazard, because t he circuit is likely
produce a 0- glit ch when t he out put is expect ed t o remain in st at e 1 as per t he
st eady st at e analysis. Similarly, if t he circuit is likely t o produce a 1- glit ch when t he
out put is expect ed t o remain in st at e 0 as per t he st eady st at e analysis it is known
as st at ic- 0 hazard. When t he out put is supposed t o change from 0 t o 1 ( or 1 t o 0) ,
t he circuit may go t hrough t hree or more t ransient s t o produce more t han one glit ch.
Such mult iple glit ch sit uat ions are known as dynamic hazards. The st at ic and
dynamic hazards are illust rat ed in t he figure 2. Obviously t hese hazards are
undesirable when t hese out put s happen t o be crit ical in a given digit al syst em.

FI G. 2: Different t ypes of st at ic and dynamic hazards
The K- Map of t he expression given above is shown in t he figure 3.

1 1 1
1
1
1
A
B
C
D
1 1 1
1
1
1
A
B
C
D
AC'
BC'D'
AB'

FI G. 3: K- maps of t he logic expression X = AB' + BC' D'
I t is clear from t he K- Map t hat t he hazard associat ed wit h t he 1- t o- 1 t ransit ion
occurred when t he change of st at e of t he variable B caused t he t ransit ion from one
grouping BC' D' t o anot her grouping AB' . This j ump made it necessary for t he signal B
t o go t hrough anot her pat h of longer delay t o keep t he out put at t he same st at e.
While t he K- Map makes it easy t o ident ify t he hazard associat ed wit h 1- t o- 1
t ransit ion it is much more difficult t o det ect t he ot her t hree t ransit ions. Fort unat ely
one result from Logic and Swit ching Theory comes t o our rescue. The t heorem for
t he hazard free design st at es t hat a t wo level gat e implement at ion of a logical
expression will be hazard free for all t ransit ions of t he out put if it is free from t he
hazard associat ed wit h 1- t o- 1 t ransit ion. This t heorem makes it very easy t o det ect
and correct for t he hazards in a combinat ional circuit , since t he 1- t o- 1 t ransit ion can
easily be det ect ed t hrough K- Map. When t he input variables change in such manner
as t o cause a t ransit ion from one grouping t o anot her grouping, t he 1- t o- 1 t ransit ion
can occur. Therefore, t he procedure t o eliminat e hazards in t wo level gat ing
realizat ion of a logical expression is t o include all 1s which are unit dist ance apart at
least in one grouping. I n t he example considered above t he hazard occurred
because when B changed it s st at e, it caused a t ransit ion from BC' D' grouping t o A B'
grouping. Therefore t he solut ion t o remove hazard is t o group t he t erms ABC' D' and
AB' C' D' t oget her. This would lead t o an addit ional gat e. This procedure is illust rat ed
in t he figure 4. The added gat e defines t he out put during t he t ransit ion of B from
one st at e t o t he ot her. This procedure can be applied t o all t wo level gat e sit uat ions
t o eliminat e hazards.
A
B
C
D
X

FI G. 4: Hazard free realisat ion of t he expression
X = AB' + BC' D' as X = AB' + BC' D' + AC' D'

LOADI NG
A logic gat e has limit ed capacit y t o source and sink current at it s out put . As t he
out put of a gat e is likely t o be connect ed t o more t han one similar gat e, t he designer
has t o ensure t hat t he driving unit has t he necessary current capabilit y. The loading
in t he case of digit al circuit s, built wit h TTL int egrat ed circuit s, is defined in t erms of
Unit Loads ( UL) . One UL is defined as t hat of t he input of St d. TTL gat e. This is given
by,
I
I L
: I nput LOW Current ( The current flowing out of an input when a
specified LOW level volt age is applied t o t hat input )
= - 1. 6 mA ( wit h V
CC
at Maximum and V
I
= 0. 4 volt s)
I
I H
: I nput HI GH Current ( The current flowing int o an input when a specified
HI GH level volt age is applied t o t hat input )
= 40A ( wit h V
CC
at Maximum and V
I
= 2. 4 volt s)
A St d. TTL gat e has a fanout of 10 ULs. This is equivalent t o,
I
OL
: Out put LOW Current ( The current flowing int o an out put which is in t he
LOW st at e)
= 16 mA ( wit h V
CC
and V
I H
at Minimum and V
OL
= 0. 4 volt s)
I
OH
- Out put HI GH Current ( The current flowing out of an out put which is in
HI GH st at e)
= - 400 A( wit h V
CC
at Minimum, V
I L
at Maximum and V
OH
= 2. 4 volt s)
The out put current capabilit y of LSTTL gat e is
I
OH
= - 400 A at V
OH
= 2. 7 volt s
I
OL
= 4 mA at V
OL
= 0. 4 volt s
= 8 mA at V
OL
= 0. 5 volt s
I f t he LOW st at e out put V
OL
is t o be maint ained at 0. 4 volt s LSTTL gat es have 2.5 UL
capabilit y, and if V
OL
can be t olerat ed at 0. 5 volt s it can support 5 ULs. However, it is
unlikely t hat we need t o drive St d. TTL gat es. The LSTTL gat e has t he input
charact erist ics as given below:
I
I H
= 20 A at V
I
= 2. 7 volt s
I
I L
= - 0. 4 mA at V
I
= 2.7 volt s
Therefore, an LSTTL gat e can drive 10 LSTTL gat es wit h V
OL
of 0. 4 volt s and 20
LSTTL gat es wit h a V
OL
of 0. 5 volt s. The loading on an LSTTL gat e, t hat is, t he
number of ot her LSTTL gat es t hat can be connect ed t o it , should be kept wit hin t hese
limit s. I f t hese limit s are exceeded, init ially t he logic volt age levels det eriorat e from
t he specified values, and subsequent ly t he gat e would be damaged due t o t he
excessive power consumpt ion.
The input and out put current specificat ions of a HCMOS gat e are given by;
I
in
= + 0. 1 A at V
CC
= 6. 0 V at T: 25
o
C t o - 55
o
C,
= + 1. 0 A at V
CC
= 6. 0 V at T: < 85
o
C
= + 1. 0 A at V
CC
= 6. 0 V at T: < 125
o
C
I
OH
= - 4. 0 mA at V
OH
= 3. 98 V wit h V
CC
= 4. 5 V and T: - 55
o
t o 25
o
C
at V
OH
= 3. 84 V wit h V
CC
= 4. 5 V and T: < 85
o
C
at V
OH
= 3. 70 V wit h V
CC
= 4. 5 V and T: < 125
o
C
= - 5. 2 mA at V
OH
= 5. 48 V wit h V
CC
= 6. 0 V and T: - 55
o
t o 25
o
C
at V
OH
= 5. 34 V wit h V
CC
= 6. 0 V and T: < 85
o
C
at V
OH
= 5. 20 V wit h V
CC
= 6. 0 V and T: < 125
o
C
I
OL
= 4. 0 mA at V
OL
= 0. 26 V wit h V
CC
= 4. 5 V and T: 25
o
t o - 55
o
C,
at V
OL
= 0. 33 V wit h V
CC
= 4. 5 V and T: < 85
o
C
at V
OL
= 0. 40 V wit h V
CC
= 4. 5 V and T: < 125
o
C
= 5. 2 mA at V
OL
= 0. 26 V wit h V
CC
= 6. 0 V and T: 25
o
t o - 55
o
C
at V
OL
= 0. 33 V wit h V
CC
= 6. 0 V and T: < 85
o
C
at V
OL
= 0. 40 V wit h V
CC
= 6. 0 V and T: < 125
o
C
As it can be seen t he designer has t o consider a wide range of operat ing condit ions
t o t ake loading effect s int o considerat ion when working wit h HCMOS family circuit s.
For t he HCTMOS family I Cs t he current s specified at V
CC
= 4. 5 V need only t o be
considered.
There may arise cert ain occasions, like a clock source driving many unit s and set t ing
up LOW( L) and HI GH ( H) volt age levels t o be connect ed t o unused input s, wherein it
may become necessary t o provide more drive capabilit y t han t he st andard values. I n
such cases buffers have t o be used. The available buffers in LSTTL family are;
Quad 2 - input NAND Buffer - 74LS37
Dual 4 - input NAND Buffer - 74LS40
These have an out put current capabilit y of
I
OL
= 24 mA
I
OH
= - 1200A
They have t he capacit y t o drive as many as 60 LSTTL loads. There is a small price t o
be paid in t erms of increased propagat ion delay ( t
PHL
= t
PLH
= 24 n secs against t he
usual 15 n secs) for t his enhanced drive capabilit y. This increased t ime delay should
not normally make any difference as t hese buffers are unlikely t o be used for
implement ing logic expressions. There are no similar buffers available in t he HCMOS
and HCTMOS families. When we are required t o drive a load even beyond t he
capabilit y of a buffer, discret e component s have t o be used.

LARGER OUTPUT VOLTAGE SWI NG
The worst case out put volt age level of a gat e when it is in HI GH st at e can be as low
as 2. 7 volt s in t he case of LSTTL family and only 2. 4 volt s in t he case of St d. TTL
family. I n t he case of HCMOS family t he out put volt age levels can go up t o 5. 5V if
6. 0V power supply is used. I f it is desired t o have a higher out put volt age swing one
simple way is t o connect a 1 K or a 2 K resist or from V
CC
t o t he out put t erminal.
However, it should be remembered t hat t his modificat ion of t he out put circuit would
increase t he propagat ion delay. Larger out put volt age swings can be obt ained wit h
t he help of open- collect or gat es. I n t he open- collect or ( OC) gat es t he act ive pull- up
circuit of t he out put t ot em- pole configurat ion in t he LSTTL circuit is delet ed as shown
in t he figure 1.

A
B
vcc

FI G. 1: 2- input LSTTL NAND gat e wit h open collect or out put
The designer can now have t he choice of ret urning t he open collect or t erminal t o t he
desired supply volt age, as long as it s value is less t han or equal t o t he V
OH( max)

specified, t hrough a suit able load resist or.
The available open collect or LSTTL gat es are:
Quad 2- input NAND( OC) gat e - 74LS03 [ V
OH

( max)
= 5. 5 V, I
OL
= 8 mA]
Quad 2- input NAND( OC) gat e - 74LS26 [ V
OH

( max)
= 15 V, I
OL
= 18 mA]
Hex I nvert er ( OC) - 74LS38 [ V
OH

( max)
= 5. 5 V, I
OL
= 24 mA]
Hex I nvert er/ Buffer ( OC) - 7406 [ V
OH

( max)
= 30 V, I
OL
= 40 mA]
Hex Buffer ( OC) - 7407 [ V
OH

( max)
= 30 V, I
OL
= 40 mA]
The manner in which t he load resist or is t o be connect ed is shown in t he figure 2. As
t he pull- up is t hrough a passive resist or t he propagat ion delay will be higher t han
t hat of t he gat e wit h t he t ot em- pole out put . For example 74LS26 operat ed at V
CC
of
5 V, R
L
= 2 K and C
L
= 15 pF has t
PLH
= 32 ns ( max) and a t
PHL
= 28 ns ( max)
against t
PHL
= t
PLH
= 15 ns ( max) in t he case of 74LS00 under t he same operat ing
condit ions. Open collect or gat es are useful for int erfacing I Cs from different logic
families, and I Cs wit h discret e circuit s operat ing wit h different supply volt ages.

A
B
vcc
v
C

FI G. 2: Connect ing a load resist or t o an OC gat e
The HCMOS and HCTMOS families do not offer many open drain circuit s. Whenever
larger volt age swings are needed it is possible t o use CD4000 series circuit s. The
only open drain gat e t hat is available in t he HCMOS family is 74HC03, which is quad
2- input NAND gat e. The maj or applicat ion of open- collect or gat es is in implement ing
wired- logic operat ion needed in bussing signal lines.

WI RED- LOGI C OPERATI ONS
I f t he out put s of t he gat es can be t ied t oget her as shown in t he figure 1 it would be
possible t o realise AND operat ion wit hout t he act ual use of hardware.

A
B
C
D
AB
CD
X=ABCD

FI G. 1: Wired AND operat ion
Such connect ions are referred t o as wired- AND and implied- AND. This is because t he
volt age at t he int erconnect ing point is High only if t he out put s of bot h t he gat es are
High at t he same t ime. Such wired- logic connect ions are very useful in bussing
signals in large digit al syst ems wherein t he hardware has t o be implement ed on a
number of print ed circuit boards. Consider t he sit uat ion shown in t he figure 2.

BOARD A BOARD B BOARD C BOARD N

FI G. 2: Common signal line in Bus organised digit al syst em
Board A has t o t ake some act ion aft er verifying t he change of st at e in all t he ot her
boards. Though t his operat ion can be performed t hrough using combinat ional
circuit s, it is more convenient ly performed t hrough wired- AND int erconnect ion of t he
out put s from all t he boards and connect ing t his wired- AND signal t o be input line of
board- A. This would subst ant ially reduce t he amount of hardware t o be used.
Let us explore t he possibilit y of implement ing such wired- logic connect ions wit h
LSTTL combinat ional I Cs. The act ual circuit t hat would result when we connect t he
out put s of t wo LSTTL gat es wit h t ot em- pole out put configurat ions is shown in t he
figure 3. I t can be seen from t he circuit diagram t hat if one of t he out put s is in Low
st at e while t he ot her one is in High st at e t here will occur a low impedance pat h
bet ween t he supply and ground leading t o a large value of current . This can lead t o
t he dest ruct ion of t he component s in t he out put circuit s of t he I Cs. Therefore, it is
not possible t o short t he out put s of t wo or more LSTTL gat es t o realize wired- logic
operat ions. However, wired logic operat ions can be implement ed wit h t he help of
open- collect or gat es.

H L
Vcc
Vcc

FI G. 3: Out put s of t wo LSTTL gat es t ied t oget her
When t he out put s of t he open collect or gat es are t ied t oget her it becomes necessary
t o connect a load resist ance R from t he out put point t o t he supply. The value of t his
load resist ance should be carefully chosen t o maint ain t he logic st at e wit hin t he TTL
limit s under worst operat ing condit ions. The most general int erconnect ion sit uat ion
t hat can occur is shown in t he figure 4.

OC
OC
OC
OC
H
H
H
H
RL
I
IH
I
IH
I
IH
I
OH
I
OH
I
OH
I
OH
V
CC

FI G. 4: Connect ion of OC gat es in parallel wit h all t he out put s in t he High st at e
I t may be not ed t hat when t wo OC gat es are int erconnect ed t o perform wired- AND
operat ion t hey are capable of driving one t o nine Unit Loads, and when an OC gat e is
not paralleled wit h ot her gat es t hen it can drive up t o t en Unit Loads. The maximum
value of t he load resist ance R must be select ed t o ensure t hat sufficient load current
( t o drive t he out put gat es) out put is High. Using t he worst case values for t he High
and Low st at es for designing t he load resist or R
L
, will give a guarant eed dc noise
margin of 700 mV in t he logic High st at e. Since 2. 7 V should be present no more
t han 2. 3V can be dropped acrossR
L
. The current t hrough R is composit e of current
int o t he loads, m . I
I H
, and leakage current int o out put t ransist ors which are biased
int o off st at e, n. I
OH
. Bot h I
OH
and I
I H
are dat a sheet specificat ions; t hey are 250 A
and 20 A respect ively in t he case of 74LS38. The maximum value of t he load
resist or is calculat ed from t he relat ionship given below:
R
L( max)
=
V
CC
V
OH(required)
n.I
OH
+m.I
IH
wit h n = 4, m = 3 and V
CC
= 5 V and V
OH
( required) = 2. 7 V t he maximum value of
R
L
is 2170 ohms. A great er value will result in t he det eriorat ion of t he High st at e
volt age value. The minimum value of R
L
is found by considering Low st at e at t he
out put of t he paralleled gat es as shown in t he figure 5. R
L
is permit t ed t o drop a
maximum volt age dict at ed by t he noise margin in t he Low st at e, which is 400 mV. I n
t he circuit shown in t he figure 5, wherein t he worst case sit uat ion is indicat ed, t he
out put of one gat e is in Low st at e while t he out put s of t he remaining gat es are in
High st at e. The resist or must be able t o maint ain t he Low level while sinking t he
load current from all t he gat es connect ed as load.
The minimum value of t he load resist or R
L
may now be calculat ed from t he
relat ionship given as below:

R
L( min)
=
V
CC
V
OL(required)
I
OL(capability)
I
sink(load)

OC
OC
OC
OC
H
L
H
H
RL
V
CC

FI G. 5: OC gat es connect ed for wired- AND operat ion wit h t heir
out put s in Low st at e
Wit h I
OL
= 24 mA and I
I L
= 0. 4 mA t he minimum value of R
L
is 201 ohms. The value
of t he load resist or may be chosen bet ween R
L
( max) and R
L
( min) . I t is essent ial t o
not e t hat t he out put impedance of t he OC gat es will be significant ly higher in t he
High st at e due t o t he pull- up resist or in comparison t o t hat of t he gat e wit h t he
t ot em- pole out put . This also result s in a slight ly higher propagat ion delay.
1

TRISTATE GATES
Wired- logic operat ions are import ant in t he design of bus- st ruct ured digit al syst ems. The
open- collect or gat es can meet t he requirement s of bussing, but have limit at ions wit h regard t o
t he speed and t he dist ance bet ween t he modules, and every signal line requires t he usage of a
suit able load resist or. These fact ors limit t he operat ion of OC based bus st ruct ured syst ems t o
about 2 MHz operat ion over a dist ance of a few met ers. Trist at e logic element s provide a
solut ion t o t he problems of speed and power in bus organized digit al syst ems. Trist at e gat es
are essent ially gat es wit h out put st ages t hat assume t hree st at es. Two of t hese t hree ar e
normal low impedance High and Low st at es. The t hird one is a high- impedance ( Hi- z) st at e.
When t he device is in Hi- z st at e bot h t he t ransist ors in t he out put t ot em- pole cir cuit are in off
condit ions. When t he out put of such a gat e in Hi- z st at e is t ied t o t he out put of a gat e t hat is
in Lo- z st at e, t he High- z st at e gat e does not influence ( in any significant manner) t he out put
circuit of a Lo- z st at e gat e. This enables us t o t ie t he out put s of many t rist at e devices, and
share a common ( bus) signal line. These unit s have t he speed of t he regular devices, higher
line- dr ive capabilit y and higher noise immunit y. By eliminat ing t he pull- up resist ors t hese
t rist at e gat es cut bus delays t o a few nanoseconds. The available TSL buffers are list ed in t he
following:
LSTTL HCMOS HCTMOS
Quad 3- st at e noninvert ing buffer 74LS125A 74HC125A
Quad 3- st at e noninvert ing buffer 74LS126A 74HC125A
Oct al 3- st at e invert ing buffer/ line driver/ line
receiver
74LS240 74HC240A 74HCT240A
Oct al 3- st at e Noninvert ing buffer/ line driver/ line
receiver
74LS241 74HC241 74HCT241A
Oct al 3- st at e invert ing bus t ransceiver 74LS242 74HC242
Oct al 3- st at e noninvert ing buffer/ line driver/ line
receiver
74LS244 74HC244A 74HCT244A
Oct al 3- st at e noninvert ing bus t ransceiver 74LS245 74HC245A 74HCT245
Hex 3- st at e noninvert ing buffer wit h common
enables
74LS365A 74HC365
Hex 3- st at e invert ing buffer wit h common enables 74LS366A 74HC366
Hex 3- st at e noninvert ing buffer wit h 2- bit and 4- bit
sect ions
74LS367A 74HC367
Hex 3- st at e invert ing buffer wit h 2- bit and 4- bit
sect ions
74LS368A 74HC368
Oct al 3- st at e invert ing buffer/ line driver/ line
receiver
74LS540 74HC540 74HCT540
Oct al 3- st at e noninvert ing buffer/ line driver/ line
receiver
74LS541 74HC541 74HCT541
Oct al 3- st at e invert ing bus t ransceiver 74LS640 74HC640A 74HCT640

2
When t he out put of an LSTTL t rist at e gat e is in Hi- z st at e t he maximum leakage current at t he
out put , which occurs when it is t ied t o a gat e whose out put is low- impedance High st at e, is
+ 20 A ( int o t he out put t erminal) . When t he device is placed in it s low impedance st at e it has
all t he desirable proper t ies of t he usual LSTTL gat e. Anot her import ant fact or in driving a bus
line is t he current capabilit y in sinking and sourcing. For t his reason t he out put st age of a
t rist at e gat e is designed t o source 2. 6 mA at a V
OH
of 2. 7 V, and sink 24 mA at V
OL
of 0. 5 V
and 12 mA at a V
OL
of 0. 4 V. This is 6. 5 t imes more sourcing capabilit y t han a LSTTL gat e.
This will permit as many as 128 t rist at e logic ( TSL) out put s t o be t ied t o a common bus and
st ill provide enough sourcing current t o drive t hree LSTTL loads. I f one device is ON and 127
are OFF t he following is valid:
127 x 20A = 2. 54 mA
2. 6 mA - 2. 54 mA = 60A
= 3 x 20 A ( LSTTL)
The device t hat is ON, t herefore, is capable of maint aining LSTTL speeds while driving t he bus.
Anot her advant age of t he high current sourcing feat ure is t hat t he LSTTL gat e wit h 400 A
maximum sourcing capabilit y can only drive about 25 t o 35 cms of line before t he noise
problems become prohibit ive. The TSL out put will be able t o drive reliably a line over 3 met ers
long. The great er sourcing capabilit y also pr ovides a far superior High level noise immunit y
t hat is bet t er t han t he usual LSTTL devices. TSL gat es are designed in such a way t hat t he
delay from I nhibit t o Out put Disable, 20 ns( max) , is less t han t he delay from Enable t o Low
St at e, 25 ns( max) . Therefore, t he device t hat is disabled off t he line is removed before t he
device t hat is being enabled int o Low st at e is brought on t o t he bus. This prevent s t he
occurrence of heavy current s during t he t ransient s from Hi- Z st at e t o Low- Z st at e and vice-
versa. I n addit ion t he out put st at e is designed t o t ake care of short ed condit ions bet ween t wo
TSL gat es. Even if t wo devices are simult aneously swit ched on, t he pull down t ransist ors are
designed t o wit hst and as much as 40 mA. But long before it reaches t hat limit t he t ransist ors
begin t o come out of sat urat ion.
At present many of t he combinat ional and sequent ial MSI circuit s are available commercially
wit h t rist at e out put s. This opt ion makes t he usage of t hese I Cs very convenient .

Digital Electronics
Multiplexers
N.J. Rao
Multiplexers
A multiplexer is a combinational circuit that gates one out
of its several inputs to a single output.
It is also called a data selector.
The input selected for connection to the output is
controlled by a set of SELECT inputs.
4-Input Multiplexer
MUX
0
1
0
1
2
3
S0
S1
DI0
DI1
DI2
DI3
G
0
_
3
Y
SELECT
INPUTS
DATA
INPUTS
Functioning of the Multiplexer
S0 and S1 are select inputs.
Together S0 and S1 determine the input, among the
Data Inputs, DI0, DI1, DI2, and DI3, that gets connected
to the output Y.
The output of the multiplexer is given by:
Y = DI0.S1/.S0/ + DI1.S1/.S0 + DI2. S1.S0/ +
DI3.S1.S0
The relationship between the SELECT inputs and the
DATA inputs is G dependency.
Parameters of concern
The main parameters of concern to us are:
Number of inputs
Nature of outputs
Propagation delay
Available LSTTL multiplexers
54/74LS 54/74F 54/74HC 54/74HCT
Quad 2-input multiplexers
2-state noninverting outputs 157 157A 157 157A
2-state inverting outputs 158 158A
3-state noninverting outputs 257B 257A 257
3-state noninverting outputs 258B 258A
Available LSTTL multiplexers
54/74LS 54/74F 54/74HC 54/74HCT
Dual 4-input Multiplexer
2-state noninverting outputs 153 153 153
2-state inverting outputs 352 352
3-state inverting outputs 353 353
8-input Multiplexer
16-input Multiplexer
2-state noninverting outputs 150
Multiplexer ICs can be used for
selection of data from multiple sources
realising logic expressions
Data Selection
Selecting 8-bit data
from four sources
Data Selector
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
ch9
ch10
ch11
ch12
ch13
ch14
ch15
ch16
ch25
ch26
ch27
ch28
ch29
ch30
ch31
ch32
s3
s4
ch17
ch18
ch19
ch20
ch21
ch22
ch23
ch24
ch1
ch2
ch3
ch4
ch5
ch6
ch7
ch8
s3
s4
s0
s1
s2
s3
s4
1-of-32 data selector
Multiplexers for Logic Realization
Consider the function Y
Y = A
/
B
/
C
/
+ A
/
BC + AB
/
C + ABC
/
Y = m0 (IP0) + m1 (IP1) + - - - - m2n (IP2n)
Y = m0 + m3 + m5 + m6
Y = m0(IP0=1) + m1(IP1=0) + m2(IP2=0) +
m3(IP3=1) + m4(IP4=0) + m5(IP5=1) +
m6(IP6=1) + m7(IP7=0).
Realization of Y
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
C
B
A
L
H
Y
Example
Y = (1, 2, 4, 7, 8, 9, 13)
X4 0 1 1 1 1 0 1 1
X4 0 0 1 1 1 0 0 1
X4
/
1 1 0 1 0 0 0 1
X4 1 1 0 1 1 1 1 0
X4
/
0 1 0 1 0 0 1 0
X4
/
1 0 0 1 0 1 0 0
X4 0 0 0 1 1 0 0 0
Y X3 X2 X1 Y X4 X3 X2 X1
Y = X4 (0, 3, 4, 6) + X4
/
(1, 2, 4)
= X4 (0, 3, 6) + X4
/
(1, 2) + (1) 4
Example
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y
X4
X3
X2
X1
L
H
Some variables are Asserted Low
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y
X3
X2'
X1'
X4
H
L
X1 and X2 are asserted low
MULTI PLEXERS
A mult iplexer is a combinat ional circuit t hat gat es one out of it s several input s t o a
single out put . As it select s one out of many input s, it is also called a dat a select or .
The input select ed for connect ion t o t he out put is cont rolled by a set of SELECT
input s. A t ypical 4- input mult iplexer is illust rat ed in t he figure 1.
MUX
0
1
0
1
2
3
S0
S1
DI0
DI1
DI2
DI3
G
0
_
3
Y
SELECT
INPUTS
DATA
INPUTS

FI G. 1: Schemat ic of a 4- input mult iplexer
S0 and S1 are select input s. Toget her S0 and S1 det ermine t he input , among t he
Dat a I nput s, DI 0, DI 1, DI 2, and DI 3, t hat get s connect ed t o t he out put Y.
The out put of t he mult iplexer is given by:
Y = DI 0. S1
/
. S0
/
+ DI 1. S1
/
. S0 + DI 2. S1. S0
/
+ DI 3. S1. S0
Not ice t hat t he relat ionship bet ween t he SELECT input s and t he DATA input s is G
dependency.
The main paramet ers of concern t o us are:
Number of input s
Nat ure of out put s
Propagat ion delay
The choice on t he number of input s enables us t o select t he appropriat e mult iplexer,
t o minimize t he number of I Cs needed t o implement a given logic funct ion.
For example, if dat a is t o be select ed from t wo 16- bit sources, it is more convenient
t o use 2- input mult iplexers, t han 4- input or 8- input mult iplexers.
Some addit ional feat ures:
Higher drive capabilit y of a mult iplexer enables t he designer t o save on
buffers and t he consequent delay in cert ain sit uat ions.
Availabilit y of complement ary out put s oft en result s in t he saving of addit ional
invert ers.
Availabilit y of t rist at e out put s make it easy t o t ie t he out put s of a number of
mult iplexers wit hout using addit ional gat es.
There are t wo propagat ion delays t hat are of int erest t o designers:
- Delay from t he dat a input s t o t he out put
- Delay from t he select input t o t he out put
These t iming relat ionships are shown in figure 2.
t
PLH
t
PLH
t
t
PHL
PHL
t output
select
data

FI G. 2: Timing relat ionship bet ween signals of a mult iplexer
Some of t he commonly available mult iplexers as MSI s in t he LSTTL family are:
54/ 74LS 54/ 74F 54/ 74HC 54/ 74HCT
Quad 2- input mult iplexers
2- st at e noninvert ing out put s 157 157A 157 157A
2- st at e invert ing out put s 158 158A
3- st at e noninvert ing out put s 257B 257A 257
3- st at e noninvert ing out put s 258B 258A
Dual 4- input Mult iplexer
2- st at e noninvert ing out put s 153 153 153
2- st at e invert ing out put s 352 352
3- st at e invert ing out put s 353 353
8- input Mult iplexer
16- input Mult iplexer
2- st at e noninvert ing out put s 150
As can be seen from t he I Cs list ed above, t here are available, a variet y of
combinat ions of paramet ers in t he case of 2- input mult iplexers, while in t he ot her
cases, t he main choice is bet ween t he normal out put and 3- st at e out put s.
Mult iplexer I Cs can be used for
select ion of dat a from mult iple sources
realising logic expressions
These t wo aspect s are explored in t his Unit
Dat a Sel ect i on
The mult iplexer was mainly designed for select ing dat a from several sources. For
example, if we are required t o select an 8- bit dat a from one of four possible sources,
t hen, it can be realised t hrough four dual 4- input mult iplexers, like 74LS153. The
circuit t hat realises such a dat a select ion is shown in figure 3

EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
C
B
A
L
H
Y

FI G. 3: Circuit for select ing 8- bit dat a from four sources
Anot her convent ional use of t he mult iplexers is one of t ime- division gat ing of several
dat a lines on t o a t ransmission channel using SELECT lines. This is done by using a
` Mult iplexer' as t he sending unit , and a ` Demult iplexer' as a receiving unit . The
sending end of such a t ransmission syst em which mult iplexes 32 dat a lines is shown
in Figure 4.

FI G. 4: 1- of- 32 dat a select or

Mul t i pl ex er s f or Logi c Real i zat i on
The mult iplexer also finds applicat ion in realising logical funct ions, somet imes in a
more effect ive manner t han wit h t he gat es. Consider t he following example.
Ex ampl e 1: Consider t he funct ion Y
Y = A
/
B
/
C
/
+ A
/
BC + AB
/
C + ABC
/

The general expression t hat gives t he input - out put relat ionship of a mult iplexer is
Y = m
0
( I P0) + m
1
( I P1) + - - - - m
2
n
( I P2
n
)
This expression for Y can be writ t en in t erms of MI NTERMS as:
Y = m
0
+ m
3
+ m
5
+ m
6

EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
ch9
ch10
ch11
ch12
ch13
ch14
ch15
ch16
ch25
ch26
ch27
ch28
ch29
ch30
ch31
ch32
s3
s4
ch17
ch18
ch19
ch20
ch21
ch22
ch23
ch24
ch1
ch2
ch3
ch4
ch5
ch6
ch7
ch8
s3
s4
s0
s1
s2
s3
s4
This expression can in t urn be rewrit t en as:
Y = m
0
( I P0= 1) + m
1
( I P1= 0) + m
2
( I P2= 0) + m
3
( I P3= 1) + m
4
( I P4= 0) +
m
5
( I P5= 1) + m
6
( I P6= 1) + m
7
( I P7= 0) .
Connect t he logic variables A, B, and C t o t he Select I nput s and binary input s t o t he
Dat a lines of an 8- input mult iplexer as indicat ed in t he figure 5. This is a very
general met hod and it allows any expression of n- logic variables t o be realized by a
2
n
- input mult iplexer.
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
C
B
A
L
H
Y

FI G. 5: Realisat ion of t he funct ion given in example 1
Ex ampl e 2: I mplement t he logic expression given below, using 74LS251 ( 8- input
mult iplexer)
Y = ( 1, 2, 4, 7, 8, 9, 13) .
X1 X2 X3 X4 Y X1 X2 X3 Y
0 0 0 1 1 0 0 0 X4
0 0 1 0 1 0 0 1 X4
/

0 1 0 0 1 0 1 0 X4
/

0 1 1 1 1 0 1 1 X4
1 0 0 0 1 0 1 1 X4
/

1 0 0 1 1 1 0 0 X4
1 1 0 1 1 1 1 0 X4

Let X1, X2, X3 and X4 be t he four variables of which X1 is t he most significant and
X4 is t he least significant variable. All variables are considered Assert ed High.
Consider t he t rut h t able given in t he following. A 4- input funct ion can be reduced t o
a 3- input funct ion by expressing t he out put Y in t erms of X4.
Y = X4 ( 0, 3, 4, 6) + X4
/
( 1, 2, 4)
= X4 ( 0, 3, 6) + X4
/
( 1, 2) + ( 1) 4
The realisat ion of t he above expression wit h a 3- input ( 8- dat a input ) mult iplexer is

EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y
X4
X3
X2
X1
L
H

FI G. 6: Realisat ion of t he logical expression in t he example 2
What happens when some of t he variables are Assert ed Low while ot hers are
Assert ed High? Mult iplexers can st ill be used advant ageously t o realise expressions
using variables wit h mixed assert ion levels. One simple met hod is t o change t he
assert ion levels of all t he signals t o High level by using invert ers. Let X1 and X2
variables in t he logic expression given in t he example 2 be Assert ed Low, while t he
variables X3 and X4 be Assert ed High. I mplement at ion of t his expression using t he
invert ers along wit h t he mult iplexer is shown in Figure 7.

FI G. 7: Realisat ion of t he expression in Example 2 when some of t he variables are
Assert ed Low
EN
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y
X3
X2'
X1'
X4
H
L
Digital Electronics
Demultiplexers
N.J. Rao
Demultiplexers
It is a combinational circuit that asserts one of several
outputs in response to a unique input code.
It is a unit with n-inputs and m-outputs, where m < 2
n
.
An output switches from Not Asserted state to an
Asserted state, when the input code is switched to a
specific one.
When m = 2
n
, each one of the outputs can be associated
with a Minterm of n-variables.
Hence, such a decoder is known as Minterm Recogniser
3-input demultiplexer
0
1
2
EN
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
Each one of the outputs have an AND (G) dependence on one of
the input codes.
Enable input can be used to disable/enable the entire functional
unit.
LSTTL/HCMOS Demultiplexers
Dual 1-of-4 demultiplexer
2-state AL outputs: 74LS139/
74HC139A
2-state AL outputs and common addressing: 74LS155
AL OC outputs and common addressing: 74LS156
3-state AH outputs: 74LS539
1-of-8 demultiplexer
AL outputs and 3 Enable inputs: 74LS138/
74HC138A
AL outputs, 2 Enable, Address latch with latch enable: 74LS137
1-of-10 demultiplexer (2-state AL outputs): 74LS42
1-of-16 demultiplexer (AL outputs and 2 Enable inputs):74LS154/
74HC154
Uses of a demultiplexer
Demultiplexing
Realisation of logic functions
Decoding
An 8-channel multiplexer-demultiplexer combination
0
1
2
E N
G
0
7
_
DMUX
0
1
2
3
4
5
6
7
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y DATA
SO
S1
S2
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
1-to-32 demultiplexer
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
D MUX
&
H
1 3 8
}
O1
O2
O3
O4
O5
O6
O7
O8
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
D MUX
&
H
1 38
}
O9
O1 0
O1 1
O1 2
O 13
O1 4
O1 5
O1 6
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
D MUX
&
H
1 38
}
O1 7
O1 8
O1 9
O2 0
O 21
O2 2
O2 3
O2 4
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
D MUX
&
H
1 3 8
}
O2 5
O2 6
O2 7
O2 8
O2 9
O3 0
O3 1
O3 2
EN
0
1
} G
_0
3
0
1
2
3
DMUX '13 9
X2
X1
X5
X4
X3
Delays
74LS138: Propagation delays
Address to output t
PLH
= 27 ns t
PHL
= 39 ns (max)
Enable to output t
PLH
= 26 ns t
PHL
= 38 ns (max)
Address to output t
PLH
= 29ns t
PHL
= 38 ns (max)
Enable to output t
PLH
= 24 ns t
PHL
= 32 ns (max)
The worst case delay time from the most significant bits of
the input address to output of is 76 ns
The delay from the data input to output is 70 ns
Realization of Logic functions
Demultiplexer is essentially a Minterms generator
Do the necessary ORing of the required Minterms to
realize the logic expression.
One demultiplexer which generates all the Minterms, and
a number of OR gates can realize multiple logic
expressions of the same set of variables
Example 1
Y1 = S (0, 2, 4, 5, 6, 11)
Y2 = S (0, 3, 4, 7, 8)
Y3
/
= S (1, 3, 6, 14)
Y4 = S (8, 13, 15)
X0'
X1'
X2'
X3'
X4'
X5'
X6'
X7'
X8'
X9'
X10'
X11'
X12'
X13'
X14'
X15'
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
&
DMUX-154
0
1
2
3
-D
-C
-B
-A
G
0
_
7
X0'
X2'
X4'
X5'
X6'
X11'
X0'
X3'
X4'
X7'
X8'
X1'
X3'
X6'
X14'
X8'
X13'
X15'
Y1
Y2
Y3'
Y4
EN
Example 1 (2)
Address to output t
PLH
= 36 ns t
PHL
= 33 ns (max)
Enable to output t
PLH
= 30 ns t
PHL
= 27 ns (max)
74LS20: Propagation delay t
PLH
= t
PHL
= 15 ns (max)
74LS30: Propagation delay t
PLH
= 15 ns, t
PHL
= 20 ns (max)
Net Propagation delay = 36 + 20 = 56 n secs (max)
Realization by INVERTERS and NAND gates results in a
propagation delay of 55 (15+20+20) ns
Demultiplexer solution to the realisation of logical
expressions can reduce the net chip count
Example 2
Y1 = (0, 2, 5, 6)
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
X3
X2
H
138
Y1
X1
Example 2 (2)
If one of the variables X1 is Asserted Low
X1 X2 X3 /X1 X2 X3 Y
0 0 0 1 0 0 1
0 1 0 1 1 0 1
1 0 1 0 0 1 1
1 1 0 0 1 0 1
Example 2 (3)
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
X3
X2
H
138
X1 Y1 /
Demult iplexer
A decoder/ demult iplexer is a combinat ional circuit t hat assert s one of several out put s
in response t o a unique input code. I t is a unit wit h n- input s and m- out put s, where
m < 2
n
. An out put swit ches from Not Assert ed st at e t o an Assert ed st at e, when t he
input code is swit ched t o a specific one. When m = 2
n
, each one of t he out put s can
be associat ed wit h a Mint erm of n- variables. Hence, such a decoder is known as
Mint erm Recogniser. Schemat ic of a 3- input demult iplexer is shown in figure 1.

0
1
2
EN
0
1
3
4
5
6
7
2
G
0
7
_
DMUX

FI G. 1: Schemat ic of a 3- input demult iplexer
I n t he demult iplexer illust rat ed, each one of t he out put s have an AND ( G)
dependence on one of t he input codes, while, Enable input s can be used t o
disable/ enable t he ent ire funct ional unit . Some of t he available decoders/
demult iplexers in t he bipolar and CMOS families are list ed below:
Dual 1- of - 4 demul t i pl ex er
2- st at e AL out put s: 74LS139/ 74HC139A
2- st at e AL out put s and common addressing: 74LS155
AL OC out put s and common addressing: 74LS156
3- st at e AH out put s: 74LS539
1- of - 8 demul t i pl ex er
AL out put s and 3 Enable input s: 74LS138/ 74HC138A
AL out put s, 2 Enable, Address lat ch wit h lat ch enable: 74LS137
1- of - 10 demul t i pl ex er ( 2- st at e AL out put s) : 74LS42
1- of - 16 demul t i pl ex er ( AL out put s and 2 Enable input s) : 74LS154/ 74HC154
The uses of a demult iplexer include t radit ional demult iplexing operat ions as well as
realisat ion of logic funct ions.

Decodi ng and Demul t i pl ex i ng Funct i ons
One of t he t radit ional uses of a demult iplexer is t o use it in combinat ion wit h a
mult iplexer t o t ransmit a number of signals over a single line. An 8- channel
mult iplexer- demult iplexer combinat ion is shown in t he figure 2.

FI G. 2: An 8- channel mult iplexer- demult iplexer combinat ion
Not ice t hat one of t he Enable input s of t he demult iplexers is used as it s dat a input .
Though t his illust rat ion indicat es t hat t he address lines are t ied t oget her, in an act ual
signal t ransmission unit t hat uses such a MUX- DEMUX combinat ion a different
met hod will have t o be used t o change t he addresses of bot h t he unit s
simult aneously.
Demult iplexers/ decoders are ext ensively used in int erfacing display unit s in a digit al
syst em wit h t he rest of t he hardware, and in decoding t he addresses of t he memory
syst ems. I n some of t he applicat ions, it may become necessary t o st ring a number of
demult iplexers t oget her. Figure 3 present s a 1- t o- 32 demult iplexer using four
74LS138 unit s and one 74LS139.

0
1
2
E N
G
0
7
_
DMUX
0
1
2
3
4
5
6
7
0
1
2
1
2
3
4
5
6
7
0
G
0
7
MUX
Y DATA
SO
S1
S2
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8

FI G. 3: 1- t o- 32 demult iplexer
The import ant charact erist ics t he designer must comput e and t ake int o account are
t he delay t imes from t he dat a and t he address input s t o t he out put . The delay t imes
associat ed wit h 74LS138 are:
74LS138: Propagat ion delays
Address t o out put t
PLH
= 27 ns t
PHL
= 39 ns ( max)
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
H
138
}
O1
O2
O3
O4
O5
O6
O7
O8
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
H
138
}
O9
O10
O11
O12
O13
O14
O15
O16
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
H
138
}
O17
O18
O19
O20
O21
O22
O23
O24
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
H
138
}
O25
O26
O27
O28
O29
O30
O31
O32
EN
0
1
}
G
_0
3
0
1
2
3
DMUX '139
X2
X1
X5
X4
X3
Enable t o out put t
PLH
= 26 ns t
PHL
= 38 ns ( max)
PLH
= 29ns t
PHL
= 38 ns ( max)
PLH
= 24 ns t
PHL
= 32 ns ( max)
The worst case delay t ime from t he most significant bit s of t he input address t o
out put of 1- t o- 32 demult iplexer is 76 n secs. The delay from t he dat a input t o out put
is 70 n secs.
Real i zat i on of Logi c f unct i ons
A logical expression in t he Sum- of- Product form is not hing but ORing of a select ed
set of Mint erms. As a demult iplexer is essent ially a Mint erms generat or, it is possible
t o use a demult iplexer t o realise a logical expression along wit h a gat e t o do t he
necessary ORing of t he required Mint erms. I n comparison t o t he mult iplexer, a
demult iplexer needs addit ional hardware t o realise a logical expression. However,
t his can be t urned int o an advant age in sit uat ions where more t han one expression
of t he same logic variables has t o be implement ed. One demult iplexer which
generat es all t he Mint erms, and a number ( equal t o t he number of logical
expressions) of OR gat es, will suffice. The following example illust rat es t his use of
demult iplexers.
Ex ampl e 1: Realise t he following logical expressions using demult iplexers:
Y1 = ( 0, 2, 4, 5, 6, 11)
Y2 = ( 0, 3, 4, 7, 8)
Y3/ = ( 1, 3, 6, 14)
Y4 = ( 8, 13, 15)
As t he expressions are in four variables, 74LS154 ( 1- t o- 16 demult iplexer) is used.
The hardware realisat ion is shown in t he figure4. Not e t hat t he OR funct ion can
act ually be realised by a NAND gat e, as t he out put s of t he demult iplexer are
Assert ed Low.
X0'
X1'
X2'
X3'
X4'
X5'
X6'
X7'
X8'
X9'
X10'
X11'
X12'
X13'
X14'
X15'
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
&
DMUX-154
0
1
2
3
-D
-C
-B
-A
G
0
_
7
X0'
X2'
X4'
X5'
X6'
X11'
X0'
X3'
X4'
X7'
X8'
X1'
X3'
X6'
X14'
X8'
X13'
X15'
Y1
Y2
Y3'
Y4
EN

FI G. 4: Realisat ion of t he funct ions given in Example 1
The Propagat ion delay of t his circuit can be comput ed as:
PLH
= 36 ns t
PHL
= 33 ns ( max)
PLH
= 30 ns t
PHL
= 27 ns ( max)
74LS20: Propagat ion delay
t
PLH
= t
PHL
= 15 ns ( max)
74LS30: Propagat ion delay
t
PLH
= 15 ns, t
PHL
= 20 ns ( max)
Net Propagat ion delay = 36 + 20 = 56 n secs ( max)
I f t hese expressions are t o be realised using I NVERTERS and NAND gat es, we require
t hree- level gat ing ( one level of I NVERTERS and t wo levels of NANDs) , which would
result in a propagat ion delay of 55 ( 15+ 20+ 20) n secs. Hence, t he demult iplexer
solut ion does not give any speed advant age over t he t radit ional realisat ion of logical
expressions using gat es, whereas, t he mult iplexer realisat ion gave a marginal speed
advant age. However, demult iplexer solut ion t o t he realisat ion of logical expressions
can great ly reduce t he net chip count , at least in some cases.
I t is also possible t o t ake int o account if some of t he variables in t he logic expression
are Assert ed Low. The solut ion is very similar t o t he procedure adapt ed in t he case of
mult iplexers, viz. , eit her t hrough changing assert ion levels of t he Assert ed Low
variables or by t aking int o account t he fact t hat incompat ibilit y at t he input result s in
t he complement at ion of t he variables in t he out put logic expression. This is
illust rat ed in t he example 2
Ex ampl e 2: Realise t he logical expression Y1 = ( 0, 2, 5, 6) of t hree variables X1,
X2 and X3 using 74LS138. I ndicat e how t he realizat ion of t he expression would vary
if t he variable X1 is changed t o an assert ed- low variable
Figure 5 shows t he realizat ion of logical expression for Y1 by a demult iplexer solut ion
where.

FI G. 5: Realisat ion of t he funct ion given in t he Example 2
The modified t rut h- t able for t his expression is as given in t he following. The
corresponding hardware realisat ion of t he logic expression, where t he assert ion level
of t he variable X1 is not alt ered is given in t he figure 6.
X1 X2 X3 / X1 X2 X3 Y
0 0 0 1 0 0 1
0 1 0 1 1 0 1
1 0 1 0 0 1 1
1 1 0 0 1 0 1

FI G. 6: Modified realisat ion of t he funct ion given in t he example 2
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
X3
X2
H
138
Y1
X1
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
X3
X2
H
138
X1 Y1 /
Digital Electronics
Addition
N.J. Rao
Addition
Addition is the most fundamental arithmetic operation.
All the other arithmetic operations can be expressed in
terms of addition.
It is desirable for a digital designer to be familiar with the
realisation of simple arithmetic functions using
combinational circuits.
Many of these conventions and procedures are carried
over to the software level while designing with LSIs.
Simple Adders
Adding two one-bit numbers
1 0 1 1
0 1 0 1
0 1 1 0
0 0 0 0
C S B A S = A B
/
+ A
/
B = A B
C = A . B
A
B
S
C
Addition of multi-bit numbers
This requires an adder unit that performs addition with three bits.
Such an adder is called Full-Adder.
1 1 1 1 1
1 0 0 1 1
1 0 1 0 1
0 1 0 0 1
1 0 1 1 0
0 1 0 1 0
0 1 1 0 0
0 0 0 0 0
C
i
S
i
C
i-1
B
i
A
i
Addition of multi-bit numbers (2)
Si = A
i
/
B
i
/
C
i-1
+ A
i
/
B
i
C
i-1
/
+ A
i
B
i
/
C
i-1
/
+ A
i
B
i
C
i-1
Ci = A
i
/
B
i
C
i-1
+ A
i
B
i
/
C
i-1
+ A
i
B
i
C
i-1
/
+ A
i
B
i
C
i-1
= B
i
C
i-1
+ A
i
C
i-1
+ A
i
B
i
S
C
o u t
i -1
Addition of multi-bit numbers (3)
Full adder in terms of half-adders
B
i
A
i
C
i-1
A
B
S
C
A
B
S
S
i
C
i
4-bit adders
E
CO CI
B
A
E
CO CI
B
A
E
CO CI
B
A
E
CO CI
B
A
A1
B1
Cin
A2
B2
A3
B3
S1
S2
S3
S4
C4
A4
B4
FA
FA
FA
FA
The carry bit will have to
ripple through all the stages
and the delay of the four bit
adder will be four times the
delay associated with single
bit full adders.
MSI adders
74LS283 (4-bit full adder)
74LS181 (4-bit arithmetic logic unit)
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
4
CP
CG
CO
P=Q
CI
ALU'181
CI CO
'283
0
3
0
3
0
3
P
Q
E
t
PLH
t
PHL
CI to S (max) 24 24 ns
CI to CO (max) 17 22 ns
A, B to S (max) 24 24 ns
A, B to CO (max) 17 17 ns
16-bit adders
CI CO
'283
0
3
0
3
0
3
P
Q
E
CI CO
'283
0
3
0
3
0
3
P
Q
E
CI CO
'283
0
3
0
3
0
3
P
Q
E
CI CO
'283
0
3
0
3
0
3
P
Q
E
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
C15
C0
A0
A1
A2
A3
B0
b1
B2
B3
A4
A5
A6
A7
B4
B5
B6
B7
A9
A10
A11
B8
B9
B10
B11
A8 A12
A13
A14
A15
B12
B13
B14
B15
Addition time = t
P
(CI1 to CO1) + t
P
(CI2 + CO2) + t
P
(CI3 to CO3) +
t
P
(CI4 to S)
= 22 + 22 + 22 + 24
= 90 ns
Addition time is 108 ns if 74LS181 is used
Addition time is 42 ns if 74S181 is used
Limitations of 4-bit adders
Internal circuitry of the 4-bit adders is optimised to
provide minimum delay
The carry bit has to ripple from one group of bits to the
next group in the case of 16-bit, 32-bit and 64-bit adders
This will increase the addition time significantly.
Add extra circuitry that can determine the final carry bit
without waiting for it to ripple through all the stages.
Such an arrangement is called Carry Look Ahead
feature.
Carry Look Ahead
Carry Generator, Gi = Ai Bi
Carry Propagator, Pi = Ai + Bi
C1 = A0 B0+ C0 (A0 + B0) = G0 + C0 P0
C2 = A1 B1 + C1 (A1 + B1)
= G1 + C1 P1 = G1 + P1 G0 + P1 P0 C0
C3 = A2 B2 + C2 (A2 + B2) = G2 + C2 P2
= G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = A3 B3 + C3 (A3 + B3) = G3 + C3 P3
= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 +
P3 P2 P1 P0 C0
Carry Look Ahead (2)
74LS283 incorporates this feature to minimise the
associated delay.
74LS182, called Carry Look Ahead Generator, can
accept these group-carry signals from the four ALUs to
generate final carry bit in the case of 16-bit addition
If 64-bit adder is to be built, a second level carry look
ahead generator, taking the group carry signals from
each group of 16 bits, will have to be used.
16-bit adder with carry look ahead
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
H
L
L
H
L
H
H
H
H
L
L
L
LL
L
L
H
H
L
L
L
A8
A9
A10
A11
A12
A13
A14
B12
B13
B14 B10
B9
B8
A4
B4
A5
B5
A6
B6
A7
B7 B11
A15
B15
A0
B0
A1
B1
A2
B2
A3
B3
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
CP0
CP1
CP2
CP3
CG0
CG1
CG2
CG3
CP
CG
C00
C01
CO2
'182
31 31
31 31
Subtraction
Normally subtraction is performed by changing the sign of
subtrahend and adding it to the minuend.
Ways of representing the signed numbers:
sign-magnitude
ones complement
twos complement forms
BCD representations
Addition and subtraction
(2s complement)
Add the two numbers and ignore the carry
Overflow occurs when there is a carry into the sign-bit
position and no carry out of the sign-bit position, and
vice-versa
The overflow may, therefore be realised by
The sign changing is done by complementing the
subtrahend and adding a 1 in the least significant bit
position.
A mode signal has to be created to instruct the unit whether
the addition or subtraction should take place.
9-bit 2s complement adder
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
'86
'86
OF
1
0
E0
E1
E2
E3
E5
E4
E6
E7
E8
B8
B7
B6
B5
B4
B0
B1
B2
B3
B
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
'86
ADD'/SUB
Addi t i on
Addit ion is t he most fundament al arit hmet ic operat ion. All t he ot her arit hmet ic
operat ions can be expressed in t erms of addit ion. Some t ime ago t he design of t he
cent ral processing unit and t he consequent speed of t he digit al comput er depended
great ly on t he design of t he adder hardware. Design of a mult i- bit fast adder was
one of t he skills t hat a digit al designer had t o acquire in t he early era of comput ers.
The availabilit y of low cost general purpose LSI circuit s like microprocessors and
digit al signal processors, and t he availabilit y cost effect ive t echnology for realising
special purpose LSI s changed t he scene radically. At present t he need for designing
an arit hmet ic unit from a large collect ion of SSI and MSI circuit s does not exist .
However, it is desirable for a digit al designer t o be familiar wit h t he realisat ion of
simple arit hmet ic funct ions using combinat ional circuit s. Many of t hese convent ions
and procedures are carried over t o t he soft ware level while designing wit h LSI s. This
Unit present s only t he very basics of adders based on combinat ional circuit s.
Si mpl e Adder s
The simplest binary addit ion is t o add t wo one- bit numbers. When t he sum of t wo
bit s is more t han 1 it is considered as an overflow and we generat e a carry bit . The
t rut h- t able associat ed wit h t his addit ion process is given in t he following, wit h A and
B as t he input one- bit numbers, S as t he sum and C as t he carry.
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1

0 1

The combinat ional circuit for t he addit ion of t wo one- bit numbers is known as Half
Adder. The logical expressions for t he t wo out put s, S and C, may be writ t en from
t he above t rut h- t able as;
S = A B
/
+ A
/
B = A B
C = A . B
The gat e level realisat ion of a half- adder is shown in t he figure 1.

A
B
S
C

FI G. 1: Half adder
A half- adder has only provision t o add t wo bit s. I f mult i- bit numbers are t o be added
provision is t o be made t o t ake t he carry bit s coming from t he previous st ages. This
requires an adder unit t hat performs addit ion wit h t hree bit s. Such an adder is called
Full- Adder. Let A
i
and B
i
be t he i' t h bit s of an n- bit number, C
i- 1
be t he carry bit from
t he i- 1 st age of addit ion, S
i
be t he i' t h bit of t he sum, and C
i
be t he carry bit from t he
i' t h st age of addit ion. The t rut h- t able of a full adder is
A
i
B
i
C
i- 1
S
i
C
i

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1

1 1

The logical expressions for t he Sum and Carry bit s can be writ t en as in t he following
Si = A
i
/
B
i

/
C
i- 1
+ A
i
/
B
i
C
i- 1
/
+ A
i
B
i
/
C
i- 1
/
+ A
i
B
i
C
i- 1

Ci = A
i
/
B
i
C
i- 1
+ A
i
B
i
/
C
i- 1
+ A
i
B
i
C
i- 1
/
+ A
i
B
i
C
i- 1

= B
i
C
i- 1
+ A
i
C
i- 1
+ A
i
B
i

The realisat ion of t he full adder using gat es is shown in t he figure 2.

FI G. 2: Full adder realised wit h basic gat es
S
C
out
-1
However, t he full adder can also be realised in t erms of half- adders as shown in t he
figure 3.

FI G. 3: Full adder realised by t wo half- adders
Adders for adding single bit numbers are of hardly any use in pract ice. Addit ion of
mult iple bit numbers requires cascading of a number of full adders. A 4- bit adder
put t oget her wit h four single bit full adders is shown in t he figure 4.

FI G. 4: 4- bit binary adder
I t may be not ed t hat t he carry bit will have t o ripple t hrough all t he st ages and t he
delay of t he four bit adder will be four t imes t he delay associat ed wit h single bit full
adders. Besides, building such a circuit wit h basic gat es or half adders requires large
number of SSI circuit s. There are t wo MSI circuit s t hat offer four bit addit ion,
available from all t he vendors. These are 74LS283 ( 4- bit full adder) and 74LS181 ( 4-
bit arit hmet ic logic unit ) . 74LS181 is more t han a adder, and can perform a variet y
of arit hmet ic and logic funct ions which can be select ed by a set of cont rol and mode
signals The logical symbols of 74LS283 and 74LS181 are shown in t he figure 5.

B
i
A
i
C
i-1
A
B
S
C
A
B
S
S
i
C
i
CO CI
B
A
CO CI
B
A
CO CI
B
A
CO CI
B
A
A1
B1
Cin
A2
B2
A3
B3
S1
S2
S3
S4
C4
A4
B4
FA
FA
FA
FA
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
4
CP
CG
CO
P=Q
CI
ALU'181
CI CO
'283
0
3
0
3
0
3
P
Q

FI G. 5: Schemat ic represent at ions of 74LS181 and 74LS283
The int ernal circuit ry of t he 74LS283 is opt imised t o give minimum possible delay
t imes bet ween all t he input s and out put s. These propagat ion delays are list ed in t he
following:
t
PLH
t
PHL

CI t o ( max) 24 24 ns
CI t o CO ( max) 17 22 ns
A, B t o ( max) 24 24 ns
A, B t o CO ( max) 17 17 ns

Adder s w i t h Feat ur es
I t oft en becomes necessary t o build adders for numbers much larger t han 4- bit
numbers. A 16- bit adder built wit h four unit s of 74LS283s is shown in t he figure 6.
CI CO
'283
0
3
0
3
0
3
P
Q
CI CO
'283
0
3
0
3
0
3
P
Q
CI CO
'283
0
3
0
3
0
3
P
Q
CI CO
'283
0
3
0
3
0
3
P
Q
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
C15
C0
A0
A1
A2
A3
B0
b1
B2
B3
A4
A5
A6
A7
B4
B5
B6
B7
A9
A10
A11
B8
B9
B10
B11
A8 A12
A13
A14
A15
B12
B13
B14
B15

FI G. 6: 16- bit adder using 74LS283s
The most import ant paramet er of an adder is t he addit ion t ime. The addit ion t ime
for t he 16- bit adder using 74LS283s is given by;
Addit ion t ime = t
P
( CI 1 t o CO1) + t
P
( CI 2 + CO2) + t
P
( CI 3 t o CO3) + t
P
( CI 4 t o )
= 22 + 22 + 22 + 24
= 90 ns
I f 74LS283 is replaced by 74LS181 t he delay t ime will be slight ly larger, as t he
circuit ry wit hin t his unit is more complex. The net addit ion t ime for a 16- bit adder
will be 108 ns. I f a fast er unit like 74S181 is used t he addit ion t ime get s reduced t o
42 ns.
While t he int ernal circuit ry of t he available adder unit s is opt imised t o provide
minimum delay for t he addit ion of 4- bit numbers, t he carry bit has t o ripple from one
group of bit s t o t he next group in t he case of a 16- bit adder. When t he addit ion
involves numbers t hat are 32- bit or 64- bit long, t he carry bit will have t o ripple
t hrough 8 and 16 st ages of adders respect ively. This will increase t he addit ion t ime
significant ly. One met hod of reducing t he addit ion t ime is t o add ext ra circuit ry t hat
enables t he det erminat ion of t he final carry bit wit hout wait ing for it t o ripple t hrough
all t he st ages. Such an arrangement is called Carry Look Ahead feat ure. This is
based on deciding independent ly whet her a part icular st age in addit ion generat es a
carry bit or merely propagat es t he carry bit coming from t he previous st age. Let Ai
and Bi be t he t wo i' t h bit s of mult i- bit numbers A and B respect ively. A carry bit is
generat ed from t his st age t o t he next one, whet her t here is a carry bit from t he
previous st age or not , if bot h bit s are 1s. The carry bit from t he previous st age is
propagat ed t o t he next st age if one of t he bit s or bot h of t hem are 1s. These t wo
funct ions, namely carry generat e and carry propagat e, can be defined as;
Carry Generat or, Gi = Ai Bi
Carry Propagat or, Pi = Ai + Bi
Let , in a 4- bit adder, CI be t he carry bit int o t he first st age and C1, C2, C3 and C4 be
t he carry bit s from t he four st ages of addit ion. G0, G1, G2 and G3 are t he carry
generat es and P0, P1, P2 and P3 are t he carry propagat es from t he four st ages of
addit ion of t he 4- bit adder. Then t he relat ionships can be st at ed as below:
C1 = A0 B0+ C0 ( A0 + B0) = G0 + C0 P0
C2 = A1 B1 + C1 ( A1 + B1) = G1 + C1 P1 = G1 + P1 G0 + P1 P0 C0
C3 = A2 B2 + C2 ( A2 + B2) = G2 + C2 P2
= G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = A3 B3 + C3 ( A3 + B3) = G3 + C3 P3
= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
C4 can, t herefore, be generat ed independent ly of C1, C2, and C3 as P and G
funct ions can be generat ed from t he A and B input s direct ly. This is known as t he
carry look ahead feat ure. The circuit ry wit hin t he unit 74LS283 incorporat es t his
feat ure t o minimise t he associat ed delay. But it becomes necessary t o have
addit ional circuit ry t o incorporat e carry look ahead feat ure when an adder has t o be
designed for numbers more t han four. This can be done t hrough generat ing group
carry generat e and group carry propagat e signals. I n t he cont ext of commercially
available I Cs, four bit s const it ut e a group. The 74LS181 Arit hmet ic Logic Unit ( ALU)
generat es bot h group carry generat e and group carry propagat e signals. These
signals can be combined across st ages in a manner similar t o t he relat ionships list ed
above. 74LS182, called Carry Look Ahead Generat or, can accept t hese group- carry
signals from t he four ALUs t o generat e final carry bit in t he case of 16- bit addit ion,
as shown in t he figure 7.
I f 64- bit adder is t o be built , a second level carry look ahead generat or, t aking t he
group carry signals from each group of 16 bit s, will have t o be used.
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
P0
Q0
F0
P1
Q1
F1
P2
Q2
P3
Q3
F2
F3
0
4
M
0
CP
CG
CO
P=Q
CI
ALU'181
H
L
L
H
L
H
H H
H
L
L
L
LL
L
L
H
H
L
L
L
A8
A9
A10
A11
A12
A13
A14
B12
B13
B14
B10
B9
B8
A4
B4
A5
B5
A6
B6
A7
B7 B11
A15
B15
A0
B0
A1
B1
A2
B2
A3
B3
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
CP0
CP1
CP2
CP3
CG0
CG1
CG2
CG3
CP
CG
C00
C01
CO2
'182
31 31
31 31

FI G. 7: 16- bit adder wit h carry look- ahead feat ure
Combi ned Addi t i on and Subt r act i on
Normally subt ract ion is performed by changing t he sign of subt rahend and adding it
t o t he minuend. However, t here are several ways of represent ing t he signed
numbers. These include sign- magnit ude, ones complement , t wos complement forms
and BCD represent at ions. Here we consider addit ion and subt ract ion operat ions wit h
numbers represent ed in t wos complement form. The reader is urged t o work out t he
hardware for ot her represent at ions as exercises.
The algorit hm for addit ion of t wo t wos complement numbers is
Add t he t wo numbers and ignore t he carry
The algorit hm for overflow is
Overflow occurs when t here is a carry int o t he sign- bit posit ion and no carry
out of t he sign- bit posit ion, and vice- versa
The overflow may, t herefore be realised by

The sign changing is done by complement ing t he subt rahend and adding a 1 in t he
least significant bit posit ion. A mode signal, t herefore, has t o be creat ed t o inst ruct
t he arit hmet ic unit whet her t he addit ion or subt ract ion should t ake place. A 9- bit
t wos complement adder- subt ract or is shown in t he figure 8.
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
CI
CO
A1
B1
A2
B2
A3
B3
A4
B4
S1
S2
S3
S4
'86
'86
OF
1
0
0
1
2
3
5
4
6
7
8
8
7
6
5
4
0
1
2
3
0
1
2
3
4
5
6
7
8
'86
ADD'/SUB

FI G. 3: 9- bit t wos complement adder- subt ract or

APPENDI X: DEPENDENCY NOTATI ON
I nt r oduct i on: Dependency Not at ion refers t o t he symbolic language developed as a part
of t he St andard ANSI / I EEE St d- 91- 1984. This not at ion was evolved t o indicat e t he
relat ionship of each input of a digit al logic circuit t o each out put wit hout explicit ly showing
t he int ernal logic. However, t his not at ion can only be used wit h regard t o circuit s of
medium complexit y and MSI s. When t he MSI s are represent ed in t his not at ion t here would
not be any need t o const ant ly refer t o t he dat a sheet t o underst and t he logical relat ionship
bet ween signals. This Appexdix int r oduces t he basics of Dependency Not at ion. I t s use wit h
regard t o specific I Cs will be elaborat ed in t he relat ed Modules. The mat erial present ed in
t he following should be sufficient t o underst and and t o draw t he logic diagrams needed for
t he design of digit al syst ems of reasonable complexit y.
Gener al Def i ni t i ons: I EEE St andard support s t he not ion of bubble- t o- bubble logic design
in wit h some import ant t erms encount ered are explained in t he following.
Logi c St at e: One of t wo possible abst ract st at es t hat may be t aken on by a logic ( binary)
variable.
0- St at e: The logic st at e represent ed by t he binary number 0 and usually st anding for Not
Assert ed st at e of a logic variable.
1- St at e: The logic st at e represent ed by t he binary number 1 and usually st anding for
Assert ed st at e of a logic variable.
Ex t er nal Logi c St at e: A logic st at e assumed t o exist out side symbol out line; ( 1) on an
input line prior t o any ext ernal qualifying symbol at t he input or ( 2) on out put line beyond
any ext ernal qualifying symbol at t hat out put .
I nt er nal Logi c St at e: A logic st at e assumed t o exist inside a symbol out line at an input
or an out put .
Qual i f yi ng Symbol : I t is graphics or t ext added t o t he basic out line of a device logic
symbol t o describe t he physical or logical charact erist ics of t he device. The ext ernal
qualifying symbol ment ioned above is t ypically an inversion bubble, which denot es a
negat ed input or out put , for which t he ext ernal 0- st at e corresponds t o t he int ernal 1-
st at e. I nt ernal 1- st at e may be int erpret ed as t he corresponding signal get t ing assert ed.
Similarly int ernal 0- st at e may be int erpret ed as t he corresponding signal get t ing not -
assert ed.
A symbol for a digit al circuit comprises of an out line or a combinat ion of lines t oget her
wit h one or more qualifying symbols. Lines on t he left hand side indicat e input s while t he
lines on t he right hand side indicat e out put s. This concept of composing t he symbol is
illust rat ed in t he figure 1.
*
* *
* *
* *
*
General qualifying
Symbol
Output
lines
Outline

FI G. 1: Composit ion of a logic circuit symbol
General addit ional informat ion may be included in a symbol out line in t he diagrams for
digit al circuit s. A qualifying symbol is included at t he t op t o indicat e t he general funct ion
performed by t he logic circuit under considerat ion. Some of t hese qualifying symbols t o
indicat e t he device funct ions are list ed in t he following.
SYMBOL DEVI CE FUNCTI ON
> OR
& AND
= 1 Exclusive OR
= All input s at t he same st at e
2k Even number of input s Assert ed
2k+ 1 Odd number of st at es Assert ed
Buffer
Schmit t Trigger
X/ Y Code Convert er
MUX Mult iplexer
DX Demult iplexer
Adder
P - Q Subt ract or
CPG Carry look- ahead generat or
ALU Arit hmet ic logic unit
COMP Magnit ude comparat or
The input and out put lines will have qualifying symbols inside t he symbol out lines. These
qualifying symbols are illust rat ed in t he following.
SYMBOL SI GNAL FUNCTI ON
Assert ed Low input ( Ext ernal 0 = I nt ernal 1)

Assert ed Low out put ( I nt ernal 1 = Ext ernal 0)

Assert ed High input ( Ext ernal 1 = I nt ernal 1)

Assert ed High out put ( I nt ernal 1 = Ext ernal 1)

Bit hreshold input ( I nput wit h hyst eresis)

Open- collect or or open- drain out put

Posit ive edge cont rol input signal

Negat ive edge cont rol input signal

3- St at e out put

Post poned out put ( pulse t riggered flip- flop)

Enable input , when at it s int ernal 1- st at e, all out put s are enabled.
When at it s int ernal 0- st at e all out put s are at t he int ernal 0- st at e

Dat a input t o a st orage element

Shift right ( left ) input s m= 1, 2, 3, et c.

Count ing up ( down) input s m= 1, 2, 3, et c.

Binary Grouping. m is t he highest power of 2.

Cont ent equals ( e. g. , 9)

I nt ernal connect ion

I nt ernal connect ion wit h negat ion

I nt ernal input ( virt ual input )

I nt ernal out put ( virt ual out put )

I nt ernal dynamic connect ion
When t he logic circuit has one or more input s t hat are common t o more t han one element
of t he circuit , t he symbol is modified t o include a common cont rol block. The dist inct ive
EN
m m
m m + -
0
m
}
CT=9
D
shaped cont rol block adopt ed by I EC is shown in t he figure 2. Unless ot herwise qualified
specifically wit hin t he cont ext of Dependency Not at ion t he input s t o t he cont rol block are
assumed t o be common t o all t he element s wit hin t he circuit .
A
B
C
D
A
B
C
D

FI G 2: Symbol for common cont rol block
I f an out put is dependent on all t he element s of t he cir cuit it is shown as a common
out put , and t he common out put element is dist inct ly shown by being separat ed from t he
ot her element s by a double line as shown in t he figure 3. I t may be not ed t hat in drawing
t he symbols it is not permit t ed t o represent t he signals ent ering or leaving from t he t op or
bot t om sect ion of t he logic symbol.

FI G 3: Symbol for common out put block
Medium Scale I nt egrat ed ( MSI ) circuit s available from many vendors are designed t o
perform well defined combinat ional or sequent ial funct ions. The commonly available MSI s
include combinat ional circuit s like mult iplexers, demult iplexers, encoders, arit hmet ic unit s
and comparat ors, and sequent ial circuit s like regist ers, count ers and display cont rollers.
The aim of t he Dependency Not at ion is t o give a det ailed descript ion of t he funct ion of
each input / out put and t he int errelat ionship bet ween signals of t he I C wit hin t he symbol
it self, using simple codes. Such a not at ion will great ly help in designing wit h MSI s wit hout
const ant dependence on t he dat a sheet s. While t he dependency not at ion can be used t o
compose symbols for circuit s t hat are composed of a few SSI s and MSI s, it is not always
possible t o creat e a symbol for every circuit . For example it is not feasible t o compose a

symbol for an LSI chip like a microprocessor, using t he dependency not at ion.
Dependency not at ion is a means of denot ing t he relat ionships, bet ween input s, out put s or
input s and out put s, wit hout act ually showing all t he element s and int erconnect ions
involved. I t should not be used t o replace t he symbols for combinat ional element s. I t
gives infor mat ion t hat supplement s t hat provided by t he qualifying symbols for an
element ' s funct ion. The signals are classified as ` affect ing' and ` affect ed' . An input as well
as an out put signal can be an affect ing signal or affect ed signal. There are t en t ypes of
dependencies ident ified under t his St andard. These are explained in t he following.
AND Dependency ( G Dependency) : A common relat ionship bet ween t wo signals is t o
have t hem ANDed t oget her. This AND relat ionship in Dependency not at ion is shown as
indicat ed in t he figure 4. The input B is ANDed wit h input A and t he complement of B is
ANDed wit h C. t he let t er G has been chosen t o indicat e AND relat ionships and is placed at
input B, inside t he symbol. An arbit rary number ( 1 has been used here) is placed aft er t he
let t er G and also at each affect ed input . Not e t he superscript slash aft er 1 at input C.

FI G. 4: G dependency bet ween input s
I n figure 5 out put B affect s input A wit h an AND relat ionship. The lower example shows
t hat it is t he int ernal logic st at e of B, unaffect ed by t he negat ion sign t hat is ANDed.

FI G. 5: G dependency bet ween out put s and input s

Figure 6 shows A t o be ANDed wit h a dynamic input B.

FI G. 6: G dependency wit h a dynamic input
The rules for G- dependency can be summarised as:
When a Gm input or out put ( m is a number) st ands at it s int ernal 1- st at e ( Assert ed) all
t he input s and out put s affect ed by t his Gm st and at t heir normally defined int ernal logic
st at es.
When Gm input or Gm out put st ands at it s int ernal 0- st at e ( Not Assert ed) all t he input s
and out put s affect ed by it st and at t heir 0- st at e ( Not Assert ed) .
Convent ions for t he Applicat ion of Dependency Not at ion in General: The rules for applying
dependency relat ionships in general follow t he same pat t ern as was illust rat ed for G-
dependency. Applicat ion of dependency not at ion is accomplished by:
Labelling t he input ( or out put ) affect ing ot her input s or out put s wit h a let t er symbol
indicat ing t he relat ionship involved followed by an ident ifying number, arbit rar ily chosen.
Labelling each input or out put affect ed by t hat affect ing input ( or out put ) wit h t hat same
number.
I f it is t he complement of t he int ernal logic st at e of t he affect ing input or out put t hat does
t he affect ing, t hen a bar is placed over t he ident ifying numbers at t he affect ed input s or
out put s. I f t he affect ed input or out put requires a label t o denot e it s funct ion t his label will
be prefixed by t he ident ifying number of affect ing input . I f an input or out put is affect ed
by more t han one affect ing input , t he ident ifying numbers of each of t he affect ing input s
will appear in t he label of t he affect ed one, separat ed by commas. The left - t o- r ight
sequence of t hese numbers is t he same as t he sequence of t he affect ing relat ionships.
I f t he labels denot ing t he funct ions of affect ed input s or out put s must be numbers, t he
ident ifying numbers t o be associat ed wit h bot h affect ing input s and affect ed input s or
out put s will be replaced by anot her charact er select ed t o avoid ambiguit y
OR Dependency ( V Dependency) : The symbol denot ing OR dependency is t he let t er V.
Each input or out put affect ed by a Vm input or Vm out put st ands in an OR relat ionship
wit h t his Vm input or out put . When Vm input or out put st ands at it s int ernal 1- st at e
( Assert ed) all input s an out put s affect ed by t his Vm input or Vm out put st and at t heir
int ernal 1- st at e ( Assert ed) . When a Vm input or Vm out put st ands at it s int ernal 0- st at e
( Not Assert ed) , all input s and out put s affect ed by t his Vm input or Vm out put st and at
1
G1 A
A
B
B
&

t heir normally defined int ernal logic st at es. The nat ure of V dependency is illust rat ed in
t he figure 7.
Negat e Dependency ( N Dependency) : The symbol denot ing negat e dependency is t he
let t er N. Each input or out put affect ed by an Nm input or Nm out put st ands in an Exclusive
OR relat ionship wit h t his Nm input or Nm out put . When Nm input or Nm out put st ands at
it s int ernal 1- st at e ( Assert ed) , t he int ernal logic st at e of each input and each out put
affect ed by t his Nm input or Nm out put is t he complement of t he normally defined int ernal
logic st at e of t he input or out put . When Nm input or Nm out put st ands at it s int ernal 0-
st at e, all input s and out put s affect ed by t his Nm input or Nm out put st and at t heir
normally defined int ernal logic st at es. This relat ionship is illust rat ed in t he figure 8.

FI G. 7: V ( OR) dependency

FI G 8: I llust rat ion of N dependency
I nt er connect i on Dependency ( Z Dependency) : The symbol denot ing int erconnect ion
dependency is t he let t er Z. I nt erconnect ion dependency is used t o indicat e t he exist ence
of int ernal logic connect ions bet ween input s, out put s, int ernal input s, and int ernal out put s,
in any combinat ion. When a Zm input or Zm out put st ands at it s int ernal 1- st at e
( Assert ed) , all input s and out put s affect ed by t his Zm input or Zm out put st and at t heir
int ernal 1- st at es ( Assert ed) , unless modified by addit ional dependency not at ion. When a
Zm input or Zm out put st ands at it s int ernal 0- st at e Not Assert ed, all input s and out put s
affect ed by t his Zm input or Zm out put st and at t heir int ernal 0 st at es ( Not Assert ed) ,
unless modified by addit ional dependency not at ion. The nat ure of Z dependency is
illust rat ed in t he figure 9.
Cont r ol Dependency ( C Dependency) : The symbol denot ing cont rol dependency is t he
let t er C. Cont rol dependency should only be used for sequent ial element s. I t implies more
t han a simple AND relat ionship. I t ident ifies an input t hat produces act ion, for example,
t he edge- t riggered clock of a bist able circuit or t he level- operat ed dat a enable of a
t ransparent lat ch. When a Cm input or Cm out put st ands at it s int ernal 1- st at e
( Assert ed) , t he input s affect ed by t his Cm input or Cm out put have t heir normally defined
effect on t he funct ion of t he element . When a Cm input or Cm out put st ands at it s int ernal
0- st at e ( Not assert ed) , t he input s affect ed by Cm are disabled and have no effect on t he
funct ion of t he element . This dependency is explained t hrough examples in t he figure 10.

FI G. 9: I llust rat ion of Z dependency

FI G. 10: I llust rat ion of Cont rol dependency
S ( Set ) and R ( Reset ) Dependenci es: The symbol denot ing t he set dependency is S
and t he symbol denot ing t he reset dependency is R. Set and reset dependencies are used
if it is necessary t o specify t he effect of t he combinat ion R = S = 1 on a bist able element .
These dependencies should not be used if such specificat ion is not necessary. When a Sm
input st ands at it s int ernal 1- st at e ( Assert ed) t he out put s affect ed by t his Sm input will
t ake on t he int ernal logic st at es t hey normally would t ake on for t he combinat ion S = 1, R
= 0, regardless of t he st at e of any R input . When an Sm input st ands at it s int ernal 0-
st at e ( Not assert ed) it has no effect .
When an Rm input st ands at it s int ernal 1- st at e ( Assert ed) t he out put s affect ed by t his
Rm input will t ake on t he int ernal logic st at es t hey normally would t ake on for t he
combinat ion S = 0, R = 1 regardless of t he st at e of t he S input . When an Rm input st ands
at it s int ernal 0- st at e it has no effect . The R and S dependencies are illust rat ed in t he
figure 11.
a b c d
0 0 No change
0 1 0 1
1 0 1 0
1 1 Not specified

a b c d
0 0 No change
0 1 0 1
1 0 1 0
1 1 1 0

a b c d
0 1 No change

0 1 0 1

1 0 1 0
1 1 0 1

a b c d
0 1 No change
0 1 0 1
1 0 1 0
1 1 1 1

a b c d
0 1 No change
0 1 0 1
1 0 1 0
1 1 0 0

FI G 11: I llust rat ion of R and S dependencies
Enabl e Dependency ( EN Dependency) : The symbol denot ing enable dependency is EN.
Enable dependency is used t o indicat e an Enable input t hat does not necessarily affect all
out put s of an element . I t can also be used when one or more input s of an element are
affect ed. When t his input st ands at it s int ernal 1- st at e ( Assert ed) , all t he affect ed input s
and out put s st and at t heir normally defined int ernal logic st at es and have t heir normally
defined effect on element s or dist ribut ed funct ions t hat may be connect ed t o t he out put s,
provided no ot her input s or out put s have an overriding and cont radict ing effect . When t his
input st ands at it s int ernal 0 st at e ( Not Assert ed) , all t he affect ed open- circuit out put s
st and at t heir ext ernal high- impedance st at es, all 3- st at e out put s st and at t heir normally
defined int ernal logic st at es and at t heir ext ernal high- impedance st at es, and ot her t ypes
of out put s st and at t heir int ernal 0- st at es. The nat ure of EN dependency is illust rat ed in
t he figure 12.

1
EN1
EN
A
D
1
B
C

I f A = 0, B disabled and D = C I f A = 1, C disabled and D = B
FI G 12: I llust rat ion of t he EN dependency
Mode Dependency ( M Dependency ) : The symbol denot ing mode dependency is t he
let t er M. Mode dependency is used t o indicat e t hat t he effect s of part icular input s and

out put s of an element depend on t he mode in which t he element is operat ing. When an
Mm input or Mm out put st ands at it s int ernal 1- st at e ( Assert ed) , t he input s affect ed by
t his Mm input or Mm out put have t heir normally defined effect on t he funct ion of t he
element and t he out put s affect ed by t his Mm input or Mm out put st and at t heir normally
defined int ernal logic st at es, t hat is, t he input s and out put s are enabled. When an Mm
input or Mm out put st ands at it s int ernal 0- st at e, t he input s affect ed by t his Mm input or
Mm out put have no effect on t he funct ion of t he element and at each out put affect ed by
t his Mm input or Mm out put , any set of labels cont aining t he ident ifying number of t hat
Mm input or out put has no effect and is t o be ignored. When an affect ed input has several
set s of labels separat ed by slashes, any set in which t he ident ifying number of Mm input
or Mm out put appears has no effect and is t o be ignored. This represent s disabling of
some of t he funct ions of a mult ifunct ion input . When an out put has several different set s
of labels separat ed by slashes, only t hose set s in which t he ident ifying number of t his Mm
input or Mm out put appears are t o be ignored. This represent s disabling or select ion of
some of t he funct ion of a mult ifunct ion out put , or t he modificat ion of some of t he
charact erist ics or dependent relat ionships of t he out put . These concept s are illust rat ed in
t he figure 13.
The circuit in t he figure 13 has t wo input s, B and C, t hat cont rol which one of four modes
( 0, 1, 2, or 3) will exist at any t ime. I nput s D, E and F are D- input s subj ect t o dynamic
cont rol ( clocking) by t he A input . The numbers 1 and 2 ar e in t he series chosen t o indicat e
t he modes of input s E and F are only enabled in mode 1 ( parallel loading) and input D is
only enabled in mode 2 ( for serial loading) . Not e t hat input A has t hree funct ions. I t is t he
clock for ent ering dat a. I n mode 2, it causes right shift ing of dat a, which means a shift
away from t he cont rol block. I n mode 3, it causes t he cont ent s of t he regist er t o be
increment ed by one count .
M Dependency affect ing Out put s : When an Mm input or Mm out put st ands at it s int ernal
1 st at e, t he affect ed out put s st and at t heir normally defined int ernal logic st at es, t hat is,
t he out put s are enabled.

C4/2->/3+
0
1
}
M--
0
3
2,4D
1,4D
1,4D
A
B
C
D
E
F

FI G. 13: I llust rat ion of M dependency.
When an Mm input or Mm out put st ands at it s int ernal 0 st at e, at each affect ed out put any
set of labels cont aining t he ident ifying number of t hat Mm input or Mm out put has no
effect and is t o be ignored. When an out put has several different set s of labels separat ed
by slashes ( e. g. , C4/ - > / 3+ ) , only t hose set s in which t he ident ifying number of t his Mm
input of Mm out put appears are t o be ignored. I n t he figure 5. 14, mode 1 exist s when t he
A input st ands at it s int ernal 1 st at e. The delayed out put symbol is effect ive only in mode
1 ( when input A = 1) in which case t he device funct ions as a pulse- t riggered flop- flop
( Mast er- Slave flip- flop) . When t he input A = 0, t he device is not in mode 1 so t he delayed
out put symbol has no effect and t he device funct ions as a t ransparent lat ch.
1
M1
C2
2D
A
B
C
D

FI G. 14: Type of flip- flop det ermined by mode
I f in figure 15, if t he input A st ands at it s int ernal 1 st at e est ablishing mode 1, out put B
will st and at it s int ernal 1 st at e when t he cont ent of t he regist er equals 9. Since t he
out put B is locat ed in t he common- cont rol block wit h no defined funct ion out side of mode
1, t his out put will st and at it s int ernal 0 st at e when input a st ands at it s int ernal 0 st at e,
regardless of t he regist er cont ent .
M1 A
B
1CT=9

FI G. 15: Disabling an out put of t he common- cont rol block
Addr ess Dependency ( A Dependency) : The symbol denot ing address dependency is
t he let t er A. Address dependency provides a clear represent at ion of t hose element s,
part icularly memories t hat use address cont rol input s t o select specified sect ions of a
mult idimensional array. Address dependency allows a symbolic represent at ion of only a
single general case of t he sect ions of t he array, rat her t han requir ing a symbolic
represent at ion of t he ent ire array. When t his input st ands at it s int ernal 1- st at e
( ASSERTED) , t he input s affect ed by t his input ( t hat is, t he input s of t he sect ion of t he
array select ed by t his input ) have t heir normally defined effect on t he element s of t he
select ed sect ion. Also, t he int ernal logic st at es of t he out put s affect ed by t his input ( t hat
is, t he out put s of t he select ed sect ion) have t heir normal effect on t he OR funct ion ( or t he
indicat ed funct ions) det ermining t he int ernal logic st at es of t he out put s of t he array.

When t he input st ands at it s int ernal 0- st at e ( Not assert ed) , t he input s affect ed by t his
input ( t hat is, t he input s of t he sect ion select ed by t his input ) have no effect on t he
element s of t his sect ion. Also, t he out put s affect ed by t his input ( t hat is, t he out put s of
t he sect ion select ed by t his input ) have no effect on t he out put s of t he array. An affect ing
address input is labelled wit h t he let t er A followed by an ident ifying number t hat
corresponds t o t he address of t he part icular sect ion of t he array select ed by t his input .
The nat ure of address dependency is illust rat ed in t he figure 16.
A
B
C
D
A1
A2
A3
C4
A
B
C
D
A1
A2
A3
C4
A,4D E
G
F
H
1,4D
2.4D
3,4D
1,4D
2,4D
3,4D
E
G
F
H
> 1
> 1

FI G 16: I llust rat ion of address dependency.

Symbols based on t he Dependency Not at ion, of some of t he commonly encount ered
int egrat ed circuit s are given in t he figure 17. The reader is advised t o underst and and
int erpret t he funct ion and operat ion of t hese int egrat ed circuit s using t he dependency
not at ion.
0
1
2
E N
0
1
3
4
5
6
7
2
G
0
7
_
DMUX
&
X3
X2
H
138
0
G
_
3
MUX
0
1
0
1
2
3
S0
S1
DI0
DI1
DI2
DI3
Y
'164
R
C1/1
& 1D
R
C1/
195A
M1
1, 2 J
1, 2 K
1', 2 D
1', 2 D

FI G. 17: Symbols of some common int egrat ed circuit s.

DRAWI NG DI GI TAL CI RCUI T DI AGRAMS
The gat e shown in t he figure 18( a) is not commercially available. However, a minor
modificat ion will est ablish t his correspondence. This is shown in t he figure 18( b) . Each one
of t he gat es shown will correspond t o t he gat es t hat are commercially available.

FI G. 18: Redrawing of a logic symbol t o correspond t o t he act ual gat es used.

Document at ion is an import ant aspect of any design exercise. Any such document at ion
must be consist ent , use st andard symbols and follow unambiguous procedures. Many
variet ies of document s need t o be prepared t o describe a given digit al syst em
exhaust ively. I t is necessary for any organisat ion concerned wit h t he design and
development and/ or manufact ur ing and market ing of digit al syst ems t o evolve and
implement a document at ion st andard for effect ive communicat ion bet ween individuals
concerned wit h various aspect s of t he product . The basic rules t o be followed in drawing
t he digit al circuit diagrams will be present ed in t he following.
The basic r ules are:

All signals flow from left t o right . I n case of any deviat ion from t his convent ion t he
direct ion must be indicat ed by an arrow. Such a need may arise when t here is
requirement t o feed t he out put of a circuit module t o t he input of circuit module
which is ot herwise upst ream from t he signal flow point of view.
Ext ernal input s should ent er t he left hand side of t he diagram. Out put s from t he
circuit should be shown in t he right hand side.
Use polarised mnemonic not at ion and all t he st andard symbols t hereof.
Use dependency not at ion t o represent any MSI and LSI circuit s.
All signals should have properly defined mnemonics wit h t heir assert ion levels
indicat ed.
All gat es represent ed in t he circuit diagr am must correspond t o t he act ual
hardware element s used. But t he choice of operat or symbol ( NAND, NOR, OR,
EXOR ETC. ) for gat es must be indicat ive of t he funct ion t hey perform.
Each operat or symbol should be given a number t o correspond wit h t he act ual I C
used. These are designat ed as U1, U2 et c. A part icular number, say U2, may be
given t o more t han one logic operat or as an I C may have more t han one funct ional
element .
The pin numbers corresponding t o t he specific I C used should be shown near t he
input s or t he out put s of t he logic operat or, or out side t he symbol out line in t he
case of MSI s and LSI s.
The specific I Cs used along wit h t heir pin numbers for V
CC
and GND ( V
BB
) should be
shown at a convenient place on t he circuit diagram.
I f t he circuit diagram is large and is t o be drawn on a large sheet , zonal co-
ordinat es should be incorporat ed.
I f a discont inuit y is t o be int roduced in a signal line, it s dest inat ion or source, if
needed in t erms of zonal coordinat es, should be indicat ed at t he discont inuit y.
Consider t he circuit diagram shown in t he figure19. I t is redrawn as per t he rules st at ed
above and shown in t he figure 20.

FI G. 19: Example of a combinat ion circuit

FI G. 20: Cir cuit diagram of figure 20 redrawn as per t he rules of document at ion st andard

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