GUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)

Seshadri Rao Knowledge Village, Gudlavalleru – 521 356.

Department of Electronics and Communication Engineering

HANDOUT

On

DIGITAL CIRCUITS DESIGN

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Vision
To be a pioneer in electrical and electronics engineering education and research, preparing
students for higher levels of intellectual attainment, and making significant contributions to
profession and society

Mission
 To impart quality education in electrical and electronics engineering in dynamic learning
environment and strive continuously for the interest of stake holders, industry and society.
 To create an environment conducive to student-centered learning and collaborative research.
 To provide students with knowledge, technical skills, and values to excel as engineers and
leaders in their profession.

Program Educational Objectives

PEO1: Graduates will have technical knowledge, skills and competence to identify,
comprehend and solve problems of industry and society.
PEO2: Graduates learn and adapt themselves to the constantly evolving technology to
pursue higher studies and undertake research.
PEO3: Graduates will engage in lifelong learning and work successfully in teams with
professional, ethical and administrative acumen to handle critical situations.
Programme Specific Outcomes(PSO)

1. Apply the knowledge of circuit design, analog & digital electronics to the field of

electrical and electronics systems

2. Analyze, design and develop control systems, industrial drives and power systems

using modern tools.

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 HANDOUT ON DIGITAL CIRCUITS
Class & Sem. : II B.Tech – II Semester Year : 2019-20
Branch : EEE Credits : 3
Name of the staff: B. Mahesh Babu/ V.Prathab Babu/ Ch.Trinayani
======================================================================
1. Brief History and Scope of the Subject
Digital circuits are circuits that handle digital signals – discrete bands of analog levels –
rather than by continuous ranges (as used in analogue electronics). All levels within a
band of values represent the same numeric value and are represented by two voltage
bands: one near a reference value (typically termed as "ground" or zero volts), and the
other a value near the supply voltage. These correspond to the "false" ("0") and "true"
("1") values of the Boolean domain respectively, named after its inventor, George Boole,
yielding binary code. Digital electronic circuits are used to implement complex logic
blocks such as ALU, UART, Bus Interfaces, and Memories etc.
2. Pre-Requisites
 Mathematics
3. Course Objectives:
 To familiarize with the concepts of different number systems and Boolean algebra
 To introduce the design techniques of combinational, sequential logic circuits.
 To give a model of combinational and sequential circuits using HDLs.

4. Syllabus : Digital Circuit Design

UNIT - I: Boolean Algebra and Logic gates
Number Systems - Binary numbers, Octal, Hexadecimal, Other Binary Codes;
Complements, Signed binary numbers, Digital logic operations and gates, Basic
theorems and Properties of Boolean Algebra, Boolean functions, Canonical and
Standard Forms, Complements of Boolean functions, Two-level NAND and NOR,
Implementation of Boolean functions.
UNIT - II: Combinational Logic Circuits
The Map Method (upto Four Variables), Don’t care conditions, Design Procedure,
Adders, Subtractors, 4-bit Binary Adder/ Subtractor circuit, BCD adder,
carrylook-a-head adder, Decoders and Encoders, Multiplexers, Demultiplexers.
UNIT - III: Sequential Logic Circuits
Design Procedure, Flip-Flops, truth tables and excitation tables, Conversion of
flip-flops, Design of Counters, Ripple Counters, Synchronous Counters, Ring
Counter, Johnson Counter, Registers, shift registers, universal shift register.
UNIT - IV: Finite State Machines
Types of FSM, Capabilities and limitations of FSM, State assignment, Realization
of FSM using flip-flops, Mealy to Moore conversion and vice-versa, Reduction of
state tables using Partition technique.
UNIT - V: Programmable Logic Devices & HDL

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 Types of PLD’s: PROM, PAL, PLA, Basic structure of CPLD and FPGA,
Advantages of FPGA’s. Introduction to Verilog - Structural Specification of Logic
Circuits, Behavioral Specification of Logic Circuits, Hierarchical Verilog Code.
UNIT - VI: Digital Design Using HDLs
Verilog for combinational circuits - conditional operator, if-else statement, case
statement, for loop; using storage elements with cad tools-using verilog constructs
for storage elements, blocking and non-blocking assignments, non-blocking
assignments for combinational circuits, flip-flop with clear capability, using
verilog constructs for registers and counters.

5. Lecture Schedule / Lesson Plan

No. of Periods
Topic
Theory Tutorial
UNIT –1: Boolean Algebra and Logic gates
Number Systems - Binary numbers, Octal, Hexadecimal 1
Other Binary Codes; Complements, Signed binary 1
numbers 1
Digital logic operations and gates, Two-level NAND and 1
NOR
Basic theorems and Properties of Boolean Algebra 1
Boolean functions, Canonical and Standard Forms, 1
1
Complements of Boolean functions,
Implementation of Boolean functions. 2
UNIT – 2: Combinational Logic Circuits
The Map Method (upto Four Variables) 2
Don’t care conditions, Design Procedure 1
4-bit Binary Adder Adders, Subtractors, 1 1
BCD adder, carry look-a-head adder, / Subtractor circuit, 2
Decoders and Encoders, 1
Multiplexers, 2
1
Demultiplexers. 2
UNIT – 3: Sequential Logic Circuits
Design Procedure, Flip-Flops 1
Truth tables and excitation tables, Conversion of flip-flops, 1 1
Design of Counters, Ripple Counters, 1
Ring Counter, Synchronous Counters, 4
Shift registers, Johnson Counter, 1 2
Universal shift register. 1
UNIT – 4: Finite State Machines
Types of FSM, Capabilities and limitations of FSM 1
1
State assignment, Realization of FSM using flip-flops, 2
Mealy to Moore conversion 1
Moore to Mealy conversion 4

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 Reduction of state tables using Partition technique.
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1
UNIT – 5: Programmable Logic Devices & HDL
Types of PLD’s: PROM, PAL, PLA 2
Basic structure of CPLD 1 1
Basic structure of FPGA, Advantages of FPGA’s. 1
Introduction to Verilog - Structural Specification of Logic
1
Circuits,
1
Specification of Logic Circuits, 2
Behavioral Hierarchical Verilog Code. 1
UNIT – 6: Digital Design Using HDLs
Verilog for combinational circuits - conditional operator 1
if-else statement, case statement, for loop; 2
1
using storage elements with cad tools 1
using verilog constructs for storage elements 1
blocking and non-blocking assignments 2
non-blocking assignments for combinational circuits 1
2
flip-flop with clear capability 1
using verilog constructs for registers and counters 1
Total No. of Periods: 56 14
6. Course Outcomes:
Upon successful completion of the course, the students will be able to
 Design various logic circuits using Boolean laws.
 Design combinational and sequential logic circuits.
 Gain the knowledge of PLDs.
 Develop digital circuits using HDL Course Content.
7. Program Outcomes:
Graduates of the Electrical and Electronics Engineering Program will have ability to
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals and an engineering specialization for the solution of complex
engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs with
appropriate consideration for public health and safety, and cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of t h e information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
Modern engineering and IT tools, including prediction and modeling to complex
engineering activities, with an understanding of the limitations.

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 6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal, and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with
the engineering community and with the society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognizes the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.
8. Mapping of Course Outcomes with Program Outcomes:
 PO  PO  PO  PO  PO  PO  PO  PO  PO  PO11   PO1  PO1  PSO  PSO
1 2 3 4  5 6 7 8  9 0 1 2  1 2
CO
1 3 3 3 3 3     2 2 2   2 3  
CO
2 3 3 3 3 2     2 2 2   2 3  
CO
3 3 3           2 2 2   2 2  
CO
4 3 3 3 3 2     2 2 2   2 3  
9. Prescribed Text Books
1.M. Morris Mano, “Digital Design”, 3rd Edition, PHI. (Unit I to IV).
2.Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic withVerilog
Design”, 3rd Edition, McGrawHill (Unit V, VI)
10. Reference Books:
1. Charles H. Roth, Jr, “Fundamentals of Logic Design”, 4th Edition, Jaico Publishers.
2. Zvi Kohavi and Niraj K.Jha, “Switching and Finite Automata Theory, 3rd Edition,
Cambridge University Press, 2010.
3.Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”,
2ndEdition, Prentice Hall PTR.
4.D.P.Leach, A.P.Malvino, “Digital Principles and Applications”, TMH, 7th Edition.
11. URLs and Other E-Learning Resources
 http://www.electronics-tutorials.ws/logic/logic_1.html
 http://nptel.iitm.ac.in/video.php?courseId=1005

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  http://nptel.iitm.ac.in/courses/Webcourse-contents/IIT-
%20Guwahati/digital_circuit/frame/index.html
 http://www.scribd.com/doc/16066166/Logic-Gates-Experiment-1
 http://richardbowles.tripod.com/dig_elec/chapter1/chapter1.htm
 http://www.piclist.com/images/ca/ualberta/phys/www/http/~gingrich/phys395/notes/n
ode129.html
 http://www.doc.ic.ac.uk/~ih/teaching/lectures/comparch/logic/adder/
 http://msbte.com/docs/labmanual/Diploma%20in%20Engineering/Third
%20Semester/Principales%20of%20Digital%20Techniques%20(9040)
 http://www.scribd.com/doc/18737197/Full-Adder-Experiment-5
 http://www.gyte.edu.tr/dosya/102/dersler/elm321/Lab1.pdf
 http://www.ece.rice.edu/~kmram/elec326/Notes/notes-326-set8.pdf
 http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol1/cwl3/article1.html
 http://verticalhorizons.in/shift-registers-in-digital-electronics/
12. Digital Learning Materials:

 Digital Design-Morris Mano.pdf

 Digital Design-Mano solutions/
 Digital Electronics Prof. Gautam Saha's notes/
 Digital Electronics Tutorial - 1.ppt
 Digital Electronics Tutorial - 2.ppt
 Digital logic Design - Morris Mano/
 Logic design-Roth.pdf
 Switching Theory and Logic Design-Singh,AK.pdf
13. Seminar Topics
 LCD and LED Displays.
 Semiconductor memories.
 Digital Keyboard

14. Tutorials:
Tutorial classes will be conducted to clear the doubts, to solve previous question papers,
to solve some additional problems and to take special care of weak students.

UNIT-1
Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students

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 I) Objective Questions
1) The _____ or ________ of a number system indicates the number of
unique symbols used in that system.
2) The highest decimal number that can be represented with 10 binary digits is
(A) 512 (B) 1023 (C) 1024 (D) 211-1
3) Let (A2C) 16 = (X) 8. Then X is
(A) 7054 (B) 6054 (C) 5154 (D) 5054
4) The eight bit 2’s complement form of (-23)10 is _____.
5) 4-bit 2’s complement representation of a decimal number is 1000. The number is
(A) +8 (B) 0 (C) -7 (D) -8
6) The 2’s complement representation of -17 is
(A) 101110 (B) 101111 (C) 111110 (D) 110001
 7) How many bits are in an ASCII character?
(A) 16 (B) 8 (C) 7 (D) 14
8) A binary number's value changes most drastically when the ________ is changed.
9) Decimal 11 in BCD is ________.
(A) 00001011 (B) 00001100 (C) 00010001 (D) 00010010
10) The two types of parity are ________ and ________.
11) For a code to be an error detecting code, the minimum hamming distance between two
code words must be ________.
12) The parity of the binary number 11011001 is
(A) Even (B) odd (C) same as the number of zeros (D) none
13) Every logical operation in a Boolean expression represents a ----------
2) A+AB+ABC+ABCD+ABCDE+---- =
(A) 1 (B) A (C) A+AB (D) AB
14) Boolean expression for the output of XNOR logic gate with inputs A and B is
        (A). AB’ + A’B  (B) (AB)’ + AB (C).(A’ + B)(A + B’) (D) (A’ + B’)(A + B)
15) The number of cells in a 6- variable K-map is ----
(A) 6 (B) 12 (C) 36 (D) 64
16) The bunch of 1’s on the K-map which from a 2-square, 4-square. Etc. is called a -
17) The number of adjacent cells each cell in an n variable K-map can have is
(A) n-1 (B) n (C) n+1 (D) 2n
18) The NAND-NAND realization is equivalent to
(A) AND –NOT realization (B) AND – OR realization
(C) OR - AND realization (D) NOT – OR realization
19) If and only if all of the inputs are on, the output will be off. This is called ---------
(A) NAND (B) NOR (C) X-OR (D) OR
20) Match the following
1) DeMorgan’s law A) A (A + B) = A
2) Distributive law B) A+1=1
3) Identity law C) (A+B)’=A’.B’
4) Redundancy Law D) A + (B C) = (A + B). (A + C)

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10) The Boolean expression A+BC in reduced form is
(A) AB+BC (B) (A+B)(A+C) (C) (A+C)B (D) AB
11) Which of the following expressions is in the sum-of-products (POS) form?
(A) (X + Y).(Z + W) (B) X+Y+ZW (C) XY+ZW (D) XY + Z+W

12) Derive the Boolean expression for the logic circuit shown below

A. C(A+B)DE B. [C(A+B)D+E’] C.[C(A+B)D]E’ D. ABCDE

II) Descriptive Questions

1) Explain the classification of different number systems.
2) Describe the conversion of decimal number to hexadecimal number with an example.
3) Convert the following decimal numbers to octal numbers
(a) 4796 (b) 8957.75
4) Explain the process of decimal number subtraction using 9’s complement and 10’s
complement with an example.
5) Discuss by an example, the operation of binary number subtraction using the method of
1’s and 2’s complement.
6) Describe how signed number is represented in two's complement form.
7) Write the equivalent (743)10 in BCD, 2421 and 6421 codes.
8) What are the different types of non weighted codes and explain them with examples.
9) Write notes on error correcting codes
10) What is hamming code? How is the hamming code word tested and corrected?

B1. Question testing the ability of students in applying the concepts.

I) Objective Questions
1) The (128)10 = (1003) b, the possible base b is
(A) 3 (B) 4 (C) 5 (D) 6
2) Decimal 43 in Hexadecimal and BCD number system is respectively
(A) B2, 0100 011 (B) 2B, 0100 0011 (C) 2B, 0011 0100 (D) B2, 0100 0100
3) An equivalent 2’s complement representation of the 2’s complement number 1101 is
(A) 110100 (B) 01101 (C) 110111 (D) 111101
4) 11001, 1001, 111001 correspond to the 2’s complement representation of which one of
the following sets of number
(A) 25, 9, and 57 (B) -6, -6, and -6 (C) -7, -7 and -7 (D) -25, -9 and -57
5) Consider the signed binary number A = 01000110 and B = 11010011, where B is
in 2’s complement and MSB is the sign bit. In list-I operation is given and is List-II
resultant binary number is given in the table below:

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 The correct match of P Q R S is
(A) 5 7 4 2 (B) 6 3 1 2 (C) 6 7 1 3 (D) 5 3 4 2
6) The range of signed decimal numbers that can be represented by 6-bit 1’s complement
number is
(A) -31 to +31 (B) -63 to +63 (C) -64 to +63 (D) -32 to +31
7) Which of the following is an invalid BCD code?
(A) 0011 (B) 1101 (C) 0101 (D) 1001
8) Convert the 127decimal number to BCD.
(A) 011100100001 (B) 111010001 (C) 001010111 (D) 000100100111
9) The binary-coded decimal (BCD) system can be used to represent each of the 10 decimal
digits as an:
(A) 4-bit binary code (B) 8-bit binary code (C) 16-bit binary code (D) ASCII code
10) For 2-bit error detecting, the minimum hamming distance must be
(A) 1 (B) 2 (C) 3 (D) 4
11) The number of parity bits in a 12-bit hamming code is
(A) 4 (B) 5 (C) 6 (D) 8
II) Descriptive Questions
1) Convert the following numbers with the given radix to decimal.
i) (334)5 ii) (12345)7 iii) (768)9
2) Solve
i) (AD012)16 = (X)5 ii) (5.204)10 = (X)3
3) Perform the following
a) (137.64)10 = ( )6 = ( )2
b) (1111.1011)2= ( )8=( )16
4) Subtract (0001.1110)2 from (0011.1001)2 using 2’s complement method.
5) If A = -57 and B = +38, then represent A and B in 8-bit 2’s complement.
Find (i) A + B (ii) A - B using 2’s complement method.
6) Perform the following operations using r-1’s complement arithmetic:
i) (+43)10 − (−53)10. ii) (+346.56)10 − (+456.78)10.
7) Convert (1101) binary code to gray code with detailed steps?
8) Perform the addition of the following XS-3 codes
(i) 109 + 778 (ii) 204.6 + 185.56
9) Represent the unsigned decimal numbers 351 and 986 in BCD, and then show the steps
necessary to form their sum.
10) Generate the Hamming code for the given 11 bit message 10001110101.
11) Detect and correct errors if any in the Hamming codes and write the correct code
(i) 1100110 (ii) 0011101
12)State and prove Demorgan’s theorem.

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 13) Show that both NAND gate and NOR gate are universal gates.
14) Draw the logic circuits for the realization of basic operations using only NOR
gates.
15) Simplify the following three variable Boolean expression using karnaugh map
method.
Y= ABC’ +A’B’C’+ABC+AB’C’.
16) Using K-Map simplify the following Boolean function
F=A’BC+ABC’+ABC+AB’C’
17) What is a code converter? Explain the principle of binary to gray and gray to
binary.
18) Explain the process of minimization of Boolean function using tabular method.
19) Describe the procedure of reducing Boolean expression with don’t cares using
tabular method
B2. Question testing the ability of students in applying the concepts.
I) Objective Questions
1. For the circuit shown below, the output F is given by

(A) 1 (B) 0 (C) x (D) x’

2. Minimum number of 2 input NAND gates required to implement the function given
below is F=(X’+Y’)(Z+W)
(A)3 (B) 4 (C) 5 (D) 6
3. Which output expression might indicate a product-of-sums circuit construction?
(A) X=CH’(D+E+F)
(B). X=CG(DE)
(C). X=(AC+BD+EF)’
(D) X=(C+D)(E+G)
4. If f(A,B,C,D)=1 then the K-map contains _________ number of logic 1’s is
(A) 4 (B) 8(C) 16 (D) 32
5. The K – map for a Boolean function is shown in the figure. The number of
essential prime implicants for this function is

(A) 4 (B) 5 (C) 6 (D) 7

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6.

The output Y in the circuit below is always ‘1’ when

(A) two or more of the inputs P,Q,R are ‘0’
(B) two or more of the inputs P,Q,R are ‘1’
(C) any odd number of the inputs P,Q,R is ‘0’
(D) any odd number of the inputs P,Q,R is ‘1’
7. The Boolean function Y=AB+CD is to be realized using only 2 -input NAND gates.
The minimum number of gates required is
(A) 2 (B) 3 (C) 4 (D) 5
8. A function F(A,B,C) contains minterms 1,2,3,5,6,7, its complement contains
(A) Σm (0,4) (B) Σm(1,2,3,5,6,7) (C) ПM (1,2,3,5,6,7) (D)ПM (0,4)
9. The Boolean expression for the truth table shown is

(A) (A+C)(A’+C’) (B) B(A+C’)(A’+C)

(C) B’(A+C’)(A’+C) (D) B’(A+C)(A’+C’)
10.For the logic circuit shown in the figure the required input(A,B,C) condition to make
the output(X) = 1 is

(A) (1,0,1) (B) (0,0,1) (C) (1,1,1) (D)(0,1,1)

11. For the circuit shown below the expression for output is

(A) (PR OR Q)XOR R (B) (PR AND Q)XOR R

(C) (PR NOR Q)XOR R (D) (PR XOR Q) XOR R
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II) Problems
1. Simplify the following Boolean expressions to a minimum number of literals
i) ii) ) ii)
2. Find the complement of the following Boolean expressions
i) ii)
3. Using De-Morgan’s theorem, convert the following Boolean expression to equivalent
expression that have only OR and complement operations
F=
4. Given the following Boolean expression:
F=
a) Obtain the truth table of the function
b) Draw the logic diagram using the original Boolean expression.
c) Simplify the function to a minimum number of literals using Boolean algebra.
d) Obtain the truth table of the function from the simplified expression and show that it
is the same as the one in part(a).
5. Express the following functions in sum of minterms and product of maxterms
i) F(A,B,C,D)= ii)F(x,y,z)=(xy+z)(xz+y)
6. Find the complement of the function in sum of minterms
F(A,B,C,D)=∑(0,2,6,11,13,14)
7. Draw the logic diagram of the following Boolean expressions without simplifying them:
i) ii)
8. Show that the dual of the exclusive-OR is equal to its complement
9. Simplify the following Boolean expression and implement them in
a) Two level NAND gate circuit b)Two level NOR gate circuit

10. Simplify the following Boolean expression K- maps

ii) F(A,B,C,D)=∑(4,6,7,15)
11. Simplify the following Boolean expression by first finding the essential prime implicants
using tabular method. F(W,X,Y,Z)=∑(0,2,4,5,6,7,8,10,13,15)
C. Questions testing the analyzing / evaluating ability of students
1) Assume an arbitrary number system having a radix of 5 and 0, 1, 2, L and M
as its independent digits. Determine:
i) The decimal equivalent of (2LM.L1)
ii) The octal equivalent of (21L.M2)
iii) The hexagonal equivalent of (LM1.L2)
2) Test the following hamming code sequence for 11 bit message and correct if necessary
(100, 1101, 1110, 1011)
3) Generate the weighted codes for the decimal digits using the weights
(a) 3, 3, 2, 1 (b) 4, 4, 3, -2

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 4) Represent numeric digits 0 to 9 atleast in any two self complementing codes

5) Obtain the minimal expression for Ʃm(2,3,5,7,9,11,12,13,14,15) and implement it in

NOR logic
6) Obtain the minimal expression for ПM(2,3,5,7,9,11,12,13,14,15) and implement it in
NAND logic
7) With the use of maps, find the simplest sum-of-products form of the function F = fg
where f = abc’ + c’d + a’cd’ + b’cz’ and g = (a + b + c’ + d’)(b’ + c’ + d)(a’ + c + d’)
8) Given AB’+ A’B=C, then prove that AC’+A’C=B.
D. GATE/IES Questions
1) The number of bytes required to represent the decimal number 1856357 in packed BCD
(Binary Coded Decimal) form is __________ . GATE-2014
2) The two numbers represented in signed 2’s complement form are P = 11101101 and Q =
11100110. If Q is subtracted from P, the value obtained in signed 2’s complement form is
A. 100000111 B. 00000111 C. 11111001 D. 111111001 GATE-2008
3) X = 01110 and Y = 11001 are two 5 bit binary numbers represented in 2's complement
format. The sum of X and Y represented in 2's compliment format using 6 bits is
A. 100111 B. 001000 C. 000111 D. 101001 GATE-2007
4) A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a
base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5
number 24 will be represented by its BCP code 010100. In this number system, the BCP code
100010011001 corresponds to the following number in base-5 system
A. 423 B. 1324 C. 2201 D. 4231 GATE-2006
5) Decimal 43 in Hexadecimal and BCD number system is respectively GATE-2005
A. B2, 01000011 B. 2B, 01000011
C. 2B, 00110100 D. B2, 00110100
6) 11001, 1001 and 111001 correspond to the 2's complement representation of which one of the
following sets of number? GATE-2004
A. 25, 9 and 57 respectively B. -6, -6 and -6 respectively
C. -7, -7 and -7 respectively D. -25, -9 and -57 respectively
7) The range of .signed decimal numbers that can be represented by 6 bit 1’s complement form is
A. -31 to +31 B. -63 to +64 C. -64 to +63 D. -32 to+31 GATE-2004
8) 4-bit 2's complement representation of a decimal number is 1000. The number is
A. +8 B. 0 C. -7 D. -8 GATE-2002
9) The 2’s complement representation of- 17 is GATE-2001
A. 01110 B. 101111 C.11110 D. 10001
10) An equivalent 2's complement representation of the 2’s complement number is 1101 is
A. 110100 B. 001101 C. 110111 D. 111101 GATE-1998
11) 2's complement representation of a 16 bit number (one sign bit and 15 magnitude bits) is
FFFF, Its magnitude in decimal representation is GATE-1993
A. 0 B. 1 C.32,767 D.65,535

12) The subtraction of a binary number Y from another binary number X, done by adding 2's
compliment of Y to X, results in a binary number without overflow. This implies that the result
is
A. Negative and is in normal form GATE-1987

14
B. Negative an is in 2’s compliment form
C. Positive and is in normal form
D. Positive and is in 2's compliment form
13) The output of the combinational circuit given below is GATE-16

(A) A+B+C (B) A(B+C)

(C) B(B+A) (D) C(A+B)

14)The Boolean expression F(X,Y,Z)= converted into the canonical

product of sum(POS) form is GATE-15
(a)
(b)
(c)
(d)
15) For the given boolean function which one of the following is the complete set of essential
Prime implicants F(W,X,Y,Z)= (A
(B) (C) (D) GATE-14
16) In the sum of products function F(x,y,z)=∑m(2,3,4,5), the prime implicants are
(A) y,x (B) y,x (C) y , yz, x (D) y , yz,x ,x z GATE- 12
17) IF x=1,In the given logic equation [x+z{ +( +x )}] { + (x+y)}=1,then GATE-09
(A)y=z (B)y= (C)z=1 (D)z=0
18) The following boolean expression Y= can be minimized
to
(A) (B)Y= GATE-07

(C) (D)
19) The number of product terms in the minimized sum of product expression obtained through
the following karnaugh map (where d indicates don’t care conditions). GATE-06
1 0 0 1
0 D 0 0
0 0 D 1
0 0 0 1
(A)2 (B)3 (C)4 (D)5
20) The boolean expression for the truth table shown is GATE-05
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
15
 0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

(A) (B)
(C) (D)
21) . The Boolean expression is equivalent to GATE-04
(A) (B)
(C) (D)

22) The BDC code for a decimal number 874 is: IES-2013
A. (100001110100) BCD B. (010001111000) BCD
C. (100001000111) BCD D. (011110000100) BCD
23) The decimal equivalent of binary number 10110.11 is: IES-2013
A. 16.75 B. 20.75 C. 16.50 D. 22.75
24) A seven -bit Hamming code is received as 1111101. What is the correct code? IES-2013
A. 1101111 B. 1011111 C. 1111111 D. 1111011
25) Hexadecimal conversion of decimal number 227 will be: IES-2013
A. A3 B. E3 C. CC D. C3

26) The logic Function can be reduced to IES-2015

A) A’B’ B) AB’ C) B’D’ D) AD’

27)The minimum number of NAND gates required to implement A +AB+ABC is: IES-2014
(A) 0 (B) 1 (C) 4 (D) 7
28) The logic function f(A, B, C, D) = (A+BC) (B+ CD) can be expressed to IES-2013
A) AB+BC+AC’D+BCD B) AB+AB’+ACD+BCD’
C) AB+A’B’+A’CD+BC’D D) AB’+AB’+ACD’+BCD

29) The logic function (A+ B) can be expressed in terms of min terms as: IES-2012
A) AB+BA B) A’B+B’A+A’B’ C) A’B+AB D) AB+BA’

30) A3- Variable truth table has a High output for the inputs: 010, 011 and 110. IES-2011
The Boolean expression for sum of product (SOP) can be written as:
A) AB+BC (B) AB’+BC’ C) A’B’+BC D) AB+B’C’

16
 UNIT-2

Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students
I) Multiple Choice Questions:
1. A full subtractor circuit requires ________.
A. Two inputs and two outputs                                 B. Two inputs and three outputs
C. Three inputs and one output                                 D. Three inputs and two outputs
2. A de multiplexer has ________.
A. One data input and a number of selection inputs, and they have several outputs
B. One input and one output
C. Several inputs and several outputs
D. Several inputs and one output
3. How many outputs are on a BCD decoder?
A.4                B.16                 C.8                   D.10
4. A decoder converts ________.
A. Non coded information into coded form     B. Coded information into non coded form
C. HIGHs to LOWs                                         D. LOWs to HIGHs
5. Parallel Adders are
A. Combinational logic circuits B. Sequential logic circuits
C. Both of the above D. None of the above
6. A Full Adder can be realized using
A. One half adder, two OR gates B. Two half adders, one OR gate
C. Two half adders, two OR gates D. Two half adders, one AND gate
7. In which of the following adder circuits is the carry ripple delay is eliminated?
A. Half adder B. Full adder C. Parallel adder D. Carry-look-ahead-adder
8. Which logic gate is a basic comparator?
A. NOR gate B. NAND gate C. X-OR gate D. X-NOR gate
9. A multiplexer is also known as
A. A data accumulator B. A data restorer C. A data selector D. A data distributor
10. Which logic device is called a distributor?
A. Multiplexer B. Demultiplexer C. Encoder D. Decoder
II) Descriptive Questions

17
1. Define combinational logic? Write the design procedure for combinational circuits.
2. Explain the operation of half adder? Realize full adder using logic gates.
3. Explain the operation of half subtractor? Realize full subtractor using logic gates.
4. Discuss the functional principle of 4-bit ripple carry adder. what is its major disadvantage?
5. What is decoder? Draw the logic diagram of 3 to 8 line decoder and explain its operation.
6. What is the difference between encoder and priority encoder? Give the implementation of a
4-bit priority encoder?
7. Discuss how four bit excess - 3 adder circuit is designed. Explain its operation.
8. Discuss how four bit BCD adder circuit is designed. Explain its operation.
9. Briefly describe the concept of look-ahead carry generation with respect to its use in adder
circuits.
10. Draw the circuit diagram of a 4-bit adder/subtractor and briefly describe its functional
principle.
11. Implement the following function with 8 to 1 multiplexer:
f ( w, x, y, z )  w x yz  w x y z  w y

12. Implement the three-variable Boolean function using an 8-to-1multiplexer

F ( A, B, C )  AC  A BC  ABC

B. Question testing the ability of students in applying the concepts.

I) Multiple Choice Questions

1. How many outputs are on a BCD decoder?

A.4                 B.16                  C.8                    D.10
2. Which digital system translates coded characters into a more useful form?
A. Encoder                   B. Display                     C. Counter         D. Decoder
3. In a hexadecimal to binary priority encoder, ______ has ______ priority.
A. 0, high             B. 7, low            C. F, low        D. F, high
4. What control signals may be necessary to operate a 1-line-to-16 line decoder?
A. Flasher circuit control signal           B. A LOW on all gate enable inputs
C. Input from a hexadecimal counter            D. A HIGH on all gate enable circuits
5. How many exclusive-NOR gates would be required for an 8-bit comparator circuit?
A.4                B.6                   C.8                   D.10

18
6. The logic function implemented by the circuit below is (ground implies a logic “0”)

A. F= AND (P, Q) B. F= OR (P, Q)

C. F= XNOR (P, Q) D. F= XOR (P,
Q)
7. A digital system is required to
amplify a binary-encoded audio signal. The user should be able to control the gain of the
amplifier from minimum to a maximum in 100 increments. The minimum number of bits
required to encode, in straight binary, is
A. 8 B. 6 C. 5                                D. 7
8. The minimum number of 2-input NAND/NOR gates required to realize a half adder is
A. 3 B. 4 C. 5 D. 6
9. The minimum number of 2-input NAND gates required to realize a full adder / full subtractor
is
A. 8 B. 9 C. 10 D. 12
10. BCD subtraction is performed using
A. 1’s complement representation B. 2’s complement representation
C. 5’s complement representation D. 9’s complement representation
II) Problems

1. Realize the logic expression given below using a (i) 8:1 MUX (ii) 16:1 MUX
f=∑ m (0,1,3,5,8,11,12,14,15)
2. Design a 32:1 multiplexer using two 16:1 and 2:1 multiplexers.
3. Implement the following multiple output combinational logic circuit using a 4 to 16 decoder:
F1=∑ m (0,1,4,7,12,14,15) F2=∑ m (1,3,6,9,12) F3=∑ m (2,3,7,8,10)
F4=∑ m (1,3,5)
4. Implement the full adder sum and carry functions with decoder and multiplexers.
5. Implement the following 2:1 multiplexer
a) and gate b) or gate c) not gate d) ex-or gate
6. Develop a 3-to-8 line decoder using NOR gates only, and draw its logic diagram.

19
7. A combinational circuit is defined by the equations
f l = AB + A’B’C’
f2 = A + B + C’
f3 = A’B + AB’
Design a circuit which will implement these three equations using a decoder and NAND
gates external to the decoder.
C. Questions testing the analyzing / evaluating ability of students
1. Design a combinational circuit that detects an error in the representation of a decimal
digit in BCD. The output of the circuit must be equal to logic 1 when the inputs contain
any one of the six unused bit combinations in the BCD code.
2. A combinational circuit is defined by the following three functions F1 = x’y’+xyz’, F2 =
x’+y, F3=xy+x’y’. Design the circuit with a decoder and external gates.
3. A logic function has four inputs A, B. C and D that will produce output 1 whenever two
adjacent input variables are 1’s. Treat A and D are also adjacent. Implement this logic
function using 8 x 1 and 4 x 1 multiplexers.
4. Obtain logical functions to design decimal to octal using priority encoder.

D. GATE/IES Questions

1) The output Y of a 2 bit comparator is logic 1whenever 2-bit input A is greater than 2-bit input
B. The no. of combinations for which the output is logic 1 is GATE-2012
A. 4 B. 6 C. 8 D.10
2) The logic function implemented by the circuit below is (ground implies a logic ‘0’)
GATE-2011

A. F= AND (P,Q) B. F= OR (P,Q) C. F= XNOR (P,Q) D. F= XOR (P,Q)

3) The Boolean function realized by the logic circuit shown is
GATE-2010

A. F= Σm(0,1,3,5,9,10,14) B. F= Σm(2,3,5,7,8,12,13)
C. F= Σm(1,2,4,5,11,14,15) D. F= Σm(2,3,5,7,8,9,12)

20
4) In the following circuit X is given by GATE-2007

A. X=AB’C’+A’BC’+A’B’C+ABC. B. X= AB’C’+A’BC’+A’B’C+ABC
C. X=AB +BC+AC D. X=A’B’+B’C’+A’C’

5) The Boolean function f implemented in figure using two input multiplexers is GATE-2005

A. AB’C + ABC’ B. ABC + AB’C’ C. A’BC + A’B’C’ D. A’B’C + A’BC’

6) The minimum no. of 2:1 multiplexers required to realize a 4:1multiplexer is GATE-2004
A. 1 B. 2 C. 3 D. 4

7) The circuit shown in figure below has 4 boxes each described by inputs P, Q, R and outputs
Y, Z with Y= P Q  R; Z=RQ+ P’R+Q P’. The circuit acts as a
GATE-2003

A. 4 bit adder giving P+Q B. 4 bit subtractor giving P-Q

C. 4 bit subtractor giving Q-P D. 4 bit adder giving P+Q+R
8) The Boolean function f implemented in figure using 2 input multiplexers is GATE 2005

21
A. AB’C+ABC’ B. ABC+AB’C’ C. A’BC+A’B’C’ D. A’B’C+A’BC’

9) The minimum number of 2 to 1MUX requires to realize a 4 to 1 MUX are GATE 2004
A. 1 B. 2 C. 3 D. 4

10) The circuit shown in figure converts GATE 2003

A. BCD to binary code B. Binary to Excess-3

C. Excess-3 to gray D. Gray to binary
11) Without any additional circuitry, an 8:1 MUX can be used to obtain GATE 2003
A. Some but not all Boolean functions of 3 Variables
B. All functions of 3 variables but not of 4 variables
C. All functions of 3 variables and some but not all functions of 4 variables
D. All functions of 4 variables

12) In the TTL circuit in figure below s2 to s0 are select lines and x7 and x0 are input lines . s0 and
x0 are LSB’s. The output Y is GATE-2001
A. indeterminate B. A⊕B C. (A⊕B)’ D. C’(A⊕B) + C(A⊕B)’

13) For a binary halfsubtractor having

inputs A and B ,The correct set of
logical expressions for the outputs
D and X are
A. D=AB+A’B, X=A’B B. D=A’B+AB’, X=A’B GATE-1999
C. D=A’B+AB’, X=AB’ D. D=AB+A’B’, X=AB’
14) A 2 bit binary multipler can be implemented using GATE-1997
A.2 inputs AND only B.2 input XORS and 4 input AND gates only
C.Two 2 inputs NORS and one XOR gate D.XOR gates and shift registers
15) The output of the circuit shown in figure is equal to GATE-1995

22
A.0 B.1 C. A’B+AB’ D. (AB)’.(AB)’

16) The logic realized by the circuit shown in figure is: GATE-1992
A. F=A.C B. F=A+C C. F=B.C D. F=B+C

23
 UNIT-3
Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students
I) Objective Questions
1. A sequential logic circuit
A) Must contain flip-flops B) may contain flip-flops
C) does not contain flip-flops D) contain latches
2. A sequential circuit does not use clock pulses. It is
A) an asynchronous sequential circuit B) a synchronous sequential circuit
C) a counter D) a shift register
3. The basic memory element in a digital circuit
A) consists of a NAND gate B) consists of a NOR gate
C) is a flip-flop D) is a shift register
4. A flip-flop can store
A) one bit of data B) two bits of data
C) tree bits of data D) any number of bits of data
5. The characteristic equation of a J-K flip-flop is
A) B)
C) D)
6. The characteristic equation of a D flip-flop is
A) B)
C) D)
7. A shift register using flip-flops is called a
A) dynamic shift register B) flip-flop shift register
C) static shift register D) buffer shift register
8. The transparent latch is
A) an S-R flip-flop B) a D flip-flop
C) a T flip-flop D) a J-K flip flop
9. A universal register
A) accepts serial input B) accepts parallel input
C) gives serial and parallel D) is cable of all of the above

II) Descriptive Questions

1. Distinguish between combinational and sequential circuits.
2. Find the characteristic equation for JK flip-flop.
3. Convert a J-K flip-flop into T flip-flop
4. Convert an SR flip-flop into JK flip-flop
5. Discuss the applications of flip-flops
6. What is a universal shift register
7. Write the design steps of synchronous counters
8. Write the Excitation Tables for D, T, SR, JK Flip Flops
9. Explain the Operating Characteristics of Flip Flops

24
 10. What are shift register counters? Draw Ring Counter and explain the operation with Truth
Table.

B. Question testing the ability of students in applying the concepts.

I) Multiple Choice Questions
1. The output Qn of a J-K flip-flop is 1. It changes to 0 when a clock pulse is applied. The
inputs Jn and Kn are respectively
A) 0 and X B) 1 and X C) X and 1 D) 0 and X
2. The output Qn of a S-R flip-flop is 0.It changes to 1 when a clock pulse is applied. The
inputs Sn and Rn are respectively
A) X and 1 B) 0 and 1 C) X and 0 D) X and 1
3. The outputs Q and Q’ of a master slave S-R flip-flop are connected to its R and S inputs
respectively. Its output Q when clock pulses are applied will be
A) permanently 0 B) permanently 1
C) fixed 0 or 1 D) complementing with every clock pulse
4. A 4-bit binary ripple counter uses flip-flops with propagation delay time of 25ns each. The
maximum possible time required for change of state will be
A) 25ns B) 50ns C) 75ns D) 100ns
5. A 4-bit synchronous counter uses flip-flops with propagation delay time of 25ns each. The
maximum possible time required for change of state will be
A) 25ns B) 50ns C) 75ns D) 100ns

6. A mod-2 counter followed by a mod-5 counter is

A) the same as a mod-5 counter followed by a mod-2 counter
B) a decade counter C) a mod-7 counter D) none of above
7. A sequential circuit with ten states will have
A) 10 flip-flops B) 5 flop-flops C) 4 flip-flops D) 0 flip-flops
8. The output frequency of a mod-16 counter, clocked from a 20 KHz clock input signal is
A) 20 KHz B) 52 KHz C) 625 Hz D) 1250 Hz
9. The output frequency of a mod-12 counter is 6KHz. Its input frequency is
A) 6 KHz B) 500 Hz C) 24 KHz D) 72 KHz
10. The minimum number of flop-flops required for a mod-12 ripple counter is
A) 3 B) 4 C) 6 D) 12

II) Problems
1. Design a 3 bit synchronous up/down counter using JK flip-flop.
2. Design a mod 7 asynchronous counter using JK flip-flop.
3. Design a mod 12 synchronous counter using T flip-flop.
4. Design a BCD up/down counter using SR flip-flop.
5. Design a J-K counter that goes through states 2,4,5,7,2,4,……
6. Convert D flip-flop to SR flip-flop.
7. Convert T flip-flop to JK flip-flop.

C. Questions testing the analyzing / evaluating ability of students

1. Design a circuit using S-R flip-flops that will function as per the state diagram shown below

25
2) Design a synchronous counter that counts as 000, 010, 101, 110, 000, 010 … Ensure that the
un used states of 001, 011, 100 and 111 go to 000 on the next clock pulse. Use J-K flip-flops.

3) Find a modulo-6 gray code using k-map and design the corresponding counter.

4) The content of a 4 bit shift register is initially 1101. The register is shifted six times to the
right, with the serial input being 101101 what is the content of the register after each shift?

D. GATE/IES Questions

1) A synchronous counter counts the sequence 0-1-0-2-0-3 and then repeats. The minimum
number of J-K flip-flops required to implement this counter is GATE-2016
A) 1 B) 2 C) 4 D) 5

2) A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip flop as

follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK
flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop.
Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is
cleared. Which one of the following is the bit sequence (including the initial state) generated
at the Q output of the JK flip-flop when the flip-flops are connected to a free-running
common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding
mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
GATE-2015

A) 0110110…
B) 0100100…
C) 011101110…
D) 011001100…

3) The outputs of the two flip-flops Q 1, Q2 in the figure shown are initialized to 0, 0. The
sequence generated at Q1 upon application of clock signal is
GATE-2014

26
A) 01110…
B) 01010…
C) 00110…
D) 01100…

4) The circuit shown in the figure is a GATE-2014

A) Toggle flip-flop
B) JK flip-flop
C) SR flip-flop
D) Master-Slave D flip-flop

5) When the output Y in the circuit below is ‘1’ . It implies that data has GATE-2011

A) Changed from ‘0’ to ‘1’

B) Changed from ‘1’ to ‘0’
C) Changed in either direction
D) Not changed

6) Assuming that the all flip-flops are in reset condition initially, the count sequence observed
at QA in the circuit shown is GATE-2010

27
 A) 0010111….
B) 0001011….
C) 0101111….
D) 0110100….

7) For the circuit shown, the counter state (Q1Q0) follows the sequences GATE-2007

A) 00,01,10,11,00,……
B) 00,01,10,00,01,……
C) 00,01,11,00,01,……
D) 00,10,11,00,10,……

8) Two D flip-flops are to be connected as a synchronous counter as shown below, that goes
through the following Q1 Q0 sequence 00→01→11→10→00→……………
The inputs D0 and D1 respectively should be connected as GATE-2006

A) and Q0 B) and Q1 C) Q0and Q0 D) Q0and Q1 Q0

9) The present output Qn of an edge triggered JK-Flip Flop is logic ‘0’. If J=1,then Qn+1 is
A) Can’t determined GATE-2005
B) Will be logic ‘1’
C) Will be logic ‘0’
D) Will race around
10) Consider the given circuit. In the circuit race around condition will GATE-2005

A) Does not occur

28
 B) Occur when CLK=0
C) Occur when CLK=1 and A=B=1
D) Occur when CLK=1 and A=B=0

11) A Master-Slave flip-flop has the characteristic that GATE -2004

A) Change in the input immediately reflected in the output.
B) Change in the output occurs when the state of the master is affected.
C) Change in the output occurs when the state of the slave is affected.
D) Both the master and slave states are affected at the same time.

12) The ripple counter shown in the given figure is works as a GATE -1999

A) Mod-3 up counter
B) Mod-5 up counter
C) Mod-3 down counter
D) Mod-5 down counter

13) In the figure shown is A=1 and B=1, the input B is now replaced with a sequence
101010…., the output X and Y will be IES-2005

14) A Master Slave flip flop has the characteristic that

IES-2001
A) Change in input immediately reflected in the output
B) Change in the output occurs when the state of the Master is affected
C) Change in the output occurs when the state of the Slaver is affected
D) Both the master and the slave states are affected at the same time

29
 UNIT-4
Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students
I) Objective Questions
1. The sequential machine is another name of ______.
2. The sequential circuit in which the output depends only on the present state of the flip-flop is
called a ______circuit.
3. The sequential circuit in which the output depends only on the present state of the flip-flop as
well as on the present input is called a ______ circuit.
4. State diagram can also be called as ________.
5. The next state part of the state table is called the ________ table.
6. The process of assigning the states of a physical device to the states of a sequential machine is
known as _______.
7. __________ states are states whose functions can be accomplished by other states.

8. A ________ FSM has more number of states.

9. If the outputs of two states are different after P-state transitions they are said to be ----------.II)
Descriptive Questions
1. What are the Moore and Mealy machines? Compare them.
2. What are the capabilities and limitations of Finite state machines?
3. What does the word state diagram represent and explain with example?
4. Compare state diagram and state table.
4. Explain the reduction of state tables using Partition technique
5. Give various types of state assignment
6. Explain the steps involved in designing FSMs
7. Describe the process of converting Moore to Mealy FSM with an example.
8. Discuss the steps involved to convert a Mealy FSM to Moore FSM.
B. Question testing the ability of students in applying the concepts.
I) Objective Questions

1) In a sequential circuit design, state reduction is done for designing the circuit with
A. a minimum number of flip flops                  B. a minimum number of gates             
C. a minimum number of gates and memory elements      D. none of the above
2) A sequential circuit with 10 states will have
A. 10 flip flops                  B. 5 flip flops                     C. 4 flip flops        D. 0 flip flops
3) In general, a sequential logic circuit consists of
A. only flip flops             B. only gates           

30
C. flip flops and combinational logic circuits     D. only combinational logic circuits
4). Reduction of flip-flops in a sequential circuit is referred to as
A.Reduction B. State reduction C. Next state D. Both a and b
5). M flip-flops produces
A. 2^m-1 states B. 2^1 states C. 2^m+1 states D. 2^m states
6) Two states are said to be equal if they have exactly same
A. Inputs B. Next state C. Output D. Both a and b
7). A State which has no outgoing arcs is called a __________ state.
8) ________ outputs provide additional flexibility in state reduction.

9) The design of a clocked sequential requires

A. the state reduction        B. the state assignment
C. the design of the next state decoder        D. all of the above
II) Descriptive Questions
1. A clocked sequential circuit with single input x and single output z produces an output z=1
whenever the input x complete the sequence 1011 and overlapping is allowed.
(a) Obtain the state diagram
(b) Obtain its minimum state table and design the circuit with D flip flops.
2. A clocked sequential circuit with single input x and single output z produces an output z=1
whenever the input x complete the sequence 1011 and overlapping not allowed.
(c) Obtain the state diagram
(d) Obtain its minimum state table and design the circuit with D flip flops.
3. Realize the 4-bit serial binary adder using D flip flops.
4. For the state tables of the machines given below, find the equivalence partition and
corresponding reduced machine in standard form

5. Design a sequential circuit with minimum hardware to produce the output when the input
data stream contains 1010 pattern. ( consider overlapping pattern is not allowed)
6. Design a sequential circuit with minimum hardware to produce the output when the input
data stream contains 1010 pattern. (consider overlapping pattern is allowed)
7. Convert the following Mealy FSM to Moore FSM.

31
 8. For the state diagram given below obtain the following:
(Assume your own inputs and outputs according to the state diagram)
i) State table
ii) Next state and output functions
iii) Sequential circuit using logic gates and T-flip-flops.

C. Questions testing the analyzing / evaluating ability of students

1. Design a finite state machine (FSM) for a counter that counts through the 3-bit prime
numbers downwards. Assume the counter starts with initial prime value set to 010 as its first
3 bit prime number. You need to provide the state transition table and the state transition
diagram. Assume that the state is stored in three D-FFs.
2. Design a 2-input 2-output synchronous sequential circuit which prduces an output Z=1,
whenever any of the fllowing input sequence-1101,1011, or 1001- occurs. The circuit resets
to the initial state after a 1 output is generated.
3) Construct Moore machine whose output is 1 if the last five inputs were 11010 using JK flip-
flops.
4) Simplify the state table given in the figure below.

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 UNIT-5
Assignment-Cum-Tutorial Questions
A. Questions testing the remembering / understanding level of students
I) Objective Questions

1. PALs tend to execute ________ logic.

A. SAP B.SOP C.PLA D. SPD

2. A ________ PLD consists of a programmable array of AND gates that connects to a fixed
array of OR gates and is usually OTP.

3. By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a
________ PLD is made possible.

4. Which type of PLD should be used to program basic logic functions?

A. PLA B.PAL C.CPLD D. SLD

5. In standard TTL, the 'Totem pole' stage refers to

A. Multi emitter input stage B. Phase splitter
C. Output buffer D. Open collector output stage

6. Which of the following logic families has the shortest propagation delay?
A. CMOS
B. BiCMOS
C. ECL
D. 74SXX

7. Why must CMOS devices be handled with care?

A. so they don’t get dirty
B. because they break easily
C. because they can be damaged by static electricity discharge

8. Special handling precautions should be taken when working with MOS devices. Which of the
following statements is not one of these precautions?
A. All test equipment should be grounded.
B. MOS devices should have their leads shorted together for shipment and storage.

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 C. Never remove or insert MOS devices with the power on.
D. Workers handling MOS devices should not have grounding straps attached to their wrists.

9. Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?

A. Yes
B. No

10. What is the major advantage of ECL logic?

A. very high speed
B. wide range of operating voltage
C. very low cost
D. very high power

II) Descriptive Questions

1. Give the classification of PLDs with respect to their programmability.
2. Explain the internal structure of PROM.
3. What is programmable logic array? How it differs from PROM?
4. Give the comparison between PROM, PLA and PAL
5. Draw and explain the operation of OR gate using diode logic.
6. Draw and explain the 2-mput TTL NAND gate
7. What is transition time? How is it differ front propagation time?
8. Write a short note on various CMOS families and compare them.
9. Discuss the characteristics of ECL family.
B. Question testing the ability of students in applying the concepts.
I) Objective Questions

1) For designing a 4-variable combinational circuit, a designer must use a

A. ROM with atleast 16 locations
B. PLA with atleast 32 product terms
C. PLA with atleast 16 product terms
D. PLA with atleast 16 product terms and 16 input OR gate
2) A 32x10 ROM contains a decoder of size
A. 5x32 B. 32x32 C.32x10 D. 10x32
3. Once a PAL has been programmed:
A. it cannot be reprogrammed. B. its outputs are only active HIGHs
C. its outputs are only active LOWs D. its logic capacity is lost
4. What do the Programmable Logic Devices (PLDs) designed especially for the combinational
circuits comprise?

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A. Only gates B. Only flip flops C. Both a and b D. None of the above
5. Which among the following statement/s is/are not an/the advantage/s of Programmable Logic
Devices (PLDs)?
A. Short design cycle B. increased space requirement
C. Increased switching speed D. All of the above
6. Which of the following digital IC logic families is most susceptible to static discharge?
A. RTL B. ECL C. MOS D. TTL
7. Which of the following output levels would not be a valid LOW for a TTL gate?
A. 0.3 V B. 0.5 V C. 0.2 V D. All are valid.
8. The lower transistor of a totem-pole output is OFF when the gate output is

A. HIGH. B. Malfunctioning. C. LOW D. Over driven.

9. Which potential problem must be overcome when interfacing TTL to CMOS?
A. The HIGH output voltage may be too low.
B. The LOW output voltage may be too high.
C. The HIGH output voltage may be too high.
D. The output current may not be sufficient.

10. Typical TTL LOW level output voltage is

A. 0.3 V B. 0.0 V C. 3.4 V D. 4.0 V.

II) Descriptive Questions

1. Four 4-variable functions are defined by the following equations:
F1(A,B, C,D) = ∑m (2, 3, 6, 7, 11, 15)
F2(A,B, C,D) = ∑m (0, 4, 8, 9, 11, 15)
F3(A,B,C,D) = ∑m (1,3,5,7,10,11)
F4(A,B,C,D) = ∑m (0, 2, 4, 6, 8, 9, 11, 12, 13, 15)
Show how these functions can be implemented on a PLA having an 8*8 AND array and a
4*8 OR array.

2. Implement 3-bit binary to gray code converter using PROM

3. Using PAL, implement full adder digital circuit
4. Implement BCD to seven segment display using PLA
5. Explain the difference between static and dynamic power consumption.
6. Draw and explain the CMOS circuit from the expression Y=A’.B+C.
7. Derive rise time and fall times of CMOS inverter.
8. Discuss the operation of 2-input ECL NOR/OR gate with circuit diagram

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9. Explain with neat diagram interfacing of a TTL gate driving CMOS gates,
C. Questions testing the analyzing / evaluating ability of students

1. Design sequence detector 1101 using PLA and D-flip flops.

2. Derive the PLA programming table for the combinational circuit that squares a 3 bit
number.
3. Design a combinational logic circuit using ROM. The circuit accepts BCD number and
generates an output binary number equal to the 2's complement of the input number.
4. Implement 8:3 priority encoder using PAL.

D. GATE/IES Questions
1) Figure given below shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For
the inputs shown in the given figure, the output Y is GATE-2004

A. 0 B. 1 C. AB
D. (AB)’
2) The output of the 74 series of
TTL gates is taken from a BJT in
GATE- 2003
A. Totem pole and Common Collector configuration
B. Either Totem pole or Open Collector configuration
C. Common Base configuration
D. Common Collector configuration
3) Commercially available ECL gates uses two ground lines and one negative power supply in
order to GATE-1999
A. Reduce power dissipation
B. Increase fan-out
C. Reduce loading effect
D. Eliminate the effect of power line glitches or the biasing circuit
4) The noise margin of a TTL gate is about GATE-1998
A. 0.2 volts B. 0.4 volts C. 0.6 volts D. 0.8 volts
5) In standard TTL, the 'Totem pole' stage refers to GATE-1997
A. Multi emitter input stage B. Phase splitter
C. Output buffer D. Open collector output stage
6) Schottky clamping is resorted in TTL gates GATE-1996
A. To reduce propagation delay B. To increase noise margins
C. To increase packing density D. To increase fan-out

7) In the output stage of a standard TTL, have a diode between the emitter of the pull-up
transistor and the collector of the pull-down transistor The purpose of the diode is to isolate the
output node from the power supply Vcc.[TRUE/FALSE] GATE-1994

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8) The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family.
The circuit represents a GATE-1992

a. NAND b.
AND c. NOR d. OR

9) Among the digital 1C families, ECL, TTL and CMOS, which one of the following is correct?
A. ECL has more propagation delay GATE-1987
B. TTL has the largest tan-out
C. CMOS has the biggest noise margin
D. TTL has the lowest power consumption
10) For a logic family, given that GATE-1987
VOH is the minimum output high level voltage.
VOL is the maximum output low level voltage.
VIH is the minimum acceptable input low level voltage.
VIL is the maximum acceptable input low level voltage.
Then the correct relationship is
A. VIH>VOH>VIL>VOL
B. VOH>VIH>VIL>VOL
C. VIH>VOH>VOL>VIL
D. VOH>VIH>VOL>VIL
11) In standard TTL, the 'totem pole' refers to: IES-2012
A. Multi-emitter input stage
B. The phase splitter
C. Open collector output stage
D. The output buffer
12) CMOS logic families are associated with: IES-2012
1. Low power dissipation
2. High noise immunity
3. Low Fan-cut
4. Comparatively high logic voltage swing
A. 1, 2 and 4 only
B. 1, 2 and 3 only
C. 2, 3 and 4 only
D. 1, 2, 3 and 4
13) In standard TTL, the 'totem pole' refers to: IES-2012
A. Multi-emitter input stage '
B. The phase splitter
C. Open collector output stage
D. The output buffer

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14) The switching speed of ECL is very high, because the transistors: IES-2013
A. are switched between cut-off and saturation region
B. are switched between active and saturation region
C. are switched between active and cut off region
D. may operate in any of the three regions
15) Which one of the following statements is correct? IES-2013
A. PROM contains a programmable AND array and a fixed OR array
B. PLA contains a fixed AND array and a programmable OR array
C. PROM contains a fixed AND array and programmable OR array
D. PLA contains a programmable AND array and a programmable OR array

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