BO GIAO DUC & AO TAO TRNG AI HOC KY THUAT CONG NGHE THANH PHO HO CH MINH

Ths. NGUYEN TRONG HAI

TOM TAT BAI GIANG

VHDL
Very High speed integrated circuit Description Language

LU HANH NOI BO

07/2005

Bi ging Thit K H Thng S

Phn VHDL

VHDL
Very High speed integrated circuit Description Language
I. CU TRC CA MT THIT K DNG NGN NG VHDL.
---------------------------------- Ghi ch ---------------------------------

PACKAGE
library use ENTITY ARCHITECTURE CONFIGURATIONS 1. PACKAGE (KHI).

(Ty chn) (Th vin) (Bt buc) (Bt buc) (Ty chn)

Package l mt vng lu tr cc d liu dng chung cho cc entity. M t d liu bn trong mt package cho php c tham kho bi mt entity khc, v vy d liu c th c dng chung. Mt package bao gm 2 phn: phn m t nh ngha giao din cho package, phn thn n nh cc hot ng c th ca package. C php khai bo khi c xc nh l: PACKAGE example_arithmetic IS -- cc khai bo khi c th cha cc khai bo sau: Subprogram declaration. Type, subtype declaration. Constant, deferred constant declaration. Signal declaration creates a global signal. File declaration. Alias declaration. Attribute declaration, a user-define attribute. Attribute specification. Use clause. END example_arithmetic; Tt c cc i tng khai bo trong package c th c truy xut bi bt k mt thit k no bng cch s dng mnh use v khai bo library. library my_lib; use my_lib.example_arithmetic.all; Mt s th vin chun

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Bi ging Thit K H Thng S library ieee; use ieee.std_logic_1164.all;

Phn VHDL

std_logic_1164: l th vin logic chun ca IEEE (on 1164), mc ch cung cp cc chun c bn c th m t cc kiu d liu kt ni trong VHDL. std_logic_arith: l th vin cha tp cc php ton v hm Kiu std_logic c th c cc gi tr U X 0 1 Z W L H Uninitialized Unknown Zero One Tristate (Must be upper case!) Weak unknown Weak Zero Weak One Don't care

Ngoi ra c th t to ring cc th vin trong thit k. 2. ENTITY Khai bo entity ch dng m t ng vo v ng ra ca mt thit k. Mc cao nht ca bt k mt thit k VHDL l mt khai bo entity n, khi thit k trong VHDL, tn ca file lu tr phi trng vi tn theo sau ca t kha entity. V d, m t b cng bn phn sau

X1 A A1 B CARRY SUM

library ieee; use ieee.std_logic_1164.all; ENTITY HALF_ADDER IS PORT( A,B : IN BIT; SUM,CARRY : OUT BIT); END HALF_ADDER;

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Bi ging Thit K H Thng S Trong khai bo ENTITY, c 4 kiu tn hiu khc nhau:

Phn VHDL

IN: m t cc ng vo entity. Kiu IN th c s dng cho cc ng vo clock, cc ng vo iu khin, OUT: m t dng d liu i ra khi entity, entity s khng th c cc tn hiu ny, kiu OUT ch c s dng khi tn hiu khng c s dng bi bt k kiu no trong entity. BUFFER: Kiu tn hiu ny m t dng d liu i ra khi entity, nhng entity c th c nhng tn hiu ny (mc ch c li tn hiu ng ra bn trong ca cu trc). Tuy nhin , tn hiu s khng th iu khin t ng ra ca entity, v vy n khng th c s dng cho cc d liu ng vo. INOUT: Kiu tn hiu ny cho php tn hiu c th c c hai kiu: vo v ra, khi khai bo tn hiu theo kiu INOUT th tn hiu c th c iu khin t ng ra ca entity. Kiu tn hiu ny ch nn s dng khi tht cn thit(v d nh bus d kiu 3 trng thi), v khi s dng kiu tn hiu ny th m ca chng trnh s tr nn kh hiu hn i vi ngi thit k.

Loi tn hiu cng phi c m t trong khai bo PORT, loi tn hiu s m t cc gi tr m tn hiu c th c n nh, ngoi ra c th m t mt vector nhng tn hiu c cng loi. Lu : trong file report, nu khng gn chn linh kin th cc bin ng vo v ra s c gn ngu nhin. gn cc chn, c th thc hin t phn mm h tr hoc thc hin nh sau: V d, ENTITY my_design is Port (a, b c d e : in integer range 0 to 7; : bit_vector (3 to 5); : bit_vector (27 downto 25); : out Boolean);

attribute pinnum: string; attribute pinnum of c: signal is "1,2,3"; attribute pinnum of d: signal is "6,5,4"; attribute pinnum of e: signal is "2"; END my_design; 3. ARCHITECTURE. Chc nng ca architecture l m t mi lin h gia cc tn hiu ng vo v tn hiu ng ra ( bao gm c nhng tn hiu BUFFER), c th vit nhiu kin trc khc nhau trong mt entity, nhng ch mt trong s c kh nng xut hin trong m VHDL. architechture c 3 dng: m t cu trc (structure); m t dng d liu (data flow); m t hnh vi (behavioral)

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Bi ging Thit K H Thng S M t architechture di dng cu trc (structure) V d, chng trnh b cng trn s c dng: ENTITY HALF_ADDER IS PORT( A,B : IN BIT; SUM,CARRY : OUT BIT); END HALF_ADDER; ARCHITECTURE HA_STRUCTURE OF HALF_ADDER IS Component XOR2 Port(X,Y: in BIT; Z: out BIT); End component Component AND2 Port(L,M: in BIT; N: out BIT); End component BEGIN X1: XOR2 port map (A,B,SUM); A1: AND2 port map (A,B,CARRY); END HA_STRUCTURE;

Phn VHDL

Ch , trong trng hp ny cc tn hiu trong Port Map(nh x cng) ca i tng trong thnh phn ny v cc tn hiu trong khai bo phi c lin kt theo v tr M t architechture di dng dng d liu (data flow) V d, chng trnh b cng trn s c dng: ENTITY HALF_ADDER IS PORT( A,B : IN BIT; SUM,CARRY : OUT BIT); END HALF_ADDER; ARCHITECTURE HA_STRUCTURE OF HALF_ADDER IS BEGIN SUM<=A xor B; CARRY<=A and B; END HA_STRUCTURE; M hnh dng d liu s dng pht biu gn tn hiu ng thi, k hiu <= ch gi tr c gn cho tn hiu. Php gn c thc hin khi c 1 s kin tn hiu ca biu thc bn phi.

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Bi ging Thit K H Thng S M t architechture di dng hnh vi (behavioral)

Phn VHDL

Kiu m t hnh vi bao gm tp hp th t cc php gn tn hiu tun t c khai bo bn trong pht biu process. Bin c khai bo trong process l bin cc b. Tn hiu khng c khai bo trong process V d, chng trnh b cng trn s c dng: ENTITY HALF_ADDER IS PORT( A,B : IN BIT; SUM,CARRY : OUT BIT); END HALF_ADDER; ARCHITECTURE HA_STRUCTURE OF HALF_ADDER IS BEGIN Process(A,B); Begin SUM<=A xor B; CARRY<=A and B; End process; END HA_STRUCTURE; V d, m t mt D-FF:
D Q

CK Q

ENTITY DFF IS PORT( D,CK Q END DFF; ARCHITECTURE DFF_BEHAVIOR OF DFF IS BEGIN Process(CK); Begin If rising_edge(ck) then Q<=D; End if; End process; END DFF_BEHAVIOR ; GV: Nguyn Trng Hi Trang 5 : IN BIT; : OUT BIT);

Bi ging Thit K H Thng S M t architechture di dng hn hp (mixed style) C th trn ln 3 kiu trong mt architechture V d, m t mch cng ton phn (FULL_ADDER) sau

Phn VHDL

structure A X1

dataflow

: B

SUM

Cin

CARRY

behavior
ENTITY FULL_ADDER IS PORT( A,B,CIN END DFF; ARCHITECTURE FA_MIXED OF FULL_ADDER IS Component XOR2 Port(X,Y: in BIT; Z: out BIT); End component Signal S1: BIT BEGIN X1: XOR2 port map (A,B,S1); Process(A,B,CIN); Variable T1,T2,T3: BIT; Begin T1:=A and B; T2:=A and CIN; T3:=B and CIN; COUT<=T1 or T2 or T3; End process; SUM<=S1 xor CIN; END FULL_ADDER; GV: Nguyn Trng Hi Trang 6 --structure --behavior --Khai bo tn hiu cc b trong architechture : IN BIT; SUM, COUT : OUT BIT);

--dataflow

Bi ging Thit K H Thng S 4. CONFIGURATION Configuration dng lin kt cc hp phn ti entity

Phn VHDL

configuration ban u c th c n nh ti rt nhiu architecture trong mt entity. ENTITY component_i IS

ARCHITECHTURE Behavioral OF component_i IS .

ARCHITECHTURE dataflow OF component_i IS .

ARCHITECHTURE Structural OF component_i IS .

nh cu hnh cho php m phng cc thit k thnh phn con, d dng kim tra c thit k hn mt chng trnh ln. Mt cu hnh c dng ni tng cp nh sau: Mt thn architecture ti khai bo entity ca n. Mt component vi mt entity.

V d, xy dng mt entity FULL_ADDER trn c th tch ra lm ba architecture body: FA_BEHAVIOR, FA_STRUCTURE, v FA_MIXED. Mt architecture bt k c th c chn bng cch c t mt configuration thch hp. Library HS_LIB, CMOS_LIB; ENTITY FULL_ADDER IS Port(A,B,Cin : IN BIT; SUM, Cout: OUT BIT); END FULL_ADDER; ARCHITECTURE FA_STR OF FULL_ADDER IS Component XOR2 Port(D1,D2 : IN BIT; DZ : OUT BIT); END componen; Component AND2 Port ( Z: OUT BIT; B0,B1: IN BIT); END Component; -- c t cu hnh: GV: Nguyn Trng Hi Trang 7

Bi ging Thit K H Thng S CONFIGURATION FA_BINDING OF FULL_ADDER IS For FA_STR For X1,X2 : XOR2 use entity WORK.XOR2(XOR2BEH); End for;

Phn VHDL

-- lin kt thc th vi nhiu i tng ca mt thnh phn. For A3: AND2 Use entity HS_LIB.AND2HS(AND2STR); PORT MAP (HS_B => A1, HS_Z=>Z, HS_A => A0 ); End for; --lin kt thc th vi cc i tng n ca mt thnh phn. For all : OR2 Use entity CMOS_LIB.OR2CMOS(OR2STR); End for; -- lin kt thc th vi tt c cc i tng ca thnh phn OR2. For others: AND2 Use entity WORK.A_GATE(A_GATE_BODY); PORT MAP(A0,A1,Z); End for; -- lin kt thc th vi tt c cc i tng khng c lin kt ca thnh phn AND2. End for; End for; Signal S1, S2, S3, S4, S5: BIT; BEGIN X1: XOR2 port map(A, B, S1); X1: XOR2 port map(S1, Cin, SUM); A1: AND2 port map(S2, A, B); A2: AND2 port map(S3, B, Cin); A3: AND2 port map(S4, A, Cin); O1: OR2 port map(S2, S3, S5); O2: OR2 port map(S3, B, Cin); NAND_GATE port map(S4,S5,Cout); END FA_STR;

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Bi ging Thit K H Thng S

Phn VHDL

C 4 c t cu hnh trong phn khai bo ca thn kin trc (architecture body): c t th nht ch rng i tng c nhn X1 v X2 ca component XOR2 lin kt vi entity bi cp entity - architecture XOR2 v XOR2BEH c sn trong th vin WORK. c t th hai lin kt i tng component AND2 c nhn A3 n entity bi cp entity - architecture AND2HS v AND2STR c trong th vin thit k HS_LIB. Anh x ca cng thnh phn (AND2 ) v cc cng thc th(AND2HS) c lin kt theo tn (name association). c t th ba ch rng tt c cc i tng ca component OR2 c lin kt vi entity bi cp entity - architecture c sn trong th vin thit k CMOS_LIB. c t cui cng ch rng tt c cc i tng khng lin kt (unbound) ca component AND2, i tng A1 v A2 c lin kt ti entity khc l: A_GATE c architecture A_GATE_BODY, kin trc ny c sn trong th vin WORK.

Trong v d ny ch ra cc i tng ca cung mt thnh phn (component) c th c lin kt(bound) vi cc thc th khc nhau. II. CC KHAI BO TRONG VHDL. 1. Khai bo kiu h tr. Kiu lit k, s nguyn, dy mt chiu v kiu bn ghi. Kiu lit k. V d, Type STD_ULOGIC is (U, X, 0, 1, Z, W, L, H, _); --std_ulogic l 1 kiu lit k bao gm 9 gi tr c khai bo l U<X<0<1<Z<W<L<H< _. Signal S: STD_ULOGIC; Type STATE_TYPE is (HALT, READY, RUN, ERROR); --HALT< READY< RUN< ERROR Variable STATE: STATE_TYPE; Type CODE_TYPE is (NUL, 0, 1); Function CODE (C: in INTEGER) return CODE_TYPE; Kiu STD_ULOGIC v STATE_TYPE l 2 kiu lit k; tuy nhin mc tru tng ca STATE_TYPE cao hn ca STD_ULOGIC. Trt t cc gi tr xut hin trong khai bo lit k nh ngha th t ca chng, gi tr bn tri nh hn gi tr bn phi. Kiu nguyn. Kiu nguyn l 1 tp hp nhng gi tr ri vo vng s nguyn c ch ra. V d, type LENGTH is range 0 to 1000;

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Bi ging Thit K H Thng S type BYTE_INT is range 128 to 127; type MY_INTEGER is range -2147483647 to 2147483647; Kiu dy nhiu chiu. Kiu dy nhiu chiu c VHDL h tr nh ngha mt tp ch s.

Phn VHDL

Tuy nhin ch c dy mt chiu c cng c tng hp cho php. Vy phi khai bo hai dy mt chiu thay v mt dy hai chiu. V d, Type WORD is array (31 downto 0) of BIT; Type RAM is array (1023 downto 0) of WORD; Thay v: Type OTHER_RAM is array (1023 downto 0, 31 downto 0) of BIT Kiu bn ghi Kiu bn ghi nh ngha tp cc kiu khc nhau. Mi thnh phn bn ghi c nh v bng tn ca n, v c th dch bi cng c tng hp nh l gi tr di khng i hoc c bin i trong vi trng hp (khi nim bn ghi khng cn tn ti na, a ch thnh phn c tnh ton ch mt ln v tr thnh m c nh). V d, Architecture A of E is Type CODE_TYPE is (NONE, DATA, STATMT) ; Type ITEM_TYPE is record; CODE: CODE_TYPE; INT: INTEGER; End record; Signal S1, S2 : ITEM_TYPE; Begin Process Variable V: ITEM_TYPE; Begin S1 <= V; V:= S2; S2.INT <= 0; V.CODE := S1.CODE; Tiu chun IEEE Khi STD_LOGIC_1164 nh ngha cc gi tr kiu a lun l. Khi ny c h tr bi tt c cng c tng hp. V d, Type STD_LOGIC is ( U, -- Uninitialized X, -- Forcing Unknown 0, -- Forcing 0 1, -- Forcing 1 Z, -- High Impedance W, -- Weak Unknown L, -- Weak 0 GV: Nguyn Trng Hi Trang 10

Bi ging Thit K H Thng S H, -- Weak 1 U, -- Dont care );

Phn VHDL

'X', '1', '0' l gi tr mnh v tri hn cc gi tr yu 'W', 'L', 'H' v chng li tri hn 'Z'. '1' v '0' c th hiu nh l ni ngun v ni t. Gi tr 'U'v 'W' c gi l gi tr gn lun l, ch yu c chc nng m phng v hin nhin khng c ngha phn cng. Gi tr 'U' l ch tn cng bn tri trong nh ngha STD_ULOGIC lit k, v l gi tr mc nh cho cc bin s hoc cc tn hiu ban u trc khi c gn cc gi tr 'X' v 'W' biu din trng thi m b m phng khng th xc nh c. 'W' c nh hng t hn c th b gn n '0', '1' v 'X'. Do cc cng c tng hp cha th phn bit gia cc mnh yu, nn cc gi tr 'L' v 'H' khng c ng ngha tng hp chun. 'Z' c th c dng trong m phng nh l kt qu khi khng c b iu khin no ang hot ng. i vi tng hp, phn cng c bit c m ch khi gn php gn gi tr v hng 'Z' c dng, mc ch ca php gn l t u ra ti b m 3 trng thi. 2. Cc kiu khng h tr. Vi kiu d liu khng c dng cho mc ch tng hp (v d, tt c kiu vt l nh ngha bi ngi thit k khng c h tr), kiu vt l nh ngha trc TIME khng c h tr. Ngay c s rng buc thi gian i vi tng hp khng c biu din trong VHDL vi cc biu thc thi gian. Do mnh after v reject khng c dch v khng c cng c tng hp no c th m bo rng tn hiu s thay i sau mt khong thi gian chnh xc. Nu cc mnh ny c s dng trong m t VHDL, cng c tng hp s b qua v kt qu phn cng c th mu thun vi m t u vo. iu ny ni rng kiu mu chnh xc cho tng hp khng dng bt k biu thc thi gian no, bao gm lnh biu thc thi gian wait for. Trong m phng qa trnh b tm ngng trong thi gian nh ngha bi biu thc for. Trong sut giai on ny, tt c tn hiu gi cc gi tr mi ca chng. Trong min tng hp khng th phng on phn cng vi cc kt qu nh vy m khng cung cp phn cng v n qu phc tp v qu c bit (nh b nh thi gian). 3. Cc kiu con. Cc kiu con rt hu dng cho tng hp. mi bc m phng, cc kiu con cung cp kh nng mnh m cho vic kim tra s dng kiu. Cc kiu con cn tha hng tt c ton t nh ngha t cc kiu c bn ca chng. V d, chc nng thao tc trn kiu BIT_VECTOR c th c dng vi bt k kiu con ca BIT_VECTOR di bng gi tr cn li trong khong thch hp. III. CC I TNG VHDL. i tng trong VHDL l cc thng tin v hng s, bin s v tn hiu. 1. Hng s. Cc khai bo hng s: Constant constant_name : type_name [:=value] V d,

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Bi ging Thit K H Thng S Constant rise_time : time :=10 ns; Constant bus_width : integer :=8; V d, Type TAB2 is array (BIT, BIT) of BIT; Constant AND_TAB: TAB2 := ((0, 0), (0, 1));

Phn VHDL

Gi tr hng s c tnh ton ch mt ln. Qu trnh tng hp chp nhn hng s ca bt k kiu tng hp no. Trong trng hp khai bo nh vy khng to ra bt k phn cng no: Nu hng s c dng trong php gn tn hiu nh cc lnh di y th phn cng c suy ra: V d, Signal Z, A, B : BIT; Z <= AND_TAB (A,B); S khai bo hng s khng to ra phn cng. Hng s ch cung cp iu kin xc nh phn cng. Hng s l mt biu thc v vy n tn ti trong cng mt ni nh cc biu thc: V d, Pha phi ca php gn tn hiu Constant COD1: BIT_VECTOR := X EA; Constant MASK: BIT_VECTOR:=01111111; Signal V, R, A: BIT_VECTOR(7 downto 0); begin V <= COD1; R <= A and MASK; V d, trong biu thc lnh if hoc case

If S= CST1 then
Case VALUE is

When CST_N =>

V d, trong lnh ng thi c iu kin:

Z <= CST1 when A=1 else S when B= CST2 else CST3;

2. Khai bo bin s v tn hiu. Cc khai bo bin s Variable variable_name : type_name [:=value]; V d, Variable CTRL_STATUS : BIT_VECTOR (10 DOWNTO 0);

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Bi ging Thit K H Thng S

Phn VHDL

y bin CTRL_STATUS l mt dy c 11 phn t, mi phn t trong dy c kiu l BIT V d, Thc hin mch sau

(DATA and 01)(0) (DATA and 10)(1)

CK Q

Clock Entity MEMO_ONE is Port ( DATA: in BIT_VECTOR (1 downto 0); CLOCK :in BIT; Z: out BIT); Constant K1: BIT_VECTOR : = 01; Constant K2: BIT_VECTOR := 10 ; End MEMO_ONE;

Architecture A of MEMMO_ONE is Begin

Process (CLOCK) Variable A1, A2: BIT_VECTOR(DATArange); Variable A3: BIT; Begin If CLOCK = 1 and CLOCKevent then A1 := DATA and K1; A2 := DATA and K2; A3 := A1(0) or A2(1); Z <= A3; End if; End process;

End A;
Cc bin s s dng trong v d trn khng to ra bt k phn cng no. Tht ra qu trnh tng ng c th c cho m khng c bt k bin no, tt c cc bin c thay th bi cc phng trnh ca chng. Chng ta c th vit li nh sau.

Begin If CLOCK = 1 and CLOCKevent then Z <= (DATA and K2)(1) or (DATA and K1)(0); End if;
Khai bo tn hiu: C php: Signal signal_name : type_name [:=value]

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Bi ging Thit K H Thng S V d, Signal clock: bit; --khai bo tn hiu clock ca kiu bit ly gi tr 1,0 Signal data_bus : bit_vector( 0 to 7);

Phn VHDL

-- khai bo tn hiu data_bus thucc kiu bit_vector c rng 8 bit 3. Cc gi tr khi ng. Trong VHDL, c 3 loi gi tr ban u: Gi tr mc nh t nh ngha kiu hay kiu con Gi tr ban u khi i tng c khai bo Gi tr c gn khi s dng mt pht biu lc bt u qu trnh.

Trng hp th nht v th hai s b b qua bi cng c tng hp, nn c th pht sinh mu thun gia hot ng m phng v kt qu tng hp. Do ngh phi khi ng mt cch r rng v c h thng cc bin v tn hiu vi cc lnh c bit. iu ny t c trong phn m tng hp phc v cho vic x l thit lp/thit lp li v s khi ng phi c trnh by trong phn ny. Nu cng out hoc thng s out ca chng trnh con c gi tr mc nh, chng hot ng ging nh mt gi tr khi ng cho tn hiu hoc bin v s b cng c tng hp b qua. 4. Cc ton t s hc. Ton t logic v ton t bit l mt phn ca ton t s hc. VHDL nh ngha by loi ton t. Chng c ch bng di y vi s tng dn mc u tin. Loi Lun l Quan h Dch Cng Mt ngi Nhn Hn hp Ton t lun l Ton t lun l v ton t not chp nhn cc ton hng c cc kiu BIT, BOOLEAN, v VECTOR vi kch thc ging nhau. Mt quy c c chp nhn rng ri cho gi tr boolean: TRUE tng ng vi gi tr BIT '1' v ngc li. Ton t nand v nor khng kt hp vi nhau trong 1 c php lin tc, chng phi c ngn cch bng du () : A and B nand C; -- tri lut (A and B ) nand C;-- ng lut; = /= > < + - & + * / mod rem Cao nht ** abs not Ton t Or and nor nand xor xnor >= <= Sll Srl Sla SRA Rol Ror u tin Thp nht

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Bi ging Thit K H Thng S V d, Signal S, X, Y: BIT_VECTOR (1 downto 0); Signal R, A, B, C : BIT; Signal T, D, E, F, G: BOOLEAN; -Begin S <= X and Y; R <= (A and B) and C; T <= D xor E xor F xor G; S kt qu ca cc hm trn nh sau: X(1..0) S(1..0) D Y(1..0) A B C Ton t quan h. E

Phn VHDL

T F G

Ton t quan h lun tr v gi tr Boolean '0' hoc '1' v l kt qu ca s so snh hai ton hng cng mt kiu c bn. Trong m phng, ton t bng v khc c nh ngha r rng cho cc kiu. Kt qu l TRUE nu hai ton hng c cng gi tr. Cc ton t quan h c nh ngha cho tt c cc kiu v hng v dy mt chiu. Th t ca kiu v hng c nh ngha bi khai bo ca n, kiu 'LEFT' thp hn kiu 'RIGHT'. i vi dy mt chiu, th bc quan h ca chng c nh ngha bi bc ng ngha. V d, 0 < 1 A < BC 10 < 101 -- is true -- is true -- is also true

Ton t quan h ny khng th dng so snh cc vector bit m ha cc gi tr lit k. Ton t ny nu thc hin vi khi s hc th kt qu ca lnh cui cng "10" < "101" s c thng dch khc nhau i vi s khng du hoc s c du. Cc ton t cng. Ton t cng v tr c nh ngha cho cc ton hng s nguyn. Tt c cc cng c tng hp u ci t cc ton t ny v thng s dng vi mt s rng buc. Lu , i khi dng cc du ngoc n nhm mt tp hp cc cng li. Ni cch khc hai biu thc khc nhau chy nh nhau nhng to ra phn cng khc nhau GV: Nguyn Trng Hi Trang 15

Bi ging Thit K H Thng S V d, Architecture Signal A, B, C: BIT_VECTOR(2 downto 0); Signal B, S, R: BIT_VECTOR (0 to 5); Signal D: BIT; Begin A <= D &not D &D; S <= S & B (0 to 2) ; R <= C(1 downto 0) & 000 & D; Cc ton t dch chuyn.

Phn VHDL

Cc ton t dch chuyn h tr cho BIT_VECTOR Cc ton t dch chuyn v quay l sll, srl, sla, sra, rol v ror. Cc ton t nhn. Php chia "/", php nhn "*", ly modulo "mod", ly s d "rem" c xp trong nhm nhn. Ch c ton t nhn c h tr thm v d khng hn ch i vi tt c cc kiu s nguyn. i vi vi cng c tng hp, nhiu chin lc nhn c ngh to ra phn cng. "/", mod, v rem c h tr c hn ch i vi cc gi tr ca ton hng v phi, cc cng c tng hp i hi cc gi tr ny l dng v l ly tha ca 2. Hn na chng thng l cc hng s ton cc. Kt qu phn cng ca ton t ny da trn cc ton t dch bit. V d, xy dng mt b m modulo 4. Entity INCREMENTER is Port (CLK : in BIT; RST : in BIT; R : out NATURAL range 0 to 3) ; End INCREMENTER; Architecture A of INCREMENTER is Signal MEM: NATURAL range 0 to 3; Begin Process If CLK = 0 then If RST = 1 then MEM <= 0; Else MEM <= (MEM +1) MOD 4; End if; End if; End process; R <= MEM; End A; Cc ton t hn hp. Abs, gi tr tuyt i c h tr cho tt c cc gi tr s nguyn, Ton t s m "**", c h tr vi hn ch ton hng tri l hng s ton cc, gi tr ca n phi l 2. GV: Nguyn Trng Hi Trang 16

Bi ging Thit K H Thng S 5. Php gn bin s.

Phn VHDL

Bin khng dng chung c khai bo trong qu trnh hoc trong phn khai bo chng trnh con. Php gn bin c thc hin bi ton t :=, thao tc ny xy ra ngay lp tc khi tnh ton. Do , gi tr ca bin ch thay i bi lnh gn tip theo nu gi tr mi khc vi gi tr c. V d, cch gn bin khc nhau: A:= 0 ; REC.FIELD := B; VECTOR := X AA; WBUS(1) := F(A); WORD(3 to 4) := 10; REC := (A, 3, 10); -- gi tr integer 0 c gn cho bin A --B c gn cho bn ghi FIELD ca REC -- php gn vector ton cc -- php gn phn t ca vector -- php gn mt nhm phn t vector -- Php gn gi tr theo v tr ca vetor -- Php gn vi tn Hn na, phn bn tri ca lnh gn, nhiu bin s c th gp li. V d Variable V: BIT_VECTOR(1 to 3); Variable A, B, C: BIT; --Hai trng thi sau l tng ng (A, B, C) := V; (1 => A;2 => B; 3 => C):= V; Lu , bin khai bo trong chng trnh con ch tn ti trong chng trnh con ny v bin mt ngoi chng trnh con. V vy, nu bin s c gn, kt qu b mt sau khi chy lnh return ngoi tr c tr v khi dng thng s out bn trong th tc hoc lnh return bn trong hm. Tuy nhin bin ny c th to ra mt phn nh nu thi im ng b xy ra trc khi chng trnh con kt thc. 6. Php gn tn hiu. Mc ch ca gn tn hiu ging nh php gn bin. Hiu qu ca php gn tn hiu ch xy ra sau lnh ng b (lnh wait ). Signal <= a_waveform_with_one_item_and_without_delay_expression 7. Lnh ng b. Trong VHDL lnh duy nht ng b l lnh wait. Mt qu trnh phi cha t nht mt lnh wait. C hai cch dng lnh wait khc nhau l: i mt s kin trn mt tn hiu ty thuc vo danh sch. Danh sch ca wait phi bao gm tt c tn hiu c c trong qu trnh:

REC := (LETTER => C, FIELD => 3, BIT2 => 11);

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Bi ging Thit K H Thng S V d, Process Begin Wait on A, B, C, D; S <= A or B; If E then R <= C + D; Else R <= C+1; End if; End process;

Phn VHDL

i mt s kin xy ra trn tn hiu ng h (Clock). Tn hiu ny phi l duy nht, clock c xc nh bi cc s kin v sn xung. Wait until CLK = 1;

V d, Nu kiu ca tn hiu ng h khng l BOOLEAN hoc BIT, m l kiu a gi tr, th ph hp vi s m phng, iu kin sau phi c thm vo lnh wait: CLK'LAST_VALUE = '0'. iu ny xc nh sn ln hp l cho tng hp. iu kin cnh xung ng h tr thnh: V d, Wait until CLK =1 and CLKlast_value = 0; Nu lnh wait l r rng, lnh ng b c m t bi mt lnh iu kin if V d, If CLK = 0 and CLKevent and CLKlast_value =1 then Hoc s dng thuc tnh 'STABLE vi gi tr thi gian mc nh 0ns, ('STABLE l mt hm chp nhn kiu thng s TIME c gi tr mc nh l zero). V d, If CLK = 0 and not CLKstable and CLKlast_value =1 then Lnh iu kin. C hai cch biu din lnh iu kin : lnh if v lnh case Lnh if. Lnh if bao gm c r nhnh elsif v else, ch mc u tin thc hin cc r nhnh khc nhau. V d, thit k cc MUX sau

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Bi ging Thit K H Thng S Process (S1, S2, R3, R1, R2, R3, R4) Begin If S1 = 1 then RESULT <= R1; Elsif S2 = 0 then RESULT <= R2; Elsif S3 = 1 then RESULT <= R3; Else RESULT <= R4; End if; End process; Lnh case.

Phn VHDL

Trong lnh case, mi nhnh c cng cp vi nhau (lnh if v lnh elsif, mi nhnh c kim tra mt cch tun t). Trong lnh case, tt c cc gi tr c th phi c a vo ht v chng l duy nht, khng c u tin. nhm li tt c cc gia tr "don't care", mnh others c th c s dng. Lu , others khng bao gi nn dng nu tt c gi tr c lit k trc V d, Thit k mch sau

Type CODE_TYPE is (ADD, SUB, RST, INCX); Subtype WORD is INTEGER range 0 to 3; Signal CODE: CODE_TYPE; Signal X, Y, R: WORD; Process (CODE, X, Y) Begin Case X is When 0 => R <= Y; When 1 => R <= CODE_TYPEpos (CODE); When others => R <= 0; End case; End process; Ch rng nhnh others c dng cho gi tr 2 v 3 ca tn hiu X. GV: Nguyn Trng Hi Trang 19

Bi ging Thit K H Thng S To ra b nh.

Phn VHDL

i khi mt vi gi tr iu kin khng ng, v th cc gi tr c kt qu t cc iu kin ny trng thi khng i. Trong trng hp ny, phi c phn t nh . V d, If CONDITION (l1, l2,l3) then RESULT <= DATA (l1, l2, l3); End if; Bi v chc nng CONDITION khng lun lun tr v hng s TRUE, nn i khi RESULT s khng thay i v s gi nguyn gi tr. Vi cc dng lnh trn th loi phn t nh c to ra s ph thuc vo biu din ng b. Phn t nh cng c m ch nu tn hiu u ra khng xut hin trong bt k r nhnh c th no ca chng trnh. RESULT l tn hiu c c (pha bn phi ca php gn tn hiu) v c vit (pha bn tri ca php gn tn hiu). V vy, phn t nh l cn thit. Nu tn hiu ny ph thuc vo danh sch, th ch c mch ci t c to ra. Ngc li, nu ch ph thuc vo cc gi tr u vo (l1, l2, l3) th mt phn t nh mch lt c to ra. V d, Process (I1, l2, l3) inferring a flip-flop Begin If CONDITION (l1, l2, l3) Then RESULT <= DATA(l1, l2 , l3, RESULT); End if; End; Process (l1, l2, l3, RESULT) inferring a latch Begin If CONDITION (l1, l2, l3) Then RESULT <= DATA (l1, l2, l3. RESULT); End if; End; m bo khng to ra phn t nh, mt php gn tn hiu u ra mc nh phi c vit trc lnh iu kin nh sau: RESULT <= DEFAULT_VALUE; -- default assignment If CONDITION (l1, l2, l3) then RESULT <= DATA (l1, l2, l3, RESULT); End if; Php gn tn hiu u tin ny khng c nhm ln vi gi tr ban u c gii thch. V d, mt r nhnh else c to ra r rng : If CONDITION (l1, l2, l3) then RESULT <= DATA (l1, l2, l3, RESULT); else RESULT <= DEFAULT_VALUE; End if;

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Bi ging Thit K H Thng S Lnh lp li.

Phn VHDL

Trong VHDL c hai loi lnh lp li, vng lp for v vng lp while. Vng lp v hn loop end loop c th c xem xt nh mt vng lp while vi iu kin lun lun l TRUE. Lnh lp vng for c tr gip bi cc cng c tng hp khi cc gi tr bin l tnh (static) ton cc. 8. Lnh qu trnh v lnh ng b. Cc lnh qu trnh cho kiu hnh vi mnh nht v l c s ca mi lnh ng thi. Mt lnh qu trnh bao gm 3 phn: danh sch ty chn, khai bo cc b v phn lnh tun t. Danh sch nhy. Mt qu trnh vi mt danh sch r rng tng ng vi mt qu trnh vi mt lnh ng b n, qu trnh c hot ng mi khi mt bin c xy ra trn mt tn hiu ca danh sch ny. Cc qu trnh nh sau: Process (A, B, C) danh sch cc bin c xem xt begin end process; Qu trnh trn cng c th tng ng vi: Process begin wait on A, B, C; end process; Khai bo cc b. Trong tt c cc khai bo c th c bn trong phn khai bo qu trnh, khai bo bin l cn thit, c th bao hm phn t nh. Tht ra, bin c th s dng trong hai cch khc nhau: Ging nh cc bin cc b, khng to ra phn cng no: Process (A, B, C) Variable VAR : BIT; Begin VAR : = B and C; S <= A and VAR; End process; no memorization for this and gate

-- before being read

C th vit hnh vi tng t bng cch thay th bin vi phn bn phi ca lnh gn: Process (A, B, C) Begin S <= A and B and C; End process;

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Bi ging Thit K H Thng S

Phn VHDL

ng dng ca bin c chp nhn bi cc cng c tng hp v khng c phn cng tng ng. Trong trng hp tng qut th gia 2 lnh ng b, nu mt bin lun c gn trc khi c c, th bin ny khng to ra bt k phn cng no. Khi thit k d liu di dng my trng thi. Process synchronous finite state machine with two states Type T_STATE is (STOP, GO); Variable STATE: T_STATE; Begin Wait until CLK=1; Case STATE is --variable STATE is read -- before being target of assignment when STOP => STATE:= GO; when GO => STATE:= STOP; end case; End process; V d ny ch ra rng vic c bin khng c ngha l c n trong phn bn phi ca php gn. Biu thc case, iu kin if hoc thng s in ca th tc hoc hm l cch khc c n. V th, gia hai lnh ng b, nu mt bin c c t nht mt ln trc khi c gn th bin ny to ra phn t nh. 9. Php gn tn hiu. Php gn tn hiu n gin. Dng n gin nht ca mt php gn tn hiu ng thi l nh ngha tn hiu ch nhn c cc gi tr ca tn hiu ngun mi ln mt s kin xy ra: S <= A; -- S c gn ti A bi phn cng Z <= 1; -- Tn hiu Z l mt hng s Cc php gn tn hiu chn la v c iu kin. Hai php gn tn hiu ng thi c nh ngha cho mc ch c iu kin ca tn hiu; php gn chn la v c iu kin. V d, S <= a when x = 1 else B when Y = 1 else C V d, nu A, B, C, X, Y c nh ngha nh l cc tn hiu, qu trnh tng l: Process (A, B, C, X, Y)

Begin
If X = 1 then S <= A; Elsif Y = 1 then S <= B; Else S <= C; End if; End process; Hai v d trn chng minh cc php gn tn hiu, vi cng c ny cho php ngi thit k c th m t cc thit k ca mnh r rng hn.

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Bi ging Thit K H Thng S 10. Component.

Phn VHDL

Mc ch ca lnh hp phn l s dng mt mu m t trc. y l cch chnh xy dng s phn th bc thit k. Trc khi sao chp, hp phn phi c khai bo cc b trong phn khai bo kin trc, hoc ring bit trong mt khi. S khai bo hp phn (component) nh ngha cch ni dy cc b, c th t tng qut hn so s khai bo thc th. Trong sut giai on cu hnh, mt s tn hiu c th v tri nu chng ch out hoc inout, hoc b b qua nu chng ch in vi gi tr mc nh. Khi sao mt hp phn, cc thng s tng thch chung phi c nh x n cc gi tr v cc cng ni vi tn hiu. V d, Architecture SYNTHESIZABLE of DRIVE is Signal ORDER: ORDER_TYPE; Signal CONTROL: BIT; Signal DATA_IN, DATA_OUT: BIT_VECTOR(1 to N); Component CTRL Port (C : in BIT; O: out BIT_VECTOR); End component; Component OPRT Port (O: in BIT_VECTOR; D1: in BIT_VECTOR; D0: out BIT_VECTOR); End component; -- specification configuration for CONTROLER : CTRL use entity WORD.CTRL(A); for OPERATING_PART:OPRT use entity WORD OPRT(A) generic map (N); begin -- two component instantiation statements. CONTROLER: CTRL port map(CONTROL, ORDER); OPERATIVE_PART: OPRT port map (ORDER, DATA_IN, DATA_OUT); End SYNTHESIZABLE; Cu hnh ch ra cp thc th/ kin trc c chn cho bn sao hp phn. Vi v d sau , hai lnh cu hnh c bit c th c thay th bi mt cu hnh c lp. Configuration C1 of DRIVER is For SYNTHESIZABLE For CONTROLER: CTRL use entity WORD.CTRL(A); End for; For OPERATIVE_PART: OPRT use entity WORK.OPRT(A); Generic map (N); End for; End for; End C1;

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Bi ging Thit K H Thng S 11. BLOCK. Cc lnh block c s dng cho cu trc lnh ng thi

Phn VHDL

V d, Signal A, B, C, D, E, F, G: BIT; Signal S; BIT_VECTOR(1 to 4); BLOCK_NAME : block Subtype TWO_BIT_TYPE is BIT_VECTOR(1 to 2); Signal V1, V2: TWO_BIT_TYPE; Begin V1 <= (A or C) &B; V2 <= E &(F and G); S <= V1 &V2; End block BLOCK_NAME; Di mt s iu kin, mt vi cng c tng hp c th dch lnh block nh mt cp ca tng hp. Trong trng hp ny nhn ca lnh khi c dng nh mt thng s cho cu trc lnh. ng dng khc ca lnh block l nh ngha phn lnh ng thi c iu khin bi clock. Trong trng hp ny phn bo v (guarded) c yu cu m t chnh xc tn hiu clock v iu kin lin quan ti n (cnh ln hoc xung). Hn na, php gn tn hiu ng thi c bo v v hot ng bi biu thc bo v. iu ny c ch ra trong v d sau, gi thit rng tn hiu clock l a gi tr. V d, B: block (not CLKstate and CLK = 0 and CLKlast_value =1) Signal R: BIT; Begin R <= guarded DATA(1); S <= guarded R ; -- Tn hiu S l DATA(1) c lm tr 1 chu k End block ng dng th 3 ca lnh block c dng trong mch 3 trng thi. Lin kt vi lnh khng ni (disconnect) v tn hiu resolved, php gn bo v c th nh ngha hnh vi ba trng thi. Khi iu kin bo v khng tho, tn hiu ch khng c ni. y l hnh vi mc nh ca mnh disconnect v c cho php nu kiu tn hiu ch c resolved. i vi tng hp, vn c gii quyt l gi tr cui cng khi tt c tn hiu ngun khng c ni. Gi tr ny ph thuc vo hai yu t: kt qu ca hm resolved tr v (khi di ca vector u vo l null) v loi tn hiu resolved (bus hoc register). Tm tt hnh vi ca loi tn hiu ny nh sau: Kt qu cui cng l gi tr c tr v bi hm resolved vi vector u vo null nu kiu tn hiu ch l bus. Kt qu cui cng l gi tr trc nu ch c mt tn hiu ngun v kiu ca tn hiu ngun l register.

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Bi ging Thit K H Thng S S b m ba trng thi c to ra bi lnh block:

Phn VHDL

Mt s cng c tng hp h tr tn hiu khng ni loi bus, th kt qu ca hm resolved tr v 'Z' m ha mc 3 trng thi. 12. Gi th tc ng thi. Th tc ng thi l th tc c gi t trong mt block hoc mt architechture. P (A, B, C); -- concurent procedure call; Tng ng vi: Process -- process equivalent to the previous concurent procedure call Begin -- C is assumed to be an actual parameter of module out. P(A, B, C); Wait on A, B; End process; Cho php dng lnh wait trong cc th tc ng thi. Trong tng hp, iu ny khng c h tr. Tht ra, lnh wait c nhiu tn hiu ch c cho php nu cc iu kin ng b l nh nhau. Thng s dng gi th tc ng thi khi mun c s linh ng v kh nng thch nghi. Th tc ng thi d dng s dng hn l bn sao hp phn (component), v khng i hi s khai bo v ch r. 13. Lnh GENERATE. Hai lnh generate c nh ngha l: lnh generate c iu kin v lnh generete lp. T quan im tng hp, lnh ny khng c h tr y . Trong giai on ch to, mt tp cc lnh ng thi tng ng c pht sinh. Lnh generate lp. Lnh ny c th lp li mt tp cc lnh ng thi (v d, lp li nhiu ln hp phn hoc gn cc tn hiu vector). Trong v d sau, cc hng s k1, k2 c th l cc thng s tng thch chung v phn cng tng ng s khng thay i. V d, Architecture A of E is Constant k1: NATURAL := 0; Constant k2: NATURAL := 3; Signal A, S: BIT_VECTOR(k1 to k2 ); GV: Nguyn Trng Hi Trang 25

Bi ging Thit K H Thng S Signal R: BIT_VECTOR (k1 +1 to k2 +1); Begin L: for J in k1 to k2 generate S(J) <= not A(J); R(J+1) <= A(j); End generate; End;

Phn VHDL

Trong v d sau, kin trc A v B l tng ng, kt qu tng hp cui cng ging nhau. Trong kin trc u tin A, kt qu l vector V c gn trong lnh tun t loop v trong kin trc th hai B, cc php gn tn hiu ng thi N c pht ra. Architecture A of E is Constant N: NATURAL := 3; Signal B: BIT_VECTOR(0 to N ); Signal R: BIT_VECTOR (1 to N); Begin Process (A, B) Begin For l in 1 to N loop V(l) <= F(l, A(l), B (N-1 + 1)); End loop; End process; End A; Architecture B of E is Constant N: NATURAL := 3; Signal B: BIT_VECTOR(0 to N ); Signal A,V: BIT_VECTOR (1 to N); Begin L: for l in 1 to N generate V(l) <= F(l, A(l), B (N-1 + 1)); End generate; End B; Lnh generate c iu kin. hon tt mt mu s dng cc lnh generate lp, c th c ch khi kim tra cc gi tr u tin cui cng ca ch s vng lp. Cc lnh generate iu kin c th c dng gii quyt vn ny. V d sau y minh ho tnh cht ny, s x l cc bn sao hp phn c th khc nhau (khng c, c mt, hoc nhiu bn sao). Entity E is Generic (N: NATURAL); Port (INPUT: in BIT; OUTPUT: out BIT; ); End E; Architecture A of E is Signal LOCAL: BIT_VECTOR (1 to N -1); Component M1 Port (l: in BIT; O: out BIT); End component; Begin GV: Nguyn Trng Hi Trang 26

Bi ging Thit K H Thng S

Phn VHDL

L1: if N = 0 generate OUTPUT <= INPUT; -- no component instantiation End generate ; L2: if N = 1 generate C1: M1 port map (INPUT, OUTPUT); -- only one instantiation End generate; L3: if N >= 2 generate -- other cases using the intermediate --LOCAL signal F: M1 port map (INPUT, LOCAL(1)); L4: for: in l to N-2 generate C :M1 port map (LOCAL(l), LOCAL(l+1)); End generate; End A; S dng tng thch chung (Generic). Thng s tng thch chung l tng qut ca khi nim hng s, ni rng trong sut giai on ch to cc gi tr ca chng phi c xc nh. V vy trc bc ny, i vi giai on dch, gi tr ca chng ch xc nh kiu m khng bit gi tr. Mt vi cng c tng hp h tr hn ch mt s kiu thng s tng thch chung (ch h tr kiu nguyn hoc kiu lit k). Tuy nhin, khng c l do thc s cho cc hn ch nh vy, ngoi tr khng h tr cho cu hnh. V d, vit mt mu chp nhn mt vector vi kch thc N, nh l u vo. N l thng s tng thch chung ca mu ny. Entity AND_N is Generic (N: POSITIVE); Port (Din : in BIT_VECTOR (1 to N); R: out BIT); End AND_N; Architecture A1 of AND_N is Signal INTER : BIT_VECTOR (1 to N); BEGIN INTER (1) <= Din (1); L: for l in 1 to N-1 generate INTER (l+1) <= (Din(l+1) and INTER (l)); End generate; R <= INTER(N); End A1; Architecture A2 of AND_N is BEGIN Process (Din) Variable RES: BIT; Begin RES := Din(1); for l in 2 to N loop RES:= RES and Din(l); End loop; R <= RES; End process; End A2;

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Bi ging Thit K H Thng S

Phn VHDL

V d, nhn dng mu cho trong chui bit tun t. Cc thng s tng thch chung l vector phi tm, v mt s bit dng bo s li (0: mu phi tm chnh xc nh m t, 1: ch sai khc 1 bit mi chp nhn,) Entity SEARCH_PATTERN is Generic(PATTERN: BIT_VECTOR; ERROR_NUMBER: NATURAL); Port ( CLK: in BIT; DATA: in BIT; RESET: in BIT; FOUND: out BIT); Begin Assert (PATTERN length >= ERROR_NUMBER) Report pattern length cannot be shorter than & the authorized error number Severity ERROR; End SEARCH_PATTERN; Architecture A of SEARCH_PATTERN is Subtype REG_TYPE is BIT_VECTOR (PATTERN range); Signal REG: REG_TYPE; Begin P_REG: process (DATA, CLK, RESET) Begin If RESET = 1 then REG <= REG_TYPE (others => 0); Elsif CLK =1 and CLKevent then REG <= REG(REGleft-1 downto REGright) & DATA; End if; End process; P_FOUND: process (REG) Variable CPT: NATURAL range 0 to ERROR_NUMBER +1; Begin CPT := 0; FOUND <= 0; For l in REGrange loop If PATTERN(l) /= REG(l) then CPT := CPT + 1; If CPT >= ERROR_NUMBER then FOUND <= 1; Exit; End if; End if; End loop; End process; End A; Trong cc v d trn cn ch nhng im sau: S dng cc lnh assert trong entity khng to ra phn cng. Lnh ny kim tra tnh nht qun gia cc gi tr thng s kh m t bi cc biu thc tnh (nh l cc khong trong cc kiu hoc biu thc kiu con). Trang 28

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Bi ging Thit K H Thng S

Phn VHDL

Kin trc bao gm hai qu trnh: Qu trnh u tin suy ra phn cng tun t vi mt tn hiu reset bt ng b, trong khi qu trnh th hai biu din mch t hp thun tu. Khai bo REG_TYPE c a ra hn ch tp hp cn li (others => '0') trong nhnh RESET bt ng b. Cc thc th tng thch chung cn c nh x n cc gi tr thng s to ra phn cng thc s. iu ny c th c lm trong bn sao hp phn hoc trong cu hnh, cc thng s tng thch chung c nh x n cc gi tr ca chng.

14. Php so snh. C hai loi so snh sau: Kim tra 2 i tng ging nhau. Bao gm cc hm (cng c gi cc ton t) bng ('=') v khng bng ('/='). Tt cc kiu tng hp c c th c so snh khi s dng cc ton t ny. Kim tra th bc ca hai i tng khi s dng cc ton t quan h, cc ton t ny c th c thc hin trn kiu bt k vi mt lnh quan h nh l cc kiu s nguyn, cc kiu lit k v kiu biu din m ASCII l qu ti i vi cc ton t so snh.

15. Cc ton t s hc. Sau cc ton t Boolean v cc php so snh, mt h quan trng khc l ton t s hc. Bn php ton c bn l: php cng, tr, nhn v chia. Kiu d liu thun tin nht thc hin cc php ton nh vy l kiu INTEGER v cc kiu con quan h vi n: NATURAL v POSITIVE. Cc ton t VHDL '+', '-', '*', v '/ 'c nh ngha trc v v vy c th c s dng m khng cn khai bo. iu ny cn thit cho ngi thit k hn ch kch thc cc i tng ca kiu INTEGER n gi tr ti tu. Nu ngi thit k khng lm cng vic ny, cng c tng hp s xc nh kch thc nh ngha ca kiu INTEGER trong khi (STD.STANDARD). V d, Signal l1, l2, SUM_l: INTEGER range 16 to 15; Signal N1, N2, SUM_N: INTEGER range 0 to 47; SUM_l <= l1 + l2; SUM_N <= N1 + N2; Trong v d ngn ny c mt vi ch thch v quy c m ho cc s. Tt c qu trnh tng hp nhm vo vic dch m ngun HDL thnh biu din nh phn. y, cc s c du l1, l2 v SUM_l c m ho dng b hai vi vic s dng 4 +1 bit. Mt khc, cc s khng du N1, N2 v SUM_N c m ha vi 6 bit (47<2**6-1). Tuy nhin, khng cn thit cho khong ca i tng ca kiu INTEGER l lu tha ca hai. Ton t nhn v chia phi c xc nh trc, c hai ton hng phi l cng kiu s nguyn hoc l kiu floating point. Kt qu cng phi cng kiu, ton t nhn cng c xc nh bi trng hp khi mt trong nhng ton hng l kiu vt l v ton hng th hai l kiu integer hoc real. Kt qu tr v l kiu vt l.

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Bi ging Thit K H Thng S

Phn VHDL

i vi ton t chia, chia mt gi tr vt l bi mt gi tr integer hoc real th c cho php, v kt qu tr v l kiu vt l. Php chia ca mt gi tr kiu vt l bi mt i tng khc cng kiu vt l v phn cn li ca n, mt gi tr nguyn coi nh mt kt qu. Ton t REM v MOD tc dng cho ton hng kiu integer v kt qu c cng mt kiu. Kt qu ca REM c biu hin ca ton hng th nht v n c xc nh nh sau: A rem B = A - (A / B) *B Kt qu ca ton t MOD l biu hin ton hng th hai, v n c xc nh nh sau: A mod B = A - B * N Sau y l nhng v d s dng ton t mod v rem: 7 mod 4 (-7) rem 4 7 mod (-4) -- kt qu = 3; -- kt qu = -3; -- kt qu = -1;

(-7) mod (-4) -- kt qu = 3; 16. Cc php dch v quay. Cc php tnh ny thng c thc hin trn cc i tng c biu din bit_vector. Hai loi php tnh dch v quay c th c phn bit : lun l v s hc. Php dch s hc c th c s dng cho php nhn (dch sang tri) hoc chia (dch sang phi) nu ton hng v phi ca mt php ton l mt lu tha ca 2. Mi mt ton t gi mt dy BIT hoc BOOLEAN nh mt ton hng tri v gi tr INTEGER nh ton hng phi, ng vai tr gii thch ton t. Nu gi tr INTEGER l m, hnh vi ngc nhau s xy ra. Ton t SLL (xoay tri lun l) v ton t SRL (xoay phi lun l) in vo nhng bit hu b vi left-operand-type'LEFT. Ton t SLA (xoay tri s hc) in vo nhng bit b hu b vi bit cc phi ca ton hng tri. Ton t SRA (xoay phi s hc ), in vo nhng phn t b hu b vi bit cc tri ca ton hng tri. V d, -- gi s tt c nhng ton hng tri u l BIT_VECTOR "1001010" sll2 is "0101000"; "1001010" srl3 is "0001001"; -filled with BIT'LEFT, which is '0'

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Bi ging Thit K H Thng S III. MT S V D THIT K CC MCH T HP V TUN T. on m chng trnh to mch dn knh 2 sang 1. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux2to1 IS PORT (w0, w1, s :IN STD_LOGIC; F: :OUT STD_LOGIC); END mux2to1; ARCHITECTURE behavior OF mux2to1 IS BEGIN WITH s SELECT F <= w0 WHEN 0, w1 WHEN OTHERS; END behavior; Mch so snh 4 bit.

Phn VHDL

Mch so snh 4 bit bao gm 8 bit ng vo, chia thnh 2 nhm, mi nhm 4 bit v c t tn l A v B. Kt qu ca php so snh c 3 trng hp: A bng B, A ln hn B v A nh hn B. Trong mch so snh ny kt qu ca php so snh ng vo s c biu th bng 3 bit ng ra cho 3 trng hp so snh gia A v B, AeqB(A equal B), AgtB(A greater B), AltB (A lighter B). M chng trnh ca mch so snh 4 bit c dng nh sau: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsgned.all; ENTITY compare IS PORT (A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AeqB, AgtB, AltB :OUT STD_LOGIC); END compare; ARCHITECTURE behavior OF compare IS BEGIN AeqB <= 1 WHEN A = B ELSE 0; AgtB <= 1 WHEN A > B ELSE 0; AltB <= 1 WHEN A = B ELSE 0; END behavior; Mch m ha u tin. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY priority IS PORT (w :IN STD_LOGIC_VECTOR(3 DOWNTO 0); y :OUT STD_LOGIC_VECTOR(1 DOWNTO 0); z :IN STD_LOGIC; END priority; ARCHITECTURE behavior OF priority IS

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Bi ging Thit K H Thng S BEGIN PROCESS (w) IF w(3) = 1 THEN y <= 11; ELSIF w(2) = 1 THEN y <= 10; ELSIF w(1) = 1 THEN y <= 01; ELSE y <= 00; END IF; END PROCESS; Z <=0 WHEN w = 0000 ELSE 1; w1 WHEN OTHERS; END behavior;

Phn VHDL

T on m trn ta c mch bao gm 4 ng vo, 3 ng ra, ty thuc vo cc gi tr ng vo m cc ng ra s c gi tr tng ng, mch m ha u tin ny, w(3) c mc u tin cao nht v w(0) c mc u tin thp nht, gi tr ng ra z ch bng 0 khi tt c cc ng vo bng 0, ngc li n lun bng 1. on mch trn s dng mnh if-thenelse, tuy nhin ngi thit k c th linh hot cc thit k bng nhng mnh khc, nhng phi m bo hot ng ca mch l ng nguyn tc. Mch gii m t 2 ng sang 4. Mch gii m t 2 ng sang 4 ng, bao gm 3 ng vo, l: w1, w2, En. Hai ng vo w1, w2 l hai ng vo s quyt nh gi tr cc ng ra, ng vo En l ng vo cho php(c th l mc '0' hoc mc '1' ty theo ngi thit k), khi ng vo En tch cc th cc ng ra mi c c gi tr tng ng vi cc ng vo. Trong on m VHDL cho mch gii m ny, cc ng ra c k hiu t y3 n y0. on m ca chng trnh c dng nh sau, trong on m ny, pht biu case c s dng. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0); En : IN STD_LOGIC; y :OUT STD_LOGIC_VECTOR(0 TO 3); END dec2to4; ARCHITECTURE behavior OF dec2to4 IS BEGIN PROCESS (w, En) BEGIN IF En = 1 THEN CASE w IS WHEN 00 => y <= 1000; WHEN 01 => y <= 0100; WHEN 10 => y <= 0010; WHEN OTHERS => y <= 0001; END CASE; ELSE y <= 0000; END IF; END PROCESS; END Behavior;

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Bi ging Thit K H Thng S Mch cht d liu.

Phn VHDL

Mch cht d liu c nhim v cht li d liu ng vo v a d liu ti ng ra, d liu ti ng ra s thay i tng ng vi d liu ng vo khi c mt xung tc ng. Ng ra s duy tr d liu m n nhn c ng vo trong sut qu trnh ch xung tc ng, khi khng c xung tc ng, nu ng vo c thay i th gi tr ng ra vn khng thay i gi tr m n nhn c ln nhn cui cng. on m VHDL cho mch cht c vit nh sau: LIBRARY IEEE; USE ieee.std_logic_1164.all; ENTITY flipflop IS Port ( D, clock : IN std_logic; Q : OUT std_logic); END flipflop; ARCHITECTURE bahavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL ClockEVENT AND Clock = 1; Q <= D; END PROCESS; END bahavior; Vi on m VHDL trn, ng vo d liu c tn l D, xung tc ng cnh , ng ra l Q, khi c mt xung cnh ln, ng ra Q s nhn gi tr t ng vo D v duy tr gi tr trong sut qu trnh ch mt xung k tip. on m trn c vit vi mt bit ng vo, mt bit ng ra, ngi thit k hon ton c th thay i s bit ng vo v s bit ng ra cho ph hp vi thit k ca mnh. on m trn c vit y cho mt mch cht, vi cc cng c tng hp v bin dch, ngi thit k c th ng dng n vo trong mch thc tin sau khi np vo IC. Mch to thanh ghi 8 bit. Thanh ghi trong mch s ng vai tr rt quan trng, cc thit k s hin i hu nh u phi s dng thanh ghi, VHDL cho php ngi thit k c th to ra thanh ghi vi s bit mong mun. Ngoi ra cn c th linh hot chng trong cc thit k ca mnh, thanh ghi thc t chnh l mt mch cht d liu. on m sau y vit cho thanh ghi 16 bit, trong thit k c s dng thng s tng thch chung generic. LIBRARY IEEE; USE ieee.std_logic_1164.all; ENTITY regn IS GENERIC ( N : INTEGER := 16); Port ( D, clock : IN std_logic_vector (N-1 DOWNTO 0); Reset, clock : IN std_logic; Q : OUT std_logic_vector (N-1 DOWNTO 0); END regn; ARCHITECTURE behavior OF regn IS BEGIN

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Bi ging Thit K H Thng S

Phn VHDL

PROCESS (Reset, clock) BEGIN IF Reset = 0 THEN Q <= (OTHERS => 0); ELSIF ClockEVENT AND Clock = 1 THEN Q <= D; END IF; END PROCESS; END behavior;

Mch m ln. Mch m ln hot ng theo nguyn tc: khi c mt xung tc ng ng vo, ng ra s thay i mt bit theo chiu hng m ln, mch m ln ngoi ng vo xung clock, ngi thit k cn c th to thm cc ng vo khc nh Reset, Enable to thm tnh linh hot ca mch. M VHDL cho mch m ln c vit nh sau: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY upcount IS Port ( Reset, Clock, En : IN std_logic; Q : OUT std_logic_vector (3 DOWNTO 0); END upcount; ARCHITECTURE behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS (Clock, Reset) BEGIN IF Reset = 0 THEN Count <= 0000; ELSIF ClockEVENT AND Clock = 1 THEN IF En = 1 THEN Count <= Count+ 1; ELSE Count <= Count; END IF; END IF; END PROCESS; Q <= Count; END behavior;

Mch m 3 trng thi. Mch m 3 trng thi gip mch thc t khi hot ng c th iu chnh ng ra trng thi thch hp cho s vn hnh ca mch, vi 3 trng thi, ngi thit k cc mch s s iu chnh mch sao cho hot ng tt hn v tit kim nng lng hn. M VHDL cho mch m 3 trng thi c vit nh sau:

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Bi ging Thit K H Thng S LIBRARY IEEE; USE ieee.std_logic_1164.all; ENTITY trin IS GENERIC ( N : INTEGER := 8); Port( X : IN std_logic_vector (N-1 DOWNTO 0); E : IN std_logic; F : OUT std_logic_vector (N-1 DOWNTO 0); END trin; ARCHITECTURE behavior OF trin IS BEGIN F <= (OTHERS => Z) WHEN E =0 ELSE X; END behavior; Xy dng my trng thi trong VHDL

Phn VHDL

library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; entity divby5 is port(x, clk : in std_logic; y : out std_logic); end divby5; architecture state_machine of divby5 is type StateType is (state0, state1, state2, state3, state4); signal p_s, n_s : StateType; begin fsm: process (p_s, x) begin case p_s is when state0 => y <= '0'; if x = '1' then n_s <= state1; else n_s <= state0; end if; when state1 => y <= '0' if x = '1' then n_s <= state3; else n_s <= state2

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Bi ging Thit K H Thng S end if; when state2 => if x = '1' then n_s <= state0; y <= '1'; else n_s <= state4; y <= '0'; end if; when state3 => y <= '1'; if x = '1' then n_s <= state2; else n_s <= state1; end if; when state4 => y <= '1'; if x = '1' then n_s <= state4; else n_s <= state3; end if; when others => n_s <= state0; end case end process fsm; state-clocked : process (clk) begin if rising_edge(clk) then p_s <= n_s; end if; end process state_clocked; end architecture state_machine;

Phn VHDL

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