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CODIGO: 20101005114
PRIMER CORTE
TAREA
Obtenga la descripcin VHDL para el circuito ALU mejorado
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity alu is
port (A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
S : in std_logic_vector (3 downto 0);
M : in std_logic;
Ci : in std_logic;
F : out std_logic_vector (3 downto 0);
AeqB : out std_logic;
Co : out std_logic);
end alu;
architecture Behavioral of alu
signal x : std_logic_vector (3
signal y : std_logic_vector (3
signal w : std_logic_vector (3
signal z : std_logic_vector (4
is
downto
downto
downto
downto
0);
0);
0);
0);
begin
process (S)
begin
if M='0' then
case (S) is
when "0000" =>
z<='0'&A;
when "0001" =>
z<='0'&A or B;
when "0010" =>
z<='0'&A or not B;
when "0011" =>
z<="11111";
when "0100" =>
x<=A;
y<=A and not B;
z<=x(3)&x+y;