ECE171 DigitalCircuits

Prof.MarkG.Faust MaseehCollegeofEngineering andComputerScience

Lecture10
Topics
Programmable g Logic g Devices(PLDs) ( )
PROMs PLAs PALsandGALs

PositiveandMixedLogic

TaxonomiesofICs
DesignMethodology
StandardComponents(SSI/MSI/LSI)
OfftheshelfComponents BasicUniversalBuildingBlocks(AND,OR,NAND,NOR)

ApplicationSpecificStandardParts(ASSP)
TargetSpecificApplicationArea,butnotCustomer e.g. e g PrinterController Controller,USBInterfaceIC, IC HDDI/F

ApplicationSpecificIC(ASIC)
CustomDesignofICTargetingSpecificMarket Fullcustom,standardcell,gatearrays e.g.ATI3DGraphicsEngine

Programmable g Logic g Devices( (PLD) )

Canbeusedtoimplementwidevarietydesigns e.g.FPGA(FieldProgrammableGateArrays)
3

PLDs
ProgrammableLogicDevices(PLDs)
PROM:ProgrammableReadOnlyMemories(1960s) PLA:ProgrammableLogicArrays[Signetics](1975) PAL:ProgrammableArrayLogic[MMI](1976) GAL:GenericArrayLogic CPLDs(ComplexPLDs) FPGA: FPGA Fi Field ldProgrammable P bl G Gate t Arrays A

PAL andGAL areregisteredtrademarksofLatticeLogic

AND/ORArrayArchitecture

Device type PROM PLA PAL/GAL

AND array Fixed at factory P Programmable bl Programmable

OR array Product term sharing Programmable Yes P Programmable bl Y Yes Fixed at factory No

ProgrammableSymbology

Fuses Fuses
Actualfuses,transistorcircuits,SRAMbased Volatileandnonvolatile Nonvolatile
UV(ultravioleterasable) EE(electrically ( l t i ll erasable) bl )

UniversalProgrammingUnit Fusemap
JEDECstandardformat Severalprogramsgenerate(MACHXL,ABEL,CUPL)
7

PLDImplementation
Schematic Capture Design D i Tools PROM PLA PAL/GAL CPLDs Fuse F Map

HDL

Universal Programmer og e

Tool and PLD vendors: Xilinx, Altera, Lattice

PROMs

Producttermsharing

PLAs

Producttermsharing

10

PALs/GALs

Noproducttermsharing

11

PALwithfunctionsharingor additionalinputs

12

AdvantagestoPLDs
Shortendesigntime
Rapidprototyping!

Rapiddesignchanges
Reprogrammable
Nomasks, masks jumpers, jumpers PCBtraces

DecreasePCBrealestate
Lessspacethanmultiplestandardlogicpackages

Improvereliability
Fewerpackages,fewerexternalinterconnects
13

PALxxyyzzNomenclature
xx zz y MaximumnumberofANDarrayinputs Maximumnumberofdedicatedoutputs Typeofoutputs Combinational H activehigh L activelow P programmable C complementary Registered R registered RP registered,withprogrammablepolarity Versatile V programmableascombinationalorregistered

14

NomenclatureExamples
PAL3H2 3i inputs 2outputs ActiveHoutputs PAL16L8 16inputs 8outputs ActiveL(0soffunction) PAL22V10 22inputs 10outputs ActiveLorH( (1sor0s) ) Registeredifdesired
15

PAL

16

GAL
EmulateanyPAL Reprogrammable
Fusesarenonvolatilememorycells

17

CPLDs ComplexPLDs

18

DesigningwithPROMs
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 0 0 0 1 1 Address 00000 00001 00010 00011 00100 00101 00110 00111 Data 0XXXXXXX 0XXXXXXX 1XXXXXXX 0XXXXXXX 0XXXXXXX 0XXXXXXX 1XXXXXXX 1XXXXXXX
19

F C B A

Example
Implement: aninverter(NOT) anORgate aNANDgate anXORgate With: aPROM aPLA aPAL

A 0 0 1 1

B 0 1 0 1

F1 1 1 0 0

F2 0 1 1 1

F3 1 1 1 0

F4 0 1 1 0

20

PROMImplementation
NOT,OR,NAND,XOR ABF1F2F3F4 001010 011111 100111 110100
Fusemap AddressData 0A 1F 27 34

21

PLAImplementation
NOT,OR,NAND,XOR ABF1F2F3F4 001010 011111 100111 110100

22

PLAImplementation
NOT,OR,NAND,XOR ABF1F2F3F4 001010 011111 100111 110100

23

PALImplementation
NOT,OR,NAND,XOR ABF1F2F3F4 001010 011111 100111 110100

24

LogicConventions
PositiveLogicConvention(PLC)
Signalsalwaysactivehigh(assertedhigh) Bubbleornegationindicatortoshowcomplementation

DirectPolarityIndication(DPI)
mixedlogicnotation Suffix S ffi (H)or(L)i indicates di active i hi high horactive i l low Polarityindicatororwedgetoindicateactivelow
PLC Signal Name A or A(H) B or B(H) DPI Signal Name A(H) or A(L) B(H) or B(L) Type of Signal Active High Active Low

25

IndicatorMatching

26

DetailedDPIExample

27

28

DatabookExamples

29