PRANJALI DESHMUKH

420 South 7th Street, Apt #2, San Jose CA 95112

Phone: 408-203-0245, Email: pranjali.0307@gmail.com

OBJECTIVE Seeking a Summer Internship Position.

Preferred areas of interest: ASIC, FPGA, SoC Design and verification
(Verilog and System Verilog)

EDUCATION Masters in Electrical Engineering Dec 2009

San Jose State University. (GPA 4.0)

Bachelors in Electronics and Communication Engineering May 2008

Visvesvaraya National Institute of Technology. Nagpur, India (CPI 8.71/10)

COURSEWORK Advanced Digital System Design and Synthesis, Digital Design for DSP and Communications,
SoC Design and verification with SystemVerilog, Microprocessor (8085, 8086), Linear Systems
Theory, Semiconductor Devices.

TECHNICAL MATLAB, Verilog, System Verilog, C.

SKILLS Assembly Language - 808x, 8051,
Tools Used - Xilinx ISE, Synopsys
Proficiency in MS Excel and Powerpoint

WORK Teaching Associate for Digital Design Course at SJSU. Aug 2008 – June 2009
EXPERIENCE - Instructing undergraduate digital design lab. The coursework involves basic
digital design, hardwiring projects, using Xilinx ISE for synthesis and simulation and
implementation of verilog codes on FPGA.

Summer Intern, Midas Communication Technologies, Chennai, India May -July 2007
- Developed a user configurable Ethernet controller card .
- Designed the Layout of the Ethernet Controller Card using ORCAD.
- Programmed the EEPROM and the Ethernet Controller IC using the IC programming kit.
- Used the DSO for verifying the output.

PROJECTS Design of a sequential shift-add multiplication circuit May 2009

Designed a sequential 8 bit multiplication circuit using shift-add methodology. The project
involved the area-delay analysis of the design with two different addition implementations –
Ripple Carry Adder and the Carry Look Ahead Adder. Verilog HDL was used for RTL coding of
the circuit. The simulation and synthesis was done using the Synopsys tool. Toshiba
tc240c.db_NOMIN25 library was used for synthesis.

Integration and Testing of an 8 x 8 ATM Switch May 2009

Incomplete softcores and testbenches of an 8 x 8 ATM switch were provided. The project
involved completing the softcores, integrating the functional modules and verifying the working
of the ATM switch. System verilog was used for coding and the testing and verification was done
using Synopsys.

Design of an 8 point FFT/IFFT IP based on the butterfly algorithm April 2009

Designed and verified an 8 point FFT/IFFT IP (fixed point model). The coding was done in
verilog and Xilinx was used for synthesis and simulation. The FFT/IFFT code was based on the
butterfly algorithm. The project also involved a comparative analysis with the floating point
Matlab model.

Design of an FIR filter March 2009

Designed a parameterizable FIR filter using a multiply and accumulate circuit. Verilog was used
for coding and the synthesis and simulation was done using the Xilinx tool.
 Design of a Multiply and Accumulate circuit Feb 2009
Designed a n x n MAC circuit using Xilinx coregen. 2C fractional format was used for the inputs.
Verilog HDL was used for RTL coding of the MAC and it was synthesized and simulated in
Xilinx. A 4 x 4 MAC circuit was implemented on Spartan 3 FPGA board.

Rough set approach to unsupervised neural network based pattern classifier Apr 2008
Developed a system for pattern classification based on Rough Neuro Hybrid Approach
using MATLAB

Micro Mouse – Auto Guided maze solving robot Dec 2006

Designed a 8051 Microcontroller based Micromouse capable of detecting obstacles and finding
its own path through an undefined maze

PUBLICATION “Rough Set Approach for Feature Reduction in Pattern Recognition through Unsupervised
Artificial Neural Network” IEEE Computer Society. July 2008

PAPER Presented a paper on “Applications of Neural Networks in Wireless Aug 2007

PRESENTATION Communication” at IEEE, ENCOMIUM, Jamia Millia Islamia University,
Delhi, India.