dce

2008

Thit k mch s vi HDL

Chng 4: Thit k lun l vi Verilog

Computer Engineering 2008

Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

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Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

Advanced Digital Design with the Verilog HDL chapter 4

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Gii thiu HDLs

HDLs (Hardware Description Languages)
Khng l mt ngn ng lp trnh Ta C Thm nhng chc nng m hnh ha, m phng chc nng Verilog vs. VHDL

Cc bc thit k bng HDL

M t mch t kha Bin dch kim tra c php (syntax) M phng kim tra chc nng ca mch
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Phng php lun thit k HDL

c t bng HDL
Cu trc/hnh vi ca mch

M phng
Kim tra: thit k ng yu cu cha? Chc nng: Hnh vi I/O Mc thanh ghil (Kin trcl) Mc lun l (Cng) Mc transistor (in t) Timing: Waveform Behavior

Tng hp
nh x c t thnh cc hin thc

Advanced Digital Design with the Verilog HDL chapter 4

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M hnh cu trc v m hnh hnh vi trong HDLs

Cu trc (Structural) ch ra cu trc phn cng tht s ca mch
Mc tru tng thp
Cc cng c bn (v d and, or, not) Cu trc phn cp thng qua cc module

Tng t lp trnh hp ng

Hnh vi (Behavioral) ch ra hot ng ca mch trn cc bits

Mc tru tng cao hn
Biu din bng cc biu thc (v d out = (a & b) | c)

Khng phi tt c cc c t hnh vi u tng hp c

Khng s dng: + - * / % > >= < <= >> <<
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Nhng nguy him trong thit k Verilog

Chng trnh tun t, b tng hp c th s phi thm nhiu chi tit phn cng
Cn mt b priority encoder

Nu chng trnh song song, c th c nhng trng thi khng xc nh

Nhiu khi always, khi no thc thi trc?

To ra nhiu trng thi khng d dnh trc

if (x == 1) out = 0; if (y == 1) out = 1; R-S latch! // else out retains previous state?

Khng tnh trc c s phn t phn cng

x = x + 1 c th cn RT NHIU phn t phn cng
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Lch s pht trin HDLs

ISP (circa 1977) d n nghin cu CMU (Carnegie Mellon University)
M phng nhng khng tng hp

Abel (circa 1983) c pht trin bi Data-I/O

Mc tiu dng cho cc thit b lun l kh lp trnh Khng tt cho my trng thi

Verilog (circa 1985) pht trin bi Gateway (now Cadence)

c t c a ra t 1985 Ban u c pht trin cho m phng, tng t C v Pascal Hiu qu v d vit Berkeley pht trin cng c tng hp vo thp nin 80 c IEEE chun ha
Verilog standardized (Verilog-1995 standard) Verilog-2001 standard

VHDL (circa 1987) - DoD sponsored standard

Da trn VHSIC pht trin bi DARPA Tng t nh Ada (Nhn mnh vo ti s dng v bo tr) Ng ngha m phng r rng Rt tng qut nhng di dng c IEEE chun ha
VHDL standardized (87 and 93)

Cu trc nghim ngt

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Verilog HDL
Verilog l mt ngn ng ln
C nhiu tnh nng cho tng hp v m phng phn cng C th biu din nhng c trng mc thp
Transistor

C th hot ng nh ngn ng lp trnh

Cu trc lp Cu trc iu khin.

Cc cng c m phng chp nhn ton b khi nim ca Verilog Cc cng c tng hp ch chp nhn mt phn cc khi nim ca Verilog Ch tp trung nghin cu mt phn
S dng mt mc thch hp Tp trung trn nhng cu trc tng hp c Tp trung trnh nhng cu trc gy li khi tng hp
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Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

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M hnh mch t hp
Mt m hnh Verilog ca mt mch tm tt cc m t chc nng bng gc nhn cu trc hay hnh vi trn nhng mi quan h ng vo-ng ra Mt m hnh cu trc l mt cu trc kt ni (netlist) cha
Cc cng Cc khi chc nng

Mt m hnh hnh vi l
Cc biu thc Boolean n gin M hnh chuyn i mc thanh ghi (Register Transfer Level RTL) Mt gii thut
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M hnh cu trc mch t hp

Thit k cu trc tng t nh to ra mt s (schematic) Schematic
Hnh biu din cng logic, Ng vo ra, Cc ng kt ni gia cc cng.

M hnh cu trc HDL

Danh sch cc cng c bn v kt ni gia chng Cc pht biu ch ra ng vo-ra

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Verilog primitives
Primitives l cc i tng c bn c th c s dng trong thit k 26 i tng chc nng c nh ngha trc
n-input and nand or nor xor xnor n-output 3-states buf not bufif0 bufif1 notif0 notif1 nand N1(y, a, b, c);
instance name (optional)
13

output kt thc pht biu

nand (y, a, b, c);

keyword name input

Ng ra l phn t u tin trong danh sch cc ng vo-ra

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M hnh cu trc trong Verilog

Module
Tn module v i theo module module_name (port_list); //Declarations: sau l danh sch cc ng vo-ra (port) reg, wire, parameter, input, output, inout, Danh sch c t loi port (input/output) function, task, Danh sch cc dy ni, //Statements: cc bin s dng bn Initial statement trong module (optional) Always statement Danh sch cc kt ni Module instantiation gia cc cng v cc Gate instantiation module khc bn trong UDP instantiation endmodule Continuous assignment
endmodule

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V d
Module ports port modes Internal wires Instantiated primitives

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V d khc

Computer Engineering 2008

Module ports
Giao tip vi mi trng bn ngoi Kiu ca port quyt nh chiu truyn d liu
Mt chiu (Unidirectional)
input output

Hai chiu (Bidirectional)

inout

Kiu ca module port phi c khai bo tng minh v khng cn theo th t xut hin trong port list
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Quy tt trong Verilog

Phn bit ch hoa thng (Case sensitive) Identifier: a-z, A-Z, 0-9, _ v $ Tn bin khng c bt u bng $ hay k s v c th ti a l 1024 k t Mt pht biu c kt thc bng ; Ch thch
// mt dng ch thch /**/ ch thch nhiu dng

C th vit cc pht biu trn mt dng hay nhiu dng

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Quy tt trong Verilog

Comments Lower case key words

identifiers

Thit k t trn xung (top-down)

H thng phc tp c phn chia thnh nhng n v chc nng nh hn
D thit k D kim tra

Cc module lng nhau trong Verilog h tr thit k t trn xung Module tham kho n module khc c gi l module cha, module c module khc tham kho n gi l module con su ca cc module lng nhau khng gii hn Mi module con phi c tn duy nht trong phm vi module cha (tr cc primitives)
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Binary full adder

M2 c_in a b sum w1 Half_adder w2 b c_out a M1 a sum Half_adder w3 b c_out
a b c_in

sum

c_out

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Thit k phn cp v t chc m ngun

Top-level module l module cp cao nht Module mc thp nht
Cha cc primitives Cc module khng phn chia nh hn

Tt c cc module c t trong mt hay nhiu tp tin khc nhau Cng c m phng tch hp cc module t cc tp tin
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Mch cng 16-bit ripple carry

a[15:0] b[15:0] c_in

Add_rca_16

c_out

sum[15:0]

a[15:12]

b[15:12]

a[11:8] b[11:8]

a[7:4]

b[7:4]

a[3:0]

b[3:0] c_in

Add_rca_4 c_out M4

Add_rca_4 M3 c_in12

Add_rca_4 M2 c_in8

Add_rca_4 M1 c_in4

sum[15:12]

sum[11:8]

sum[7:4]

sum[3:1]

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Cy phn cp mch cng 16-bit ripple carry

Add_rca_16 M1 Add_rca_4 ... M1 Add_full ... M1 Add_half M2 Add_rca_4 ... M2 Add_full M2 or M3 Add_rca_4 M3 Add_full ... M3 Add_half M4 Add_rca_4 ... M4 Add_full ...

or

xor

or

xor

Cy phn cp thit k mch cng 16 bit ripple carry

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Hin thc mch cng 16-bit ripple carry

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Vectors trong Verilog

Mt vector c biu din bng ngoc vung cha dy lin tip cc bit
sum[3:0] vector sum kch thc 4 bit

Bit tri nht l MSB Bit phi nht l LSB C th truy xut tng bit hay tng dy bit trong vector
sum[1] bit th 2 t phi sang ca sum sum[2:1] bit th 2 v 3 t phi sang ca sum

sum[4] gi tr x (khng xc nh) C th gn, so snh 2 vector vi nhau

Advanced Digital Design with the Verilog HDL chapter 4 26

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Cu trc lin kt (connectivity)

Wire
Thit lp cc lin kt gia cc i tng thit k Gi tr c quyt nh trong qu trnh m phng bi ci m n c ni vo

Kiu wire
Khai bo bng t kha wire
wire y_out

Cc bin s dng khng khai bo

Cc ng vo v ra mc nh l kiu wire (tr khi c khai bo kiu khc) Kt ni gia port hnh thc v port thc t
Theo th t trong danh sch cc port .tn_hnh_thc(tn_thc_t)
half_adder (.b(b), .Cout(w2), .a(a), .sum(w1));
Advanced Digital Design with the Verilog HDL chapter 4 27

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Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

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Cc gi tr lun l trong Verilog

a

Verilog s dng 4 gi tr lun l

1 True 0 False x Khng xc nh z tng tr cao
a 0

y b

x x z x x z x

z x z x

x z

s0 a s1 b out3 out4 out1 z z z z x z z x x x x

a
x x z

x x

b out5 out6 out2 x x x x

x x x

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Phng php lun kim tra

Kim tra mch thc hin ng chc nng
Kim tra ngu nhin phc tp v khng chnh xc Cn lp k hoch kim tra t m

Kim tra mch ln

Kim tra tt c cc trng hp
Mch cng 16 bit cn kim tra 223 trng hp Kim tra phn cp
half_adder full_adder Add_rca_4 cn kim tra 29 trng hp Chn mt s trng hp kim tra kt ni ca cc Add_rca_4 trong Add_rca_16

Kim tra theo chiu ngc so vi cy phn cp thit k

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M phng lun l
Xy dng cc testbench a vo mch v hin th dng sng ca kt qu B m phng
Kim tra m ngun Bo li M phng hnh vi ca mch thng qua cc tn hiu vo trong testbench
Khng c li c php
Stimulus Generator

unit_under_test (UUT)

Response Monitor

Ngi s dng hay phn mm

Mch thc thi ng kt qu

31

Advanced Digital Design with the Verilog HDL chapter 4

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Sinh tn hiu kim tra

Mt hnh vi (behavior)
Tp hp cc pht biu c thi trong qu trnh m phng (cc pht biu th tc) c gn gi tr m phng ging nh l c iu khin bi phn cng

Initial khai bo hnh vi mt lt (single-pass) begin end

Cha danh sch cc pht biu ca hnh vi Thi gian thc thi cc pht biu th tc ty thuc vo th t v thi gian tr truyn Cc pht biu c thc thi t trn xung, t tri sang phi

# <integer> <statement>
iu khin tr truyn Cc pht biu pha sau phi i

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Khun mu cho testbench

module t_module (); reg ; Tn module UUT Khai bo kiu thanh ghi cha gi tr cho cc bin ng vo ca UUT Khai bo kiu wire cho cc ng ra ca UUT Khai bo cc tham s Tn hiu c xut ra dng text Kt thc m phng sau thi gian time_out Xy dng cc tn hiu ng vo cho U1

wire ; parameter time_out = 100; UUT_name U1 (port_list); initial $monitor(); initial #time_out $finish initial begin end endmodule
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V d

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Kch thc s
Ch ra s lng bit dng lu tr s <num_of_bit> <base> <value>
8b1000_0001 3d2987 16h24ce 3o7

Nhng s khng khai bo kch thc c hiu dng integer (thng thng 32 bits) Mc nh cc s dng decimal Khng phn bit hoa thng trong khai bo s Du _ c b qua
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Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

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Thi gian tr truyn

Ng vo thay i ng ra khng thay i ngay lp t c Cc phn t c bn ca verilog c thi gian tr l 0 Cc vi mch thc t c sn xut da trn cc th vin chun c nh ngha trc Ngi thit k ch quan tm n tnh ng n ca mch S dng cc cng c tng hp hin thc cc thit k tha mn cc rng buc thi gian timescale <time_unit base>/<precision base>
Ch th bin dch Ch ra n v thi gian v chnh xc thi gian tr Phi c khai bo trc cc module
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V d `timescale

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Cc loi tr lan truyn

Tr qun tnh (inertial delay)
=1 tpd = 2 t=3 t=5

=4

tpd = 2

=4

Tr truyn (transport delay)

Gy ra do cc dy ni 0.033ns/1cm C th b qua wire #2 A_long_wire
39

t=3

t=5

Advanced Digital Design with the Verilog HDL chapter 4

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Ni dung chnh
Gii thiu v HDLs v verilog M hnh cu trc cho mch lun l t hp M phng lun l, kim chng thit k v phng php lun kim tra Thi gian tr truyn lan M hnh bng s tht cho mch lun l t hp v tun t vi Verilog

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Bng s tht trong Verilog

table Ng ra phi c kiu v hng (scalar) Dng k hiu ? thay cho 0, 1, x Th t cc ct trong <input_list> tng ng vi th t trong khai bo input ca module Mch t hp
<input_list>:<output>

Mch tun t
<input_list>:<state>:<output/next_state> Ng ra phi c khai bo kiu thanh ghi Dng k hiu - biu din ng ra khng thay i
Advanced Digital Design with the Verilog HDL chapter 4 41