Sheet 1 of 7

D-Type flip-flop (Toggle switch) The D-type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure 1 shows how the flip-flop (latch) can be made using 2-input logic circuits and Figure 2 shows the input and output waveforms The enable pin needs to be high for data to be fed to the outputs Q and Q bar. The output will only change on the falling edge or trailing edge of the applied clk input.

D
NAND
NAND

Enable

NAND

NAND

NOT

Latch
Figure 1 Simple D-type Flip-flop circuit The D type flip-flop has only one input (D for Data) apart from the clock. The INDETERMINATE state is avoided with this flip-flop. When the clock goes high, D (a 0 or a 1) is transferred to Q. When the clock goes low, Q remains unchanged. Q stores the data until the clock goes high again, when new data may be available.

Figure 2 Output waveforms of the D-type flip-flop. In this circuit the Q output changes state on the leading edge of the clock.

Sheet 2 of 7

At A, clock and data are high. Q goes high and stays high until B. At B, clock is high and data is low. Q goes low and stays low until C. At C, clock and data are both high. Q goes high and stays high until E. Q does not change during clock pulse D, because clock and data are still both high. At E, data is low, so Q goes low. At F, data is high so Q goes high. As with the other flip-flop circuits the operation can be improved to eliminate indeterminate states by adding a master latch. The circuit of the master-slave D-type flip-flop is shown in the ADS simulation setup shown in Figure 3. The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal. Each logic gate is made up of CMOS FETS (based on the 0.8um process) as described in the other tutorials on individual gates.

Sheet 3 of 7

DT

VtPulseDT SRC4 Vlow=0 V Vhigh=5 V Delay=25 usec Width=50 usec Period=100 usec Rout=1 Ohm

DT

Clk

VtPulseDT SRC2 Vlow=0 V Vhigh=5 V Delay=0 nsec Width=10 usec Period=20 usec Rout=1 Ohm

V
V_DC SRC1 Vdc=5.0 V

V
D
Vcc A
NAND

V
OUT

Vcc
NAND

V
Vcc
OUT

Vcc
NAND

A
NAND

buffered

OUT

buffered

OUT

buffered

Port D Num=1

buffered

NAND_buffered X8

NAND_buffered X7
V
A Vcc
NAND
A

NAND_buffered X2

NAND_buffered X4

Port Q Num=3

V
Vcc A
NAND

V
Vcc
NAND

V
Vcc A
NAND
OUT

OUT

OUT
B

Q_bar

buffered

OUT

buffered

buffered

Clk

buffered

Port Clk Num=1

NAND_buffered X9
Vcc IN

NAND_buffered X6

NAND_buffered X3

NAND_buffered X5

Port Q_bar Num=4

V
OUT

TRANSIENT
Tran Tran1 StopTime=150 usec MaxTimeStep=250

NOT

NOT X10

Figure 3 ADS simulation setup of the master-slave D-type flip-flop circuit. In this simaulation there are two square wave generators, the clock at 50KHz and the data (with a 25us delay) running at 10KHz. The simulation is a time-domain transient.

Sheet 4 of 7

The resulting simulation of the circuit shown in Figure 3 is shown in Figure 4.

D-type Flip-flop transitions occur on the falling of the Clk input

6 5 4

Clk ,V

3 2 1 0 -1

20

40

60

80

100

120

140

160

time, usec
6 5 4

D, V

3 2 1 0 -1

20

40

60

80

100

120

140

160

time, usec
6 5 4

Q, V

3 2 1 0 -1

20

40

60

80

100

120

140

160

time, usec
Figure 4 Simulation of the Master-slave D-type flip-flop. Note that the transitions occur on the falling edge of the applied clock signal+1/2 half clock cycle due to the slave action.

Sheet 5 of 7

The D-type flip-flop can be configured as a T-type or Toggle flip-flop. With this configuration the Q_bar output is connected to the D input and the signal/clock is connected to the clk input. The output of this flip-flop will have a frequency half that of the input. The ADS simulation of Figure 6 is shown below (Figure 5)

D-type Flip-flop transitions occur on the falling of the Clk input. This D-type is configured as a T-type toggle flip-flop
6 5 4

Clk ,V

3 2 1 0 -1 0 6 5 4 20 40 60 80 100 120 140 160

time, usec

Q, V

3 2 1 0 -1 0 20 40 60 80 100 120 140 160

time, usec
Figure 5 Simulation results of the D-type flip-flop configured as a T-type (Toggle) flipflop by connecting the D input to the Q_bar output. Such circuits are common in frequency prescalar circuits.

Sheet 6 of 7

V
Vcc A NAND B
buffered

V V
Vcc OUT A NAND B
buffered

Vcc A NAND B OUT

buffered

V
Vcc OUT A NAND B
buffered

OUT

Q Port Q Num=3

NAND_buffered X8

NAND_buffered X7 V
Vcc A NAND OUT B A

NAND_buffered X2

NAND_buffered X4 V
Vcc A NAND OUT

V
Vcc A NAND OUT

V
Vcc NAND
buffered

OUT

buffered

buffered

Clk

buffered

Port Clk Num=1 V V_DC SRC1 Vdc=5.0 V

NAND_buffered X9
Vcc IN

NAND_buffered X6 V

NAND_buffered X3

NAND_buffered X5

TRANSIENT
OUT NOT

NOT X10

Tran Tran1 StopTime=150 usec MaxTimeStep=250 nsec

DT

VtPulseDT SRC2 Vlow=0 V Vhigh=5 V Delay=0 nsec Width=10 usec Period=20 usec Rout=1 Ohm

Clk
Figure 6 Transient ADS simulation of a D-type Flip-Flop configured as a T-type flip-flop by connecting the D input to the Q_bar output.

Sheet 7 of 7

RF Application Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue eg mixer or digital eg D-type flip-flop. When a mixer is used the output consists of the sum and difference frequencies. In an analogue mixer a number of different frequencies are generated within the mixer namely the sum of the frequencies and the difference frequency (otherwise known as the beatnote) when both input frequencies are the same is the phase difference is zero and the beatnote is DC. Most PLL circuits now use digital phase detectors formed from two D-type flip-flops as shown in Figure 7.

Vhigh

D D type Flip-Flop Q1 Q1

F1

Clk

Clear Vhigh

NAND

D D type Flip-Flop Q2 Q2

F2

Clk

Figure 7 D-type flip-flop application - Phase frequency phase detector