ANNA UNIVERSITY : CHENNAI 600 025 B.E/B.

Tech Degree Examinations, Oct-Nov-2012 EC2207 DIGITAL ELECTRONICS LABORATORY

(B.E. ELECTRONICS AND COMMUNICATION ENGINEERING) Regulations - 2008 Time: 3 Hours Maximum Marks: 100

RESULTS FOR ALL POSSIBLE COMBINATIONS TO BE SHOWN TO ALL PROGRAMS 1. DESIGN and implement FULL ADDER WITH CARRY and FULL SUBTRACTOR 100 WITH BORROW using only NOR gates DESIGN and implement FULL ADDER WITH CARRY and FULL SUBTRACTOR 100 WITH BORROW using only NAND gates DESIGN OF 4-BIT BINARY ADDER USING IC7483 DESIGN OF 4-BIT BINARY SUBTRACTOR USING IC7483 DESIGN OF 4-BIT BCD ADDER USING IC7483 DESIGN OF 4-BIT BCD SUBTRACTOR USING IC7483 100 100 100 100

2.

3. 4. 5. 6. 7.

DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR 100 USING LOGIC GATES. DESIGN AND IMPLEMENTATION OF 8 BIT MAGNITUDE COMPARATOR 100 USING IC7485 DESIGN OF 16 BIT ODD PARITY CHECKER/GENERATOR USING IC74180 100 100

8.

9.

10. DESIGN OF 16 BIT EVEN PARITY CHECKER/GENERATOR USING IC74180 11. DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER using logic gates

(4X1) MULTIPLEXER AND (1 X4) 100

12. DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

100

13. CONSTRUNCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER 14. CONSTRUNCTION AND VERIFICATION OF 4 BIT MOD 10 RIPPLE COUNTER 15. CONSTRUNCTION AND VERIFICATION OF 4 BIT MOD 12 RIPPLE COUNTER

100 100 100

16. DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN 100 COUNTER 17. DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS-SISO AND PISO 100 using DFF 18. DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS-SIPO AND PIPO 100 USING JKFF 19. USING VERILOG HARDWARE DESCRIPTION LANGUAGE DESIGN and 100 implement FULL ADDER WITH CARRY and FULL SUBTRACTOR WITH BORROW using only NAND gates 20. USING VERILOG HARDWARE DESCRIPTION LANGUAGE DESIGN and 100 implement FULL ADDER WITH CARRY and FULL SUBTRACTOR WITH BORROW using only NOR gates 21. USING VERILOG HARDWARE DESCRIPTION LANGUAGE DESIGN AND 100 IMPLEMENTATION OF (8X1) MULTIPLEXER AND (1 X8) DEMULTIPLEXER using logic gates 22. USING VERILOG HARDWARE DESCRIPTION LANGUAGE 100 CONSTRUNCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER 23. USING VERILOG HARDWARE DESCRIPTION LANGUAGE 100 CONSTRUNCTION AND VERIFICATION OF 4 BIT MOD 10 RIPPLE COUNTER 24. USING VERILOG HARDWARE DESCRIPTION LANGUAGE 100 CONSTRUNCTION AND VERIFICATION OF 4 BIT MOD 12 RIPPLE COUNTER 25. USING VERILOG HARDWARE DESCRIPTION LANGUAGE DESIGN AND 100 IMPLEMENTATION OF SHIFT REGISTERS-SISO AND SIPO using SRFF 26. USING VERILOG HARDWARE DESCRIPTION LANGUAGE DESIGN AND 100 IMPLEMENTATION OF SHIFT REGISTERS-PISOAND PIPO USING TFF