A Direct Digital Frequency Synthesizer Utilizing Quasi-Linear Interpolation Method

Ashkan Ashrafi
Department of Electrical and Computer Engineering The University of Alabama in HuntsvilIe ashkan@,ieee.org

Reza Adhami
Department of Electrical and Computer Engineering The University of Alabama in Huntsville rradhami@,ene.uah .edu

Key Words: Direct Digital Frequency Synthesizer, Sinusoidal SignaIs Generation, Polynomial Interpolation A b s t r a c b In this paper, a novel direct digital frequency synthesizer (DDFS) is introduced in which a combination of linear and even piecewise parabolic polynomial interpolation (EPW) is used to interpolate the first quadrant of a cosine signal. An appropriate combination of these two methods is employed to maximize the spurious free dynamic range and reduce the complexity of the entire system. The even parabolic polynomial can be treated as a linear interpolation with respect to the squared of the accumulator's output, thus the proposed system is called Quasi Linear Interpolation (QLIP) direct digital frequency synthesizer.
1. INTRODUCTION

Direct digital fkquency synthesizers (DDFS) are an important part of modern communication systems. They are employed to create accurate sinusoidal signal for modulation and demodulation. The amplitude of a sinusoidal signal is digitally stored in a ROM and they are consecutively fetched by the output of an at:cumulator, which feeds the address line of the ROM [l]. Fig.] shows the structure of a DDFS. The input of the accumulator and its word-length determine the output frequency and the output frequency resolution, respectively. The ROM hnctions as a phase to sine amplitude converter that generates sine amplitudes by using the digital ramp sequence generated by the accumulator. The frequency of the output sinusoidal signal is

deteriorated. by increasing the ROM size, which is used to enhance the resolution and spurious free dynamic range (SFDR) of the output sinusoidal signal. The SFDR is defined as the ratio of the fundamental harmonic magnitude to the maximum spur magnitude. A basic method to reduce the ROM size of a DDFS is to truncate the accumulator's word-length from L to W where W < L . This truncation causes a significant reduction in the SFDR of the output signal. The SFDR of the resultant structure is calculated in [2] and i s given by SFDR t; 6W dBc . (21 Moreover, the output quantization signal-to-noise ratio (QSNR) is given by [ l ] QSNR = 6.020 + 1.76 dBc, (3) Truncating the accumulator's output cannot significantly reduce the ROM size and firther reduction i s necessary if design of a low power DDFS is to be attempted. The most obvious method to reduce the ROM size is to use the quarter wave symmetry of a sinusoidal signal. In this method, only the information of the first quadrant of a sinusoidal signal needs to be stored in a ROM. The other quadrants can be produced by using the information of the first quadrant 131. Several other methods have also been introduced to further reduce the ROM size such as CORDIC method [3] and polynomial interpolation methods [4]-[7]. In all the aforementioned methods, the quarter wave symmetry of sinusoidal signals is aIso employed to further reduce the ROM size.

r-------------,
where F,, L , f& and f,,, are the input of the accumulator, the accumulator word-length, the clock frequency and the output frequency, respectively [13. A DDFS has two important features. The first and the most important feature of a DDFS is its capability to tune the frequency of the output sinusoidal signal with a very small pitch. The other feature of a DDFS is its fast frequency hopping. The only drawbacks of DDFS systems are their high power consumption and low maximum clock fiequency due to the very large ROM. These drawbacks are further

Accumulator

Fig.1: Block diagram of a DDFS system

0-7803-8808-9/05/$20.00 82005 IEEE

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In this paper, a novel method to design a phase to sine amplitude converter for direct digital frequency synthesizers is introduced. This method is based on a combination of EPIP and linear polynomial interpolation of a cosine signal because a cosine signal is very close to a parabola at the peak, but it is closer to a line at zero crossing points. An appropriate combination has been found to achieve the highest possible SFDR. A MATLAB simulation is performed to compare the proposed method with the best linear interpolation method introduced in [SI.
11. THE QLIP METHOD

method to calculate the coefficients) for x = 0 (linear) x = 1 (EPIP) and x = 3m /4(QLIP) are calculated by MATLAB and depicted in Fig.4. It can be seen in Fig. 4 that there is around l2dBc improvement in SFDR between the piecewise linear interpolation and EPIP methods. Since the maximum achievable SFDR from a piecewise linear interpolation method ( x = O ) is 16s' + 1 [XI, consequently, the maximum achievable SFDR f r o m the EPIP method ( x = 1 ) can be empirically approximated by 64s2 + I . Moreover, Fig. 4 shows that in order to achieve a certain SFDR we need half the number of sections in EPIP than piecewise linear interpolation and that leads to a simpler digital circuitcy. Fig.4 also shows that the QLlP method ( x = 3m / 4 ) has 6dBc improvement over the EPIP method ( x = 1) and 18dBc improvement over the h e a r interpolation ( x = 0 ) method which makes it more appropriate in terms of spectral purity.

Let the first quadrant ( O < @ l l ) of a cosine signal c o s ( d / 2) be divided into m = 2' segments, where s is a positive integer number and let the parameter x be the position where the interpolation method should be changed i.e., for k < x the cosine signal is interpolated by even parabolic polynomials Co,k -Clto' and for k > x cosine signal is interpolated by line segments C O ,~C&'. Fig. 2 illustrates the QLIP method. The least squares method is employed to find the and c,,k. Then, MATLAB is used to coeEcients C O , ~ calculate the SFDR of the QLIP method for different values of x and m using the evaluated coefficients. Fig. 3 shows the results calculated by MATLAB. It can be seen in Fig. 3 that for 4 1 m 1 3 2 the best SFDR is achieved when x = 3m 14 .Therefore, the output signal can be represented by

4
llQ

i d;

..
10

12 12
I

ab

3 L

Fig. 3: Variation of the SFDR versus X for different number of section.

100
90

: e

Z Q

IO
60

60
40

To compare the QLIP method with piecewise linear interpolation and EPIP methods, the variations of SFDR versus the number of sections m (utilizing the least squares

~ ~ ( =c 8 ) ~- c,,,B* , ~ ,
Pk(#)=CO,k

15 k I3m/4 3m/4+1<kIm

(4)

30

4 B 16 NMtberofSegmentqm

32

Ffg. 4: Comparison between the SFDR of the EPIP, piece-wise linear plynormal interpolationmethod and the QLIP method.

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111. DIGITAL REALIZATION

To realize the method in a digital circuitry, signal (4) should be digitized. By considering the phase word-length equal to W , the output word-length equal to D and employing the quarter wave symmetry [6]
@=-

j=O

n O I n 1 2Af -1, 2M '

M=W-2,

(5 1

the digitized version of (4) will be

where n n = ( n 2 , - M ) and {a,-b> means that the binary number n has been shifted to the right by 6 bits and the result is truncated to an integer number. Then the output is

The complexity of the linear interpolation section

3n44 + 1 5 k 5 m can be further reduced. This section can be

represented by the following discrete signal

By choosing W = D + 2 and knowing the fact that M = W - 2 then D - M , t h u s

where means the integer part of x , In fact, to digitize the coefficients we should multiply (4)by 2 D - 1 but for the sake of simplicity (having a cancellation with z M ) the multiplicand has been chosen to be 2O. Since the coefficients will be changed further both by (8) and optimization method, this assumption will not have a devastating effect. To eliminate the requirement of second multiplier, the coefficients Cl,,+ are approximated by a summation o f integer powers o f two, which can be realized by logical shifts

1 .

where

j=O

For m = 4,8 the value of r is equal to two and for = 16 it is equal to three. For greater values of m , the

digital system becomes too complicated; therefore, they would be realized as a very complicated system, which is not appropriate. The term t 1 * / 2 ~ can be realized by a fixedlength digital multiplier whose input and output word-lengths are identical. Since the output word-length is D , the output generated by (7) has to be truncated to D - 1 because the first quadrant has half of the amplitude of the full cosine signal. Therefore, the behavioral model of the entire system can be represented by the following formula

Since h,, hl,A are negative for these segments, then wi is significantly less than wk.Using this technique, the ROM size and bits involved in the addresses are dramatically reduced. Moreover, simulation shows that the input word-lengths of the squarer can be reduced by 2-bits without any significant deterioration in the output SFDR which leads to a less complex system. Fig. 5 illustrates the block diagram of the entire digital system of the QLIP method. The above approximation deteriorates the SFDR of the output signal compared to the ideal case. To restore the theoretical SFDR of the output signal, the Nelder-Mead nonlinear simplex optimization method [91 is used to change the digitized values of CO,,+ in order to maximize the SFDR. The result of the simulation is compared with the ideal QLIP in Fig. 6 that shows the optimization restores the SFDR close to the theoretical values. Table-1 shows the optimized coefficients for W=12, P I O , m=4.
a - .

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Fig3

Block diagram o f the entire DDFS system based on QLIP interpoIation method.

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Although the SFDR improvement is a very good achievement for the QLIP method, the real comparison with the piecewise linear interpolation method should be made having the information of the realized corresponding VLSI chip. Future research is needed to incorporate the QLW system in a VLSI chip to evaluate the complexity, power consumption and maximum clock frequency of the QLlP system and make a realistic comparison with the piecewise linear interpolation method.

V.REFERENCES
Fig. 6: Comparison between the ideal and the digitized QLIP.

IV. DISCUSSION AND CONCLUSION

A Quasi Linear Interpolation (QLIP) method to design a DDFS system based on a combination of a piecewise even parabolic and linear poIynomia1 interpolations, is introduced in this paper. The digital realization o f the proposed method is formulated based on the linear interpolation method given in [SI. It is shown that the SFDR of the proposed method is lSdBc better than the h e a r interpolation method introduced in [SI. Moreover, the complexity of the system is reduced because only half of the segments are required to achieve the same SFDR as the linear interpolation method given in [PI. This leads to half the number of multiplexers and a simpler adder in Fig. 5. However, in the QLIP method (compared to the linear interpolation method [8]) an extra multiplier is needed to generate the squared of the accumulators output. This extra niultipliet makes the proposed system slightly more complex.
Table-1: The cmfidencs of the QLIP method for m=4

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on Ultrasonic, Ferroelectric and Fregueng Control, Vol. 4 4 , No.2, March 1997. A.M. Sodagar & G.R. Lahiji, Mapping from Phase to sine-amplitude in direct digital frequency synthesizers using parabolic approximation, IEEE Transactions on Circuit and Systems. II, Vol. 47, No. 12, Dec.2000. D. De Caro, E. Nappli, and A.C.M. Strollo,Direct Digital Frequency Synthesizers with Polynomial Hypafolding Technique, IEEE ?runs. Circuit & Sysr. Part-II, Vo1.51, pp 337-344, July 2004. A. Ashrafi, Z .Pan, R. Adhami, and B.E. Wells, A Novel ROM-less Direct Digital Frequency Synthesizer Based on Chebyshev Polynomial Interpolation, Proceedings o f The 36h Southeastern Symposium on System Theory, SSSTU4, pp 393-397, March 2004. A. Ashrafi, R. Adhami, L. Joiner, and P. Kaveh, Arbitrary Waveform DDFS Utilizing Chebyshev Polynomials Interpolation, IEEE Trans. on Circuit & Syst.Purt- I, vO1.51, pp 1468-1475. Aug. 2004. J.M.P. Langlois, and D. AI-Khalili, Novel Approach to the Design of Direct Digital Frequency Synthesizers Based on Linear Interpolation, IEEE Trans. on Circuit & Syst. Part-II, Vo1.50, No.9, Sep. 2003. J.A. Nelder and R. Mead, A Simplex Method for Function Minimization, The Computer Journal, Vol. 7 , N0.4, pp 308-313, Jan. 1965.

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[5]

[6]

[7]

[g]

[9]

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