IMPLEMENTATION OF DIRECT DIGITAL SYNTHESIZER AD9850 USING ARDUINO UNO

B.Tech. Project Report

V.Mounika G.Ravali K.Sindhura V.Sindu

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090 2013

IMPLEMENTATION OF DIRECT DIGITAL SYNTHESIZER AD9850 USING ARDUINO UNO
Project Report Submitted in Partial Fulfillment of the Requirements for the Degree of

Bachelor of Technology In Electronics and Communication Engineering By

V.Mounika G.Ravali K.Sindhura V.Sindu

(09241A0484) (09241A0495) (09241A04A3) (09241A04A4)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY
(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090 2013

Department of Electronics and Communication Engineering Gokaraju Rangaraju Institute of Engineering and Technology
(Affiliated to Jawaharlal Nehru Technological University)

Hyderabad 500 090 2013

Certificate
This is to certify that this project report entitled ―Implementation of direct digital synthesizer AD9850 using arduino Uno‖ by V.Mounika (Roll No.09241A0484), G.Ravali (Roll No.09241A0495),K.Sindhura (Roll No.09241A04A3) and V.Sindu (Roll No. 09241A04A4), submitted in partial fulfillment of the requirements for the degree of Bachelor of Technology in Electronics and Communication Engineering of the Jawaharlal Nehru Technological University, Hyderabad, during the academic year 2009-13, is a bonafide record of work carried out under our guidance and supervision. The results embodied in this report have not been submitted to any other University or Institution for the award of any degree or diploma.

(Guide) N.Ome Assistant Professor

(External Examiner)

(Head of Department) Ravi Billa

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ACKNOWLEDGMENT

It is a pleasure to express thanks to Prof. N.Ome for the encouragement and guidance throughout the course of this project. We also express our sincere thanks to prof. Ravi Billa Head of the Department, G.R.I.E.T for extending his help. We wish to thank Mr. K.N.B. Kumar, Mr. Anantha Radhanand and Mr. V.H. Raju for their valuable suggestions during the course of our project. We wish to express our profound sense of gratitude to Prof. P.S.Raju, Director ,G.R.I.E.T for his encouragement and for all facilities to complete this project. Finally we express our sincere gratitude to all the members of faculty and my friends who contributed their valuable advice and helped to complete the project successfully.

V.Mounika

________________________

G.Ravali

________________________

K.Sindhura

________________________

V.Sindu

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Abstract
Our project deals with the implementation of direct digital synthesizer AD9850 using Arduino. A digitally-controlled method of generating multiple frequencies from a reference frequency source is called Direct Digital Synthesis (DDS).The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance D/A converter and comparator to form a complete, digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/phase programmable, analog output sine wave. This sine wave can be used directly as a frequency source, or it can be converted to a square wave for agile-clock generator applications. The AD9850‘s innovative high speed DDS core provides a 32bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz for a 125 MHz reference clock input. The AD9850‘s circuit architecture allows the generation of output frequencies which can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. Block Diagram

Hardware Required: ARDUINO UNO,DDS module,Protoshield Software Required: Arduino

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………3 2.1 1..3 FREQUENCY/HOPPING CAPABILITY OF DDS………………………………………….4 REFERENCE CLOCK CONSIDERATIONS………………………………………………….………….…10 2..3 SIGNIFICANCE ………………………………….……..3.1 OVERVIEW………………….4 PHASE ACCUMULATOR………………………………………….7 2..…………………………….3..…3 2..12 iv ..5 CONCLUSION…………………………………..2 DDS DISADVANTAGES……………………………………………..3 THEORY OF OPERATION…………………………………………..………….………………….….…………………………………….………2 CHAPTER-2:DIRECT DIGITAL SYNTHESIZE……………………………………….1..…1 1....1 THE DDS CONTROL INTERFACE……………………….1...1.………………....…1 1.……………………………………………………….4 OVERVIEW…………………………………….2 METHODOLOGY………………….3.………..……………..………3 2.……………3 2..3 THE EFFECT OF TRUNCATING THE PHASE ACCUMULATOR ON SPURIOUS PERFORMANCE…………………...1 FUNDEMENTALS OF DIGITAL TECHNOLOGY……………………….…….2 UNDERSTANDING THE SAMPLE OUTPUT OF DDS DEVICE……………………7 2.2 PROFILE REGISTERS………………………………………..……1 1.1..……………3 2.…………………………..10 2..……1 1..10 2.CONTENTS LIST OF FIGURES CHAPTER-1:INTRODUCTION………………………………………………………….………………………………………….1 MOTIVATION………….9 2..

13 CHAPTER-3:AD9850…………………………………………………………………………………………………………………14 3..3 OPERATION……………………………………………………………………….......1...............……..14 3.7 AB9850 EVALUATION BOARDS INSTRUCTION.....26 4.....…..1 ARDUINO PIN DESCRIPTION…………………………………………………………………………..24 3..………23 3............8 CONCLUSION....24 3.28 4...1 CHARACTERISTICS……………………………………………………………………………………..25 3.........…………………………..2 SETUP……………………………………………………......................……...2 PIN DESCRIPTION.....………………………17 3..............4 PROGRAMMING……………………………………………………………..24 3..…………………..5 PCB LAYOUT INFORMATION………………………….2 SCHEMATIC & REFERENCE DESIGN……………………………………………………….......….....4 PROGRAMMING THE AD9850………………………………….1.……………….……19 3.1 REQUIRED HARDWARE/SOFTWARE…………………………….....7....………………………25 3.28 4...............………………………..1....6 EVALUATION BOARDS.7......3 THEORY OF OPERATION AND APPLICATION……………….26 4..........1 GENERAL DESCRIPTION……………………………………………………………………………….5 CONCLUSION………………........3 COMMUNICATION……………………………………………………………30 4......…….......7..…………………………………………………………….........15 3.....30 v .….......2......…………………………………………25 CHAPTER4:ARDUINO……………………………………………………………………….1......

5 AUTOMATIC (SOFTWARE) RESET…………………………………….……….34 CHAPTER-6 : RESULTS…………………………………………………………………………….38 7.……………………………………………………………...1.1.……………………......37 CHAPTER-7:APPLICATIONS AND FUTURE SCOPE…..…………32 5.2 CONCLUSION……………………………………………….38 CHRONOLOGICAL BIBLIOGRAPHY…………………………………………………………….…….………………………………...4..5 CONCLUSION…………….39 APPENDIX-A…………………………………………………………………………………………40 vi .…………………………………………………….31 CHAPTER-5 : IMPLEMENTATION OF DDS AD9850………………………………….……………….33 5.2 FUTURESCOPE…………………………………………………………………….………………………………………………..32 5.……30 4.1 CONCLUSION………….34 5.……………………………………………….……...6 USB OVERCURRENT PROTECTION…………………………………………31 4..1 APPLICATIONS……...……….……..2 CONCLUSION…………………………..32 5.1 BOCK DIAGRAM……………………………………………….1...……………………….……...…………………………………………………………….7 PHYSICAL CHARACTERISTICS………………………………………………31 4.35 6.2 ALGORITHM……………………………………………………………………………………….3 FLOW CHART………………………………………………………………….38 7...38 7.4 PROGRAM……………………………………………………………………….

APPENDIX-B…………………………………………………………………………………………42 vii .

......7 Figure 2.....2:Protoshield…………………………………………………………………………………...1:DDS Module…………………………………………………………………………………35 Figure 6...………………..12 Figure 3...7:Reference clock edge uncertainty adversely effects DDS output signal quality…………......8 Figure 2......22 Figure 3....11 Figure 2..........20 Figure 3.…4 Figure 2...........LIST OF FIGURES Figure 2...…………......6:Parallel load power-Down sequence/Internal operation………….....22 Figure 3........18 Figure 3....21 Figure 3.......10:Serial Load Frequency/Phase Update Sequence……………………………....11:Serial Load Power-Down Sequence………………….4 Figure 2..............3:Output spectrum of a sampled signal…………………………………………………......................…....5:Spectral analysis of Sampled output………………………………………………………..............22 Figure 3...................23 Figure 3..................................……............3:ARDUINO UNO Board……………………………………………………..............12:AD9850 I/O Equivalent Circuits…………………………......4:Parallel Load Frequency/Control word functional assignment……....................1:Pin discription………………………………………………………………....15 Figure 3.21 Figure 3..........2:Frequency-tunable DDS system…………………………………………….................................27 Figure 6...............................7:Parallel load power-Up sequence/Internal operation…………………………………................................……21 Figure 3............36 Figure 6....5:Master Reset Timing Sequence……………………………………………………………........…6 Figure 2.....................2:Basic block diagram of DDS and Signal flow of AD9850…………………………………18 Figure 3....3:Signal flow through the DDS architecture…………………………………………….................1:ARDUINO UNO Pin Description..............6:Phase truncation Error and the phase wheel…………………………………….4:Computation of the Phase register…………………………………................36 Figure 6...............9:Pins 2 to 4 connections for Default Serial Mode Operation…………………………………....35 Figure 6...4:Interfacing of modules……………………………………………………………………….........1:Simple direct digital synthesizer………………………………………….....8:Serial Load enable sequence……………………………….23 Figure 4..5:Final Output waveform………………………………………………………………………37 viii ........

1.  Fast settling time. DDS technology was used only in high-end applications as it was costly. difficult to implement.2 Methodology We implemented this project using Arduino Uno. and required a discrete high speed D/A converter.  This is an important step towards a "software-radio" which can be used in various systems. Due to improved Integrated Circuit (IC) technologies. we discuss the fundamentals to understand DDS technology i. 1. they now present a viable alternative to analog based Phase Locked Loop (PLL) based technology for generating agile analog output frequency in consumer synthesizer applications. frequency hopping and data rates are easily achieved.e. continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Previously. protoshield a DDS module with the code written on arduino software. sub-Hertz frequency resolution. modulation formats. The DDS could be applied in the modulator or demodulator in the communication systems.4 Overview In chapter two.Chapter 1 INTRODUCTION 1. we describe the 1 . These combined characteristics have made the technology popular in various military radar and communication systems. the basic theory of operation involved.3 Significance  A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. adaptive channel bandwidths. In chapter three. Other inherent attributes include the ability to tune with extremely fine frequency and phase resolution and to rapidly hop between frequencies. 1.  By programming the DDS..1 Motivation A major advantage of a Direct Digital Synthesizer (DDS) is that its output frequency. phase and amplitude can be precisely and rapidly manipulated under digital processor control.

Arduino. The implementation of the project and the results are discussed in chapter five and six respectively.5 Conclusion The motivation.signal flow. programming the AD9850 and other necessary information related to its operation. Finally. the easy-to-use hardware and software is discussed in chapter four. where several applications and future scope of this project are discussed. we end up with chapter seven. methodology used in the implementing the project. significance and the overview is discussed in this chapter 2 . 1.

1.1.1. a direct digital synthesizer can be implemented from a precision reference clock. a programmable read only memory (PROM). Today‘s cost-competitive. an address counter. For many applications. highperformance. DDS afford unparalleled matching and control of I and Q synthesized outputs. the DDS solution holds some distinct advantages over the equivalent agile analog frequency synthesizer employing PLL circuitry. 3 . all under complete digital control. high-performance.and phase-tunable output signal referenced to a fixedfrequency precision clock source. In essence. in many cases.3Theory of Operation In its simplest form. Extremely fast ―hopping speed‖ in tuning output frequency (or phase). 2. and minutely optimized. 2. The digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled.1.1 Overview Direct Digital Synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency. phaseContinuous frequency hops with no over/undershoot or analog-related loop setting time anomalies The DDS digital architecture eliminates the need for the manual system tuning and tweaking associated with component aging and temperature drift in analog synthesizer solutions. When utilized as a quadrature synthesizer. the reference clock frequency is ―divided down‖ in DDS architecture by the scaling factor set forth in a programmable binary tuning word.Chapter 2 DIRECT DIGITAL SYNTHESIZER 2. The tuning word is typically 24-48 bits long which enables a DDS implementation to provide superior output frequency tuning resolution. and small package-sized DDS products are fast becoming an alternative to traditional frequency-agile analog synthesizer solutions. The integration of a high-speed. and a D/a converter. Fundamentals of DDS Technology 2. functionally-integrated. D/A converter and DDS architecture onto a single chip (forming what is commonly known as a Complete-DDS solution) enabled this technology to target a wider range of applications and provide. an attractive alternative to analog-based PLL synthesizers. under processor control.2 DDS advantages      Micro-Hertz tuning resolution of the output frequency and sub-degree phase tuning capability.

as a replacement for the address counter. 4 . The output frequency of this DDS implementation is dependent on 1. While the analog output fidelity.1 Simple Direct Digital Synthesizer In this case.) the sine wave step size that is programmed into the PROM. jitter. The address counter steps through and accesses each of the PROM‘s memory locations and the contents (the equivalent sine amplitude words) are presented to a high-speed D/A converter. the digital amplitude information that corresponds to a complete cycle of a sine wave is stored in the PROM. To understand this basic function. Each designated point on the phase wheel corresponds to the equivalent point on a phase wheel. and AC performance of this simplistic architecture can be quite good. The D/A converter generate an analog sine wave in response to the digital input words from the PROM.Fig 2. an N-bit variable-modulus counter and phase Fig 2. As figure 1-2 shows. With the introduction of a phase accumulator function into the digital signal chain. and 2. it lacks tuning flexibility. Neither of these options supports high-speed output frequency hopping. visualize the sine wave oscillation as a vector rotating around a phase circle. The PROM is therefore functioning as a sine lookup table.) The frequency of the reference clock. The carry function allows this function as a ―phase wheel‖ in the DDS architecture.2 Frequency-tunable DDS System register are implemented in the circuit before the sine lookup table. this architecture becomes a numerically-controlled oscillator which is the core of a highly-flexible DDS device. The output frequency can only be changed by changing the frequency of the reference clock or by reprogramming the PROM.

The number of discrete phase points contained in the ―wheel‖ is determined by the resolution. As the vector rotates around the wheel. a phase-to amplitude lookup table is used to convert a truncated version of the phase accumulator‘s instantaneous output value into the sine wave amplitude information that is presented to the D/A converter. One revolution of the vector around the phase wheel.cycle of a sine waveform. of the phase accumulator. The output of the phase accumulator is linear and cannot directly be used to generate a sine wave or any other waveform except a ramp. N. results in one complete cycle of the output sine wave. at a constant speed. visualize that a corresponding output sine wave is being generated. The phase accumulator is utilized to provide the equivalent of the vector‘s linear rotation around the phase wheel. Most DDS architectures exploit 5 . Therefore. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.

The magnitude of the increment is determined by a digital word M contained in a ―delta phase register‖ that is summed with the overflow of the counter. If the M value is changed to 0111…1111. This control of the jump size constitutes the frequency tuning resolution of the DDS architecture. or frequency tuning word. or two reference clock cycles. Once the buffer register is loaded. In practical application.the symmetrical nature of a sine wave and utilize mapping logic to synthesize a complete sine wave cycle from ¼ cycles of data from the phase accumulator.3 Signal flow through the DDS architecture The phase accumulator is actually a modulus M counter that increments its stored number each time it receives a clock pulse. the parallel-output delta phase register is 6 . Fig 2. The relationship of the phase accumulator and delta phase accumulator form the basic tuning equation for DDS architecture: FOUT = (M (REFCLK)) /2N Where: FOUT = the output frequency of the DDS M = the binary tuning word REFCLK = the internal reference clock frequency (system clock) N = the length in bits of the phase accumulator Changes to the value of M in the DDS architecture result in immediate and phase-continuous changes in the output frequency. it effectively sets how many points to skip around the phase wheel. The word in the delta phase register forms the phase step size between reference clock updates. This is generally done to minimize the package pin count of the DDS device. The larger the jump size. the phase accumulator will overflow after only 21 clock cycles. the M value. For an N=32-bit phase accumulator. is loaded into an internal serial or byte-loaded register which precedes the paralleloutput delta phase register. the faster the phase accumulator overflows and completes it‘s equivalent of a sine wave cycle. an M value of 0000…0001(one) would result in the phase accumulator overflowing after 232 reference clock cycles (increments). The phase-to-amplitude lookup table generates all the necessary data by reading forward then back through the lookup table.

the signal generator can use this address to control the phase of the signal at any point in time. because we only have 214 available points in our waveform. For NI signal generators. The remaining 34 bits are used to store the remainder of the phase increment. an address of ‗11111111111111‘ corresponds to 359. a 48-bit phase register is used for maximum precision. 2. only the 14 most significant bits of the phase register are used in the lookup table. the phase accumulator is able to represent the phase of the generated signal with 248 points of precision. For example. In this example.1. Obviously. the only speed limitation to changing the output frequency of a DDS is the maximum rate at which the buffer register can be loaded and executed. Generally. the phase accumulator produces a 14-bit address that corresponds to the exact phase of the signal. It does this by dividing the desired frequency by the sample clock and multiplying the result by 248. This number is based on the bit resolution of the phase register. the sampling clock (fCLOCK) is 300 MHz and the fundamental output frequency (fOUT) is 80 MHz 7 . an address of ‗00000000000000‘ corresponds to 0°.978°. Thus. Of these. This remainder enables the DDS precision by ensuring that the lookup table will return the appropriate phase information after the phase register rolls over (once per period of the waveform). 34 bits are used to store the remainder phase. On the other hand.4 Computation of the Phase Register As the diagram suggests. The spectrum of a sampled output is illustrated in Figure 2-1.4 Phase Accumulator The phase accumulator uses simple arithmetic operations to calculate the lookup table address for each generated sample. and 14 bits are used to choose a sample from the lookup table. However. Thus.2 Understanding the Sampled Output of a DDS Device An understanding of sampling theory is necessary when analyzing the sampled output of a DDSbased signal synthesis solution. This is shown below: Fig 2. 2.clocked and the DDS output frequency changes. a parallel byte load control interface enhances frequency hopping capability.

and 5th images appear at 380 MHz.33 fCLOCK. In typical DDS applications. It is important to generate a frequency plan in DDS applications and analyze 8 . In order to keep the cutoff requirements on the low pass filter reasonable. This is due to the quantized nature of the sampled output.5 Spectral Analysis of Sampled Output It is important to note in the sin(X)/X response curve shown in Figure 2-1 that the amplitude of the 1st image is substantial: it is within 3dB of the amplitude of the fundamental at fOUT = . The 1st image response occurs in this example at fCLOCK – fOUT or 220 MHz. the amplitude of the fundamental output will decrease inversely to increases in its tuned frequency.The Nyquist Theorem dictates that there is a minimum of two samples per cycle required to reconstruct the desired output waveform. Notice that nulls appear at multiples of the sampling frequency. DDS architectures can include an inverse SINC filtering which pre-compensates for the sin(X)/X roll off and maintains a flat output amplitude (± . This facilitates using an economical low pass filter implementation on the output. the amplitude of the FOUT and the image responses follows a sin(X)/X roll off response. The amplitude roll off due to sin(X)/X in a DDS system is –3. the 1st image response will appear within the Nyquist bandwidth (DC . Images responses are created in the sampled output spectrum at fCLOCK ± fOUT. and 820 MHz (respectively). As can be seen in Figure. a low pass filter is utilized to suppress the effects of the image responses in the output spectrum. The amplitude of the fundamental and any given image response can be calculated using the sin(X)/X formula.½ fCLOCK) as an aliased image. Per the roll off response function. In the case of the fOUT frequency exceeding the fCLOCK frequency.1 dB) from the D/A converter over a bandwidth of up to 45% of the clock rate or 80% of Nyquist. As was previously shown in Figure 2. The aliased image cannot be filtered from the output with the traditional Nyquist anti-aliasing filter. 680 MHz.92 dB over its DC to Nyquist bandwidth. Fig 2. 4th. 520 MHz.5. The 3rd. it is an accepted rule to limit the fOUT bandwidth to approximately 40% of the fCLOCK frequency.

glitch energy associated with the D/A converter. the quality of its power supplies. Let‘s find the frequency tuning word for an output frequency of 41 MHz where REFCLK is 122. These anomalies will appear as harmonics and spurious energy in the output spectrum and will generally be much lower in amplitude than the image responses. spurs performance. and a variety of other sources of low-level signal corruption. Control data clocking rates of 100 MHz are typically supported for a byte-load parallel control interface.8 MHz M= 556AAAAB hex Loading this value of M into the frequency control register would result in frequency output of 41 MHz. and the quality of the input reference clock. and clock feedthrough noise. parallel byte or serial word.8 MHz)) /232 Solving for M… M = (41 MHz (232))/122. and the speed of the control interface. The phase-continuous output of DDS frequency transitions is well-suited for high-speed frequency-hopping applications. When the tuning word is loaded by the control interface. given a reference clock frequency of 122. such as integral and differential linearity errors of the D/A converter. programmed 9 . ground coupling. The contents of these registers are executed with an external pin on the device package. Typically a DDS device will provide a parallel byte load which facilitates getting data into the control registers at a higher rate. This provides for the maximum output frequency hopping speed between pre-programmed frequency values. This arrangement is especially suitable for FSK modulation applications where the ―mark‖ and ―space‖ frequencies can be readily pre-programmed. The noise floor. The other anomalies in the output spectrum. 2.the spectral considerations of the image response and the sin(X)/X amplitude response at the desired fOUT and fCLOCK frequencies. and jitter performance of a DDS device is greatly influenced by circuit board layout.88 MHz and the tuning word length is 32 bits (binary).8 MHz Determining Maximum Tuning Speed The maximum tuning speed of a DDS implementation is determined by the loading configuration selected. will not follow the sin(X)/X roll-off response. maximum output frequency tuning speed is desired. This means that a new tuning word can be present on the output of a DDS device every 10 nS. Applications such as GMSK and ramped-FSK modulation require maximum frequency tuning speeds to support spectrally-shaped transitions between modulation frequencies. the constraint to frequency update is in the speed of the interface port. The resulting equation would be: 41 MHz = (M (122. DDS devices also usually provide a set of registers that can be pre-programmed with tuning words. In some DDS applications. thermal noise effects.3 Frequency/phase-hopping Capability of DDS Calculating the Frequency Tuning Word The output frequency of a DDS device is determined by the formula: FOUT = (M (REFCLK)) /2N Where: FOUT = the output frequency of the DDS M = the binary tuning word REFCLK = the internal reference clock frequency N = the length in bits of the phase accumulator The length of the phase accumulator (N) is the length of the tuning word which determines the degree of frequency tuning resolution of the DDS implementation. The general noise floor of a DDS device is determined by the cumulative combination of substrate noise.

the 10 .registers. With an 8-bit accumulator. Clearly.3. For example. The solution is to use a fraction of the most significant bits of the accumulator output to provide phase information. The control interface for DDS devices is available in a variety of configurations. it would be impractical to implement such a design.294. in a 32-bit DDS design. Consider a DDS with a 32-bit phase accumulator.  Phase of the output frequency – this function allows the user to execute preprogrammed increments of phase delay to the output signal.2 Profile Registers Pre-programmed registers are typically available in a DDS device that allow enhanced frequency or phase hopping of the output signal. DDS output frequency hopping speeds of up to 250 MHz can be achieved with the latest technology devices. The phase wheel depiction of this particular model is shown in Figure.3 The Effect of Truncating the Phase Accumulator on Spurious Performance Phase truncation is an important aspect of DDS architectures. interpolation (up sampling) rates . The amount of delay resolution ranges from 11.02increments (14bits). The interface conventions range from a single 40-bit register that stores all of the functional control words. Phase-shift keying modulation (PSK) can readily be accomplished with the use of pre-programmed phase registers. To directly convert 32 bits of phase to corresponding amplitude would require 232 entries in a lookup table. and output spectral inversion enable/disable. Control interface functionality and timing diagrams are detailed in the data sheets for the individual DDS devices. That‘s 4. The common configurations are serial interface and byte-load parallel interface. then 4-gigabytes of lookup table memory would be required.3. 2. and configurations of a DDS device are generally programmed through the device‘s control interface port. 2.5increments (5-bits) to . features. To understand the implications of truncating the phase accumulator output it is helpful to use the concept of the ―digital phase wheel‖. The data contained in these registers are executed via a dedicated pin on the package and allow the use to change an operating parameter without going through the control interface instruction cycle.  In digital modulator and quadrature up converter implementations of DDS architectures additional functions can be pre-programmed in profile registers.967. 2. The availability of frequency select registers also facilitates using the DDS device as an FSK modulator where the input data directly steers the output to the desired mark and space frequencies.1 The DDS Control Interface All of the functions. Consider a simple DDS architecture that uses an 8-bit accumulator of which only the upper 5 bits are used for resolving phase.296 entries! If each entry is stored with 8-bit accuracy. The lower 20 bits would be ignored (truncated) in this case. to a microprocessor-compatible a synchronous serial communications port. Examples of the types of functions that can be pre-programmed are:  Output frequency tuning word – this allows the user to achieve the maximum frequency hopping capability with a DDS device. only the upper most 12 bits might be used for phase information.3. These functions include FIR filter response.

there is a discrepancy between the phase of the accumulator and the phase as determined by 5 bits of resolution.41) results. That is. or 11.phase resolution associated with the accumulator is 1/256th of a full circle. Similarly. the accumulator phase resolution is identified by the outer circle of tic marks.41) as depicted by arc E2 in the figure. the accumulator is to count by increments of 6. however. Again.64(4 x 1.41). If only the most significant 5 bits of the accumulator are used to convey phase information. On the second phase step of the accumulator (6 more counts on the outer circle) the phase of the accumulator resides between the 1st and 2nd tic marks on the inner circle. or1. This discrepancy results in a phase error of 8. On the 4th phase step. then the resolution becomes 1/32nd of a full circle.82(2 x 1. as depicted by arc E1 in the figure.6. the accumulator phase and the 5-bit resolution phase coincide resulting in no phase error. This pattern continues as the accumulator increments by 6 counts on the outer circle each time.6. In Figure 2. at the 3rd phase step of the accumulator an error of 2.41(360/28). The result is an error of 5.25(360/25). The first four phase angles corresponding to 6count steps of the accumulator are depicted in Figure 2. Fig 2. Note that the first phase step (6 counts on the outer circle) falls short of the first inner tic mark. These are identified by the inner circle of tic marks. a discrepancy arises between the phase of the accumulator (the outer circle) and the phase as determined by 5-bit resolution (the inner circle). Thus. Now let us assume that a tuning word value of 6 is used.46(6 x 1.6 Phase Truncation Error and the Phase Wheel 11 .

Fig 2. the phase errors introduced by truncating the accumulator will result in errors in amplitude during the phase-to-amplitude conversion process inherent in the DDS.7 Reference clock edge uncertainty adversely affects DDS output signal quality 12 . is actually reduced according to: 20 LOG (Fout/Fclk). Tuning word (T) 2. after a sufficient number of revolutions of the phase wheel. It turns out that these errors are periodic. they appear as line spectra (spurs) in the frequency domain and are what is known as phase truncation spurs. the accumulator phase and truncated phase will coincide.4 Reference Clock Considerations Direct Clocking of a DDS The output signal quality of a direct digital synthesizer is dependent upon the signal quality of the reference clock that is driving the DDS.Obviously. regardless of the tuning word chosen.. edge jitter (in ps or ns). and phase noise (in dBc/Hz) will be reflected in the DDS output. i. They are periodic because. This means that a 10 MHz output signal will have 20 dB less phase noise than the 100 MHz reference clock that ―created‖ it. Important quality aspects of the clock source. the number of bits of phase after truncation 3. Phase word size (P bits). Accumulator size (A bits) 2. One quality. such as frequency stability (in PPM). It turns out that the magnitude and distribution of phase truncation spurs is dependent on three factors : 1. phase noise.e. Since these amplitude errors are periodic in the time domain. The figure below illustrates how DDS processing is affected by phase noise and jitter of the input clock.

The phase noise/jitter of 100MHz DDS clock source 1 is much more pronounced than that of clock source 2. two criteria must be met:  Appropriate amplitude (this is the DAC‘s job)  Appropriate time (the clock‘s job) The Complete-DDS IC‘s from Analog Devices provide an appropriately accurate DAC to translate the digital phase steps to an analog voltage or current. Output 1 shows a 20 dB (10X improvement) in phase noise relative to clock 1. The remaining half involves accurate timing of these amplitude steps that constitute the output sine wave. expressed in the time domain as period jitter with units of percent. This is where minimum clock edge jitter and low phase noise are required to support the precise capabilities of DDS. The phase noise improvement of the DDS output relative to the input clock becomes more apparent in the frequency domain. is relative to the period of the waveform.7 shows how phase noise. In order for the digital phase step to be properly positioned in the analog domain. Notice the presence of low level output ―spurs‖ on the skirt of output 2.e..Figure shows the 10 MHz DDS output response to the two clock sources.Figure 2. showing the phase noise of two different DDS reference clocks. 13 . These step sizes are fixed by the frequency ―tuning‖ word and are mathematically manipulated with excellent precision regardless of the quality of the clock. These spurious signals are also present in output 1 but the signal‘s excessive phase noise is masking their presence. This demonstrates why phase noise is important in maintaining good signal-to-noise ratio in radio and other noise-sensitive systems. 2. But that is only half of the job. although 20 dB is not apparent since the noise floor of the instrument is limiting the measurement. and that absolute edge jitter is unaffected by changes in frequency or period.5 Conclusion The fundamentals to understand DDS technology i. Reference clock edge jitter has nothing to do with the accuracy of the phase increment steps taken by the phase accumulator. the basic theory of operation involved is discussed in this chapter. Output 2 shows less phase noise than clock 2. The ―DDS Reference Clock‖ signals in Figure 5 -1 shows that edge jitter is a much higher percentage of the total period than the same edge jitter in the ―Squared-up Clock Output‖. This accounts for phase noise improvement through frequency division even though the same amount of edge jitter is present on both clock periods. These spurious signals are due to the necessary truncation of phase bits in the DDS phase-to-amplitude stage and the algorithm used to perform the transformation.

Bytes 2 to 5 comprise the 32-bit frequency tuning word. control.25°. the AD9850 generates a spectrally pure. 90°. and loading format. Serial loading is accomplished via a 40-bit serial data stream on a single pin. 45°.3 V supply).5 MHz). surface-mount package. and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million frequencies per second.1 General Description The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed. When referenced to an accurate clock source. and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format.0291 Hz for a 125 MHz reference clock input. The AD9850 Complete DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (3. frequency/phase programmable. power-down enable. and any combination thereof. The AD9850‘s innovative high speed DDS core provides a 32-bit frequency tuning word. It is specified to operate over the extended industrial temperature range of –40°C to +85°C. The device also provides five bits of digitally controlled phase modulation. The parallel load format consists of five iterative loads of an 8-bit control word (byte).5°. or it can be converted to a square wave for agile-clock generator applications. which enables phase shifting of its output in increments of 180°. high performance D/A converter and comparator to form a complete. This sine wave can be used directly as a frequency source. The AD9850 is available in a space-saving 28-lead SSOP. The first byte controls phase modulation. 22. 14 . analog output sine wave. The AD9850‘s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62. digitally programmable frequency synthesizer and clock generator function. 11. This facilitates the device‘s use as an agile clock generator function. which results in an output tuning resolution of 0. The AD9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output.Chapter 3 AD9850 3. The frequency tuning.

23 7 8 D0 to D7 8-Bit Data Input.3. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/ control word. Supply Voltage Leads for Digital Circuitry. These leads are the ground return for the analog circuitry (DAC and comparator).2 Pin Description PIN FUNCTION DESCRIPTION Pin Mnem No. Analog Ground. Reference Clock Input. 28 to 25 5. 24 6. This clock is used to load the parallel or serial frequency/phase/control words. 18 AGND AVDD . Digital Ground. The rising edge of this clock initiates operation. These are the ground return leads for the digital circuitry. Frequency Update. D7 = MSB. it then resets the pointer to Word 0. D0 = LSB. On the rising edge of this clock. the DDS updates to the frequency (or phase) loaded in the data input register. This may be a continuous CMOS-level pulse train or sine input biased at 1/2 V supply. Supply Voltage for the Analog Circuitry (DAC and Comparator). D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word. 15 DGND DVDD W_CL K FQ_UD 9 CLKIN 10. 19 11. onic Function 4 to 1. Word Load Clock.

DACB DAC Baseline. it clears RESET all registers (except the input register). L (NC) this lead is internally bypassed and should Normally be considered a no connect for optimum performance. when set high. Analog Current Output IOUT of the DAC.9 kΩ connected to ground. R QOUT Output True. This is the DAC baseline voltage reference. This is the comparator‘s true output. and The DAC output goes to cosine 0 after additional clock cycles. the value for RSET is 3. The RSET/IOUT Relationship is IOUT = 32 (1. Complementary Analog IOUTB Output of the DAC. Reset. This is the master reset function.12 13 14 DAC‘s External RSET Connection. This is the comparator‘s negative input. 15 VINN 16 17 Noninverting Voltage Input. 20 21 22 16 . This is the comparator‘s VINP positive input.248V/RSET). Inverting Voltage Input. This is the comparator‘s B complement output. This resistor value SET sets the DAC full-scale output current. QOUT Output Complement. For Normal applications (FS I out = 10 mA).

which results in a higher output frequency. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function. CLKIN is the input reference clock frequency in MHz fOUT is the frequency of the output signal in MHz The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter that reconstructs the sine wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. to generate a frequency phase-agile sine wave. it wraps around. and tuning word of the AD9850 is determined by the formula fOUT = (Δ Phase × CLKIN)/232 where: Δ Phase is the value of the 32-bit tuning word. and an on-board high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS compatible output square wave. in the form of a numerically controlled oscillator. When the counter overflows. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. the AD9850 allows an output frequency resolution of 0. The relationship of the output frequency. The basic functional block diagram and signal flow of the AD9850 configured as a clock generator. the faster the accumulator overflows. DDS also enables very high resolution in the incremental selection of output frequency. making the phase accumulator‘s output contiguous. The larger the added increment.0291 Hz with a 125 MHz reference clock applied. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter.3 Theory of operation and application The AD9850 uses Direct Digital Synthesis (DDS) technology. which contributes to the small size and low power dissipation of the AD9850. The AD9850‘s output waveform is phase continuous when changed. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2N number of bits in the tuning word. reference clock. The frequency tuning word sets the modulus of the counter. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. DDS technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency under full digital control.3. 17 . which effectively determines the size of the increment (Δ Phase) that is added to the value in the phase accumulator on the next clock pulse.

3 Output Spectrum of a Sampled Signal In this example. To apply the AD9850 as a clock generator. or close to. In fact. Specifically.3. the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter output. A graphical representation of the sampled spectrum. and thereby avoid generating aliased signals that fall within. Fig 3. its output spectrum follows the Nyquist sampling theorem. the device resumes normal operation. consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. This practice eases the complexity (and cost) of the external filter requirement for the clock generator application. A low-pass filter is generally placed between the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images. its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency  the selected output frequency. This 18 .Fig 3. limit the selected output frequency to <33% of reference clock frequency. with aliased images. The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. Obviously. the first aliased image can be on the order of –3 dB below the fundamental.2 Basic DDS Block Diagram and Signal Flow of AD9850 AD9850 is a sampled signal. the reference clock is 100 MHz and the output frequency is set to 20 MHz As can be seen. is shown in Figure 3. if the clock frequency again exceeds the threshold. the output band of interest (generally dc-selected output frequency). When in this state. depending on the reference clock relationship.

The rising edge of FQ_UD loads the (up to) 40-bit control data-word into the device and resets the address pointer to the first register. an FQ_UD pulse is required to update the output frequency (or phase). the register is loaded via an 8-bit bus. In serial load mode. and powering up/down. After five loads. This register can be loaded in a parallel or serial mode. 19 . a single low-pass filter.4 through 3. After 40 bits are shifted through. W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register. are shown in the timing diagrams of Figures 3. resetting the device. The function assignments of the data and control words are shown in Table III.4 Programming the AD9850 The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word.10. In the parallel load mode. and the generation of the comparator reference midpoint from the differential DAC output.shutdown mode prevents excessive current leakage in the dynamic registers of the device. the detailed timing sequence for updating the output frequency and/or phase. the 5-bit phase modulation word. The user must take deliberate precaution to avoid inputting the codes listed in Table II. subsequent rising edges of W_CLK shift the 1-bit data on Pin 25 (D7) through the 40 bits of programming information. and the power-down function. Note: There are specific control codes. The typical application of the AD9850 is with single-ended output/ input analog signals. the full 40-bit word requires five iterations of the 8-bit word. 3. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. The W_CLK and FQ_UD signals are used to address and load the registers. used for factory test purposes that render the AD9850 temporarily inoperable. The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end system.

Fig 3.4 Parallel Load Frequency/Phase Update Timing Sequence Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment 20 .

5 Master Reset Timing Sequence Figure 3.6 Parallel Load Power-Down Sequence/Internal Operation Fig 3. However. Results of reset: – frequency/phase register set to 0 – address pointer reset to w0 – power-down bit reset to 0 – data input register unaffected Fig 3.7 Parallel Load Power-Up Sequence/Internal Operation 21 .Note: the timing diagram above shows the minimal amount of reset time needed before writing to the device. the master reset does not have to be synchronous with the clk in if the minimal time is not required.

hardwire pin 2 at 0. and pin 4 at 1 (See figure 3.9 Pins 2 to 4 Connections for Default Serial Mode Operation Figure 3. 40-Bit Serial Load Word Function Assignment 22 .8 Serial Loads Enable Sequence Note: for device start-up in serial mode. Figure 3. pin 3 at 1.9).10 Serial Load Frequency/Phase Update Sequence Table IV.Fig 3.

Avoid running digital lines under the device because these couple noise onto the die. The power and ground planes should be free of etched traces that cause discontinuities in the planes.Figure 3. which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist. The power supply lines to the AD9850 should use as large a track 23 . It is recommended that the top layer of the multilayer board also contain an interspatial ground plane.5 PCB layout information The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolution design and layout practices.11 Serial Load Power-Down Sequence Figure 3. they should be connected together at the AD9850 for optimum results.12 AD9850 I/O Equivalent Circuits 3. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes.

7.and phase-agile clock source (see Figure 17 for an electrical schematic of AD9850/CGPCB). All analog and digital supplies should be decoupled to AGND and DGND. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850. It connects the AD9850‘s DAC output to the internal comparator input via a single-ended.5 inch floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen. ideally right up against the device.5 inch floppy drive. applications engineering support is available to answer additional questions on grounding and PCB layout. The 3. 42 MHz low-pass.as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. 5-pole elliptical filter. and Centronics compatible printer cable.7 AD9850 Evaluation Board Instructions 3. The operating software runs under Microsoft® Windows® and provides a user friendly and intuitive format for controlling the functionality and observing the performance of the device.6 Evaluation Boards Two versions of evaluation boards are available for the AD9850. The AD9850/CGPCB is used in applications using the device in the clock generator mode. it is recommended that the system‘s AVDD supply be used. Remove R2 for high Z clock input. 3. 3. This model facilitates the access of the AD9850‘s comparator output for evaluation of the device as a frequency. The AD9850/FSPCB is used in applications where the device is used primarily as a frequency synthesizer.1 Required Hardware/Software  IBM compatible computer operating in a Windows environment. To achieve best performance from the decoupling capacitors. respectively. Use micro strip techniques where possible. Both versions of the AD9850 evaluation board are designed to interface to the parallel printer port of a PC. Good decoupling is also an important consideration.  AD9850 evaluation board software disk and AD9850/FSPCB or AD9850/CGPCB evaluation board. the internal comparator on the AD9850 DUT is not enabled (see Figure 15 for an electrical schematic of AD9850/FSPCB). with high quality ceramic capacitors. remove R2. The evaluation boards are configured at the factory for an external reference clock input. 24 . if the on-board crystal clock source is used. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signal paths. 3. The evaluation board can be operated with 3.  5 V voltage supply. This reduces the effects of feed through through the circuit board. Traces on opposite sides of the board should run at right angles to each other.  XTAL clock or signal generator—if using a signal generator. Analog Devices.  Printer port.3 V or 5 V supplies. which facilitate the implementation of the device for bench top analysis and serve as a reference for PCB layout. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. Inc. This version facilitates connection of the AD9850‘s internal D/A converter output to a 50 Ω spectrum analyzer input. they should be placed as close as possible to the device. dc offset the signal to one-half the supply voltage and apply at least 3 V p-p signal across the 50 Ω (R2) input resistor.

3. The AD9850/FSPCB provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). The AD9850 is powered separately from the connector marked DUT +V. Monitor should display a control panel to allow operation of the AD9850 evaluation board. The AD9850 may be powered with 3. fifth-order.Locate the CLOCK box and place the cursor in the frequency box. Other operational modes (frequency sweeping. and E5 to E6 connects the on-board filter and the midpoint switching voltage to the comparator. Users may elect to insert their own filter and comparator threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold voltage at E1. elliptic. 5. locate the box called COMPUTER I/O. 3. Connect the printer cable from your computer to the AD9850 evaluation board.7. The output should be a dc voltage equal to the full-scale output of the AD9850. 8. Move the cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in MHz). 25 . Locate the file called 9850REV2. This will assist weak printer port outputs in driving the heavy capacitance load of the printer cable. Click the LOAD button or press enter on the keyboard. 4. Locate the MASTER RESET button with the mouse and click it. 2. E3 to E4. they must remove R2 (a 50 Ω chip resistor). Changing the output phase is accomplished by clicking on the down arrow in the OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button. 45 MHz. Point to and click the selection marked LPT1 and then point to the TEST box and click.3 Operation On the control panel. Type in the clock frequency (in MHz) that the user will be applying to the AD9850. the AD9850 output should be active and outputting the user's frequency information. The AD9850/CGPCB provides BNC inputs and outputs associated with the on-chip comparator and the on-board. Connect external 50 Ω clock or remove R2 and apply a high Z input clock such as a crystal can oscillator. This will reset the AD9850 to 0 Hz. 3. The BUS MONITOR section of the control panel will show the 32-bit word that was loaded into the AD9850.2 Setup 1.EXE and execute that program. The crystal oscillator must be either TTL or CMOS (preferably) Compatible. If they have trouble getting their computer to recognize any printer port. 0° phase.7. 6. A message will appear telling users if their choice of output ports is correct.3 V to 5 V. The two active outputs are labeled TP5 and TP6. low-pass filter. Unmarked ground connections are adjacent to each of these test points. and 7 of U3 to 5 V.8 Conclusion The signal flow. If troubles persist. Copy the contents of the AD9850 disk onto your hard drive (there are three files).3. they should try the following: connect three 2 kΩ pull-up resistors from Pins 9. Jumpering (soldering a wire) E1 to E2. Click the LOAD button or press the enter key. serial input) are available to the user via keyboard/mouse control. Choose other ports as necessary to achieve a correct setting. try a different printer cable. If users choose to use the XTAL socket to supply the clock to the AD9850. The two active inputs are labeled TP1 and TP2. 200 Ω input/output Z. programming the AD9850 and other necessary information related to its operation is discussed in this chapter. The unmarked hole next to each labeled test point is a ground connection. Upon completion of this step. sleep. Apply power to AD9850 evaluation board.

a power jack. the software can be downloaded for free. designers. The boards can be built by hand or purchased preassembled. hobbyists. The hardware reference designs (CAD files) are available under an open-source license. an ICSP header. The microcontroller on the board is programmed using the Arduino programming language (based on Wiring) and the Arduino development environment (based on Processing). Arduino can sense the environment by receiving input from a variety of sensors and can affect its surroundings by controlling lights. a USB connection. it features the Atmega16U2 (Atmega8U2 up to version R2) programmed as aUSB-to-serial converter. and other actuators. 26 . 6 analog inputs. simply connect it to a computer with a USB cable or power it with an AC-to-DC adapter or battery to get started. a 16 MHz ceramic resonator.Chapter-4 ARDUINO Arduino is an open-source electronics prototyping platform based on flexible. It's intended for artists. easy-touse hardware and software.1 ARDUINO pin description The Arduino Uno is a microcontroller board based on the ATmega328. and a reset button. motors. and anyone interested in creating interactive objects or environments. 4. It has 14 digital input/output pins (of which 6 can be used as PWM outputs). Instead. The Uno differs from all preceding boards in that it does not use the FTDI USB-to-serial driver chip. It contains everything needed to support the microcontroller.

27 . In future. moving forward. the IOREF that allow the shields to adapt to the voltage provided from the board. The Uno and version 1.1ARDUINO UNO Description Revision 2 of the Uno board has a resistor pulling the 8U2 HWB line to ground.0. for a comparison with previous versions. making it easier to put into DFU mode. shields will be compatible both with the board that uses the AVR. "Uno" means one in Italian and is named to mark the upcoming release of Arduino 1.  Stronger RESET circuit.0 will be the reference versions of Arduino. and the reference model for the Arduino platform. which operate with 5V and with the Arduino Due that operate with 3. The Uno is the latest in a series of USB Arduino boards.  At mega 16U2 replace the 8U2. see the index of Arduino boards.0 pin out: added SDA and SCL pins that are near to the AREF pin and two other new pins placed near to the RESET pin. Revision 3 of the board has the following new features:  1. The second one is a not connected pin that is reserved for future purposes.3V.Figure 4.

or. the voltage regulator may overheat and damage the board. The power source is selected automatically. The recommended range is 7 to 12 volts.1. if supplying voltage via the power jack. If using more than 12V. access it through this pin.1mm center-positive plug into the board's power jack.1. External (non-USB) power can come either from an AC-to-DC adapter (wall-wart) or battery.2 Schematic & Reference design Power The Arduino Uno can be powered via the USB connection or with an external power supply.  5V. or the VIN pin 28 . The adapter can be connected by plugging a 2.12V).4. The input voltage to the Arduino board when it's using an external power source (as opposed to 5 volts from the USB connection or other regulated power source). however.1 Characteristics 4. If supplied with less than 7V. Leads from a battery can be inserted in the Gnd and Vin pin headers of the POWER connector. You can supply voltage through this pin. The board can be supplied with power either from the DC power jack (7 . The power pins are as follows:  VIN. The board can operate on an external supply of 6 to 20 volts. the USB connector (5V). This pin outputs a regulated 5V from the regulator on the board. the 5V pin may supply less than five volts and the board may be unstable.

using pinMode(). These pins can be configured to trigger an interrupt on a low value. Used with analogReference(). the LED is on.e. and can damage your board. A properly configured shield can read the IOREF pin voltage and select the appropriate power source or enable voltage translators on the outputs for working with the 5V or 3. Maximum current draw is 50 mA.  LED: 13.  PWM: 3. Provide 8-bit PWM output with the analogWrite() function. Typically used to add a reset button to shields which block the one on the board. See the attachInterrupt () function for details. 13 (SCK). 29 . Ground pins. The Uno has 6 analog inputs. or a change in value. 9. and digitalRead()functions.3V pins bypasses the regulator. 10. Input and Output Each of the 14 digital pins on the Uno can be used as an input or output.of the board (7-12V). Support TWI communication using the Wire library. each of which provide 10 bits of resolution (i.3 volt supply generated by the on-board regulator. 6. These pins are connected to the corresponding pins of the ATmega8U2 USB-to-TTL Serial chip.  External Interrupts: 2 and 3. labeled A0 through A5.  3. In addition. 12 (MISO). It also has 2 KB of SRAM and 1 KB of EEPROM (which can be read and written with the EEPROM library). There are a couple of other pins on the board:  AREF.3V. By default they measure from ground to 5 volts.  SPI: 10 (SS). 11 (MOSI). Memory The ATmega328 has 32 KB (with 0. 1024 different values). when the pin is LOW. a rising or falling edge. Used to receive (RX) and transmit (TX) TTL serial data.5 KB used for the boot loader).  Reset. some pins have specialized functionality:  TWI: A4 or SDA pin and A5 or SCL pin. These pins support SPI communication using the SPI library. There is a built-in LED connected to digital pin 13. some pins have specialized functions:  Serial: 0 (RX) and 1 (TX). though is it possible to change the upper end of their range using the AREF pin and the analogReference() function. Reference voltage for the analog inputs.3V.  IOREF This pin on the Arduino board provides the voltage reference with which the microcontroller operates. A 3. We don't advise it. and 11. it's off. Bring this line LOW to reset the microcontroller.  GND. They operate at 5 volts. 5. Additionally. digitalWrite(). Supplying voltage via the 5V or 3. When the pin is HIGH value. Each pin can provide or receive a maximum of 40 mA and has an internal pull-up resistor (disconnected by default) of 20-50 ohms.

This means physical press of the reset button before an upload.5 Automatic (software) RESET Rather than requiring a low).1. An ATmega16U2 on the board channels this serial communication over USB and appears as a virtual com port to software on the computer. C header files). see the documentation for details. The '16U2 firmware uses the standard USB COM drivers. The ATmega328 also supports I2C (TWI) and SPI communication.4. which can be activated by:  On Rev1 boards: connecting the solder jumper on the back of the board (near the map of Italy) and then resetting the 8U2.inf file is required. it resets each time a connection is made to it from software (via USB). The ATmega328 on the Arduino Uno comes preburned with a boot loader that allows you to upload new code to it without the use of an external hardware programmer. It's labeled "RESET-EN". the reset line drops long enough to reset the chip.4 Programming The Arduino Uno can be programmed with the Arduino software (download). Select "Arduino Uno from the Tools > Board menu (according to the microcontroller on your board). While it is programmed to ignore malformed data (i.e. 4. another Arduino. When this line is asserted (taken that the boot loader can have a shorter timeout. One of the Hardware flow control lines (DTR) of theATmega8U2/16U2 is connected to the reset line of the ATmega328 via a 100 nanofarad capacitor.  On Rev2 or later boards: there is a resistor that pulling the 8U2/16U2 HWB line to ground. use the SPI library.3 Communication The Arduino Uno has a number of facilities for communicating with a computer. which is available on digital pins 0 (RX) and 1 (TX). anything besides an upload of new code). A Software Serial library allows for serial communication on any of the Uno's digital pins.1. making it easier to put into DFU mode. The Uno contains a trace that can be cut to disable the auto-reset. and no external driver is needed. the Arduino Uno is designed in a way that allows it to be reset by software running on a connected computer. If a sketch running on the board receives one-time configuration or other data when it first starts. or other microcontrollers. an . For SPI communication. When the Uno is connected to either a computer running Mac OS X or Linux. make sure that the software with which it communicates waits a second after opening the connection and before sending this data. The Arduino software includes a Wire library to simplify use of the I2C bus. The RX and TX LEDs on the board will flash when data is being transmitted via the USB-to-serial chip and USB connection to the computer (but not for serial communication on pins 0 and 1). on Windows. The ATmega16U2/8U2 is loaded with a DFU boot loader. The ATmega328 provides UART TTL (5V) serial communication. as the lowering of DTR can be well-coordinated with the start of the upload. The Arduino software uses this capability to allow you to upload code by simply pressing the upload button in the Arduino environment. However. For the following half-second or so. The pads on either side of the trace can be soldered together to re-enable it. The Arduino software includes a serial monitor which allows simple textual data to be sent to and from the Arduino board. it will intercept the first few bytes of data sent to the board after a connection is opened. This setup has other implications. 4.1. It communicates using the original STK500 protocol (reference. The ATmega16U2 (or 8U2 in the rev1 and rev2 boards) firmware source code is available . You may 30 . the boot loader is running on the Uno.

also be able to disable the auto-reset by connecting a 110 ohm resistor from 5V to the reset line.6 USB over connection protection The Arduino Uno has a resettable polyfuse that protects your computer's USB ports from shorts and over current.1. 4. Note that the distance between digital pins 7 and 8 is 160 mil (0.7 and 2. Arduino programs are written in C or C++. 4. the fuse provides an extra layer of protection. see this forum thread for details. the fuse will automatically break the connection until the short or overload is removed. 4. Four screw holes allow the board to be attached to a surface or case.2 Conclusion Pin description and its functioning and programming Arduino are discussed in this chapter.1.not an even multiple of the 100 mil spacing of the other pins. The Arduino IDE comes with a software library called "Wiring" from the original Wiring project.7 Physical characteristics The maximum length and width of the Uno PCB are 2. which makes many common input/output operations much easier.1 inches respectively. 31 . Although most computers provide their own internal protection.16"). with the USB connector and power jack extending beyond the former dimension. If more than 500 mA is applied to the USB port.

Frequency update 5. 6. Dividing the given 32bit frequency in to 4bytes 3b. Start 2.2 Algorithm 1.1 Block Diagram 5.Chapter 5 IMPLEMENTATION OF PROJECT 5. Connect the output to the CRO. Send 32 bit frequency 4.transfering a byte taking 1 bit at a time 4. Configuration of pins 3. Sine of desired frequency is obtained 7. End 32 .

5.3 Flow chart Start Configuration of pins Send 32 bit frequency Dividing the given 32 bit frequency into 4 bytes Transferring a byte taking one bit at a time Frequency update Connect the output to the CRO Sine of desired frequency is obtained End 33 .

OUTPUT). // this pulse enables serial mode . pinMode(DATA.connect to serial data load pin (DATA) #define RESET 11 // Pin 11 .5. #define pulseHigh(pin) {digitalWrite(pin. pinMode(RESET. pinMode(W_CLK. } tfr_byte(0x000). data>>=1) { digitalWrite(DATA. OUTPUT). b++. // freq while(1). digitalWrite(pin.5 Conclusion The algorithm. pulseHigh(RESET). // note 125 MHz clock on 9850 for (int b=0. HIGH).connect to reset pin (RST). CLK is pulsed high } } // frequency calc from datasheet page 8 = <sys clock> * <frequency tuning word>/2^32 void sendFrequency(double frequency) { int32_t freq = frequency * 4294967295/125000000. i<8. i++. 34 . LSB first to the 9850 via serial DATA line void tfr_byte(byte data) { for (int i=0. b<4. a bit at a time.Datasheet page 12 figure 10 } void loop() { sendFrequency(10. pulseHigh(W_CLK). data & 0x01). // Final control byte.connect to freq update pin (FQ) #define DATA 10 // Pin 10 . freq>>=8) { tfr_byte(freq & 0xFF). } 5. all 0 for 9850 chip pulseHigh(FQ_UD).e6). flow chart and the program used for the implementation of the project are discussed in this chapter.connect to AD9850 module word load clock pin (CLK) #define FQ_UD 9 // Pin 9 . // Done! Should see output } void setup() { // configure arduino data pins for output pinMode(FQ_UD.4 Program #define W_CLK 8 // Pin 8 . OUTPUT). pulseHigh(FQ_UD). //after each bit sent. } // transfers a byte. LOW). pulseHigh(W_CLK). OUTPUT).

2 Protoshield 35 .1 DDS Module Figure 6.Chapter-6 RESULT Figure 6.

4 Interfacing of Modules 36 .Figure 6.3 ARDUINO UNO Board Figure 6.

37 .5 Final output waveform 6.Figure 6.1 Conclusion The results obtained finally are discussed in this chapter.

3 Conclusion Applications and future scope of this project are clearly discussed in this chapter.Chapter 7 APPLICATIONS AND FUTURE SCOPE 7. The same benefit is however not easily achieved in analog circuits. Therefore. the DDS might also be suitable for the mobiles in the future. 38 .1 Applications     Frequency/Phase—Agile Sine Wave Synthesis Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications 7.2 Future scope The DDS is better suited to base stations than to mobiles. because power consumption is high in the wide output bandwidth DDS. 7. The scaling of the IC technologies constantly reduces power consumption in digital circuitry.

Inc. May 13." U. Direct Digital 1999." Application Note AN-823.CHRONOLOGICAL BIBLIOGRAPHY [1] Comparative Study of PLL. Analog Devices. [5] David Buchanan. [7] Richard J. Kerr and Lindsay A. 39 . EDN. Analog Devices. 2006. "Pseudorandom Dither for Frequency Synthesis Noise. [4] A Technical Tutorial on Digital Signal Synthesis. .S." Application Note AN-237. Analog Devices. Inc. "Choosing DACs for Direct Digital Synthesis. [6] David Brandon. DDS and DDS-based PLL Synthesis Techniques for Communication System by Govind Singh Patel & Sanjay Sharma. [3] DDS Design. Weaver. "Direct Digital Synthesizers in Clocking Applications. 2004. By David Brandon. [2]GRIET Arduino manual.

This device converts real-world analog signals into a digital format that can be processed by a computer. which are beat frequencies between the analog signal and the sampling clock that inherently occur at FSFA. Aliased images appear at 32MHz.." AC Linearity A dynamic measurement of how well an A/D performs.Appendix A GLOSSARY OF DIGITAL COMMUNICATIONS SYSTEMSRELATED TERMS A/D Converter (also A/D or ADC) Short for analog-to-digital converter. These anomalies are usually combinations of harmonics of the fundamental and intermodulation products. a pure sine wave on the analog input appears at the digital output as a pure (sampled) sine wave. As the Nyquist limit is exceeded. etc. The most common architectures for video-speed A/D converters are "flash" and "subranging. Acquisition Time This term relates to sampling A/D's which utilize a track/hold amplifier on the input to acquire and hold (to a specified tolerance) the analog input signal. AC linearity is usually characterized in terms of harmonic distortion. Only the spurious and harmonically-related signals that fall within the A/D's input bandwidth (half the sampling rate) are generally considered important. 83MHz. Analog Ground In high-speed data acquisition applications. spurious signals due to nonlinear distortion within the A/D appear in the digital output. Video-speed A/D converters are those able to digitize video bandwidth signals (greater than 1MHz): some are capable of sampling at rates up to 500 million samples. In an ideal A/D converter. or anti-alias filtering. produced when the fundamental and its harmonics beat with the sampling frequency. however. which can be used as signal sources when isolated with a bandpass filter. See also Aliased Imaging. Active Filter An active filter is one that uses active devices such as operational amplifiers to synthesize the filter response function. for using intentional aliasing as a source of highfrequency signals. Aliased Imaging This is a technique. signal-to-noise ratio.5MHz. Acquisition time is the time required by the T/H amp to settle to its final value after it is placed in the track mode. the analog input must be sampled at a rate of FS>2FA in order to avoid loss of data (Nyquist Theorem). high frequency noise can also be aliased into the input signal range which mandates low-pass filtering. commonly applied to Direct Digital Synthesis (DDS). on the input of a sampled system. The following spectral plot illustrates a DDS output with a clock frequency of 51MHz and fundamental output of 25. This technique has an advantage at high speeds because the need for inductors (with their poor high-frequency characteristics) is eliminated. the aliased signals move within the band of the analog input (DC . system ground is generally physically separated into "analog" and "digital" grounds in an attempt to suppress digital switching noise and minimize its effect on noise-sensitive analog signal processing 40 . and intermodulation distortion performance. 70MHz. Adhering to the Nyquist Theorem prevents in-band "alias" signals. Aliasing In a sampled data system.per-second (Msps) and beyond. In the real world. Likewise.FS/2) and create distortion.

The ability to add internal functions such as phase modulation. high. 41 . this is a device that changes a digitally-coded word into its "equivalent" quantized analog voltage or current. This theorem applies to A/D converter applications as well as data transmission density over limited bandwidth channels. local oscillators. Aperture Jitter Uncertainty. Direct Digital Synthesis (DDS) A process by which you can digitally generate a frequency agile. digital filtering. Aperture delay time is a fixed delay time and is normally not in itself an error source since the "hold" clock edge can be advanced to compensate for it. The digital output waveform is typically tuned by a 32-bit digital word which allows sub-Hz frequency agility.. there are very high-speed D/A's available. capable of converting at data rates up to 1GHz. a D/A converter application may require a sin(X)/X compensation filter to normalize its output amplitude. amplitude modulation. Aperture jitter is a source of error in a sampling system and it determines the maximum slew rate limitation of the sampled analog input signal for a given system resolution. Input signal conditioners. Nyquist Theorem This theorem says that if a continuous bandwidth-limited signal contains no frequency components higher than fC then the original signal can be recovered without distortion if it is sampled at a rate of at least 2 fC. D/A Converter (also D/A or DAC) Short for digital-to-analog converter. Sin(X)/X The output of a D/A converter is a series of quantized levels that represent an analog signal whose amplitude is determined by the sin (X)/X response. They serve in capacities such as modulators. references. amplifiers. highly-pure sine wave. The DDS's frequency output is normally reconstructed with a high-speed. and clock detect/recovery circuits. and I&Q outputs. from an accurate reference clock.circuitry.performance D/A to generate an analog output signal. are making DDS devices attractive for digital communication applications. At higher output frequencies. Jitter Unwanted variations in the frequency or phase of a digital or analog signal. or sample-to-sample of variation. Aperture Delay Time This term applies to A/D converters and Track/hold amplifiers and defines the time elapsed from the application of the "hold" (or "encode") command until the sampling switch opens fully and the device actually takes the sample. or arbitrary waveform. in the aperture delay time. and A/D converters are usually connected to analog ground. Just like the A/D device.

Gives you a square wave output which may eliminate the need for a comparator if the divider has suitable logic levels. 5. Drive the comparator inputs differentially. however. Using a stable reference clock to the DDS is obvious since jitter in = jitter out. Here are some basic steps in assuring best jitter performance: 1. Use of an off-chip comparator is recommended since the hostile (noisy) DDS environment degrades jitter performance. The merits of differential inputs include common-mode noise rejection and 2X the input slew rate. 2. Use spur reduction techniques. Use a stable reference clock for the DDS 2. 7. Use an external comparator or divider for very demanding applications. In choosing an external high-speed comparator. Filter the DDS output to reduce all non-harmonic spurs to at least –65 dBc. 4. Aliased harmonics can be reduced by passing the filtered fundamental and spurs to a passive frequency mixer. To make filtering easier. look for good PSRR specifications. low dispersion and single supply operation. 8. but jitter performance will be compromised. Avoid using slow slew rate signals. If wideband output is required. This is not bad until the harmonic is ―aliased‖ back into the pass band to the comparator where it becomes a nonharmonically related product that will increase jitter. Driving the comparator inputs with a low impedance. Provide low Z inputs to the comparator to suppress high Z noise sources. keep the system clock frequency as high as possible to distance the image spurs as far as possible from the fundamental. 3. The low impedance input discourages extraneous noise and comparator ―kick-back‖. Filtering of the DDS output requires some elaboration. then a low pass filter is the only choice. proper output logic levels.Appendix B JITTER Jitter Reduction in DDS Clock Generator Systems One of the most frequently asked questions regarding DDS clock generator applications is how to minimize clock edge jitter. Bandpass filtering is best since spurs may reside well below and above the fundamental output. 42 . 5 MHz and above: These are the easiest signals to handle due to their fast slew rates. The frequency division process does two very desirable things: 1. Provide plenty of comparator over-drive (at least 1 volt p-p). it will not pass dc so some means of biasing to the comparator input range may be needed. 1 V p-p input signal is ―as good as it gets‖. 6. Reduces spurious components by 20LOG(N) – where N is the division ratio. Sufficient comparator input overdrive keeps output dispersion (variation in propagation delay) to a minimum and promotes decisive switching. up converting to a much higher frequency and then dividing down (example VHF divider is a Mitel SP8402) to your desired output frequency. Higher frequency signals have higher harmonic distortion. differential. A reason able jitter figure for these frequencies is about 75 ps p-p using the above techniques. A passive broadband 1:1 RF transformer is useful in changing from single-ended to differential configuration.

The same benefits as 1 and 2 above will apply. Best results are obtained by outputting a much higher frequency than needed and then dividing down to your Desired output. jitter Levels approaching 75 ps p-p seem obtainable. This method of spur reduction is especially useful When extremely low frequencies with low jitter are needed. Without frequency division.Below 5 MHz: Much more difficult to get good jitter performance due to the slow slew rate of the fundamental. a 1 khz sine wave could produce 10 ns p-p jitter just due to the slow slew to the comparator. Depending on external frequency division ratios. 43 .

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