INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger

Product specication File under Integrated Circuits, IC06 December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

FEATURES Output capability: standard ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

74HC/HCT107

The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nCP to nQ nCP to nQ nR to nQ, nQ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL VCC2 fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC 1.5 V. ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. maximum clock frequency input capacitance power dissipation capacitance per ip-op notes 1 and 2 CL = 15 pF; VCC = 5 V 16 16 16 78 3.5 30 16 18 17 73 3.5 30 ns ns ns MHz pF pF CONDITIONS HC HCT UNIT

December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

PIN DESCRIPTION PIN NO. 1, 8, 4, 11 2, 6 3, 5 7 12, 9 13, 10 14 1Q, 2Q 1Q, 2Q GND 1CP, 2CP 1R, 2R VCC SYMBOL 1J, 2J, 1K, 2K

74HC/HCT107

NAME AND FUNCTION synchronous inputs; ip-ops 1 and 2 complement ip-op outputs true ip-op outputs ground (0 V) clock input (HIGH-to-LOW, edge-triggered) asynchronous reset inputs (active LOW) positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

74HC/HCT107

Fig.4 Functional diagram.

Fig.5 Logic diagram (one flip-flop).

FUNCTION TABLE INPUTS OPERATING MODE nR asynchronous reset toggle load 0 (reset) load 1 (set) hold no change Note 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition X = dont care = HIGH-to-LOW CP transition L H H H H X nCP X h I h I J X h h I I K L q L H q Q H q H L q Q OUTPUTS

December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nCP to nQ propagation delay nCP to nQ propagation delay nR to nQ, nQ +25 typ. 52 19 15 52 19 15 52 19 15 19 7 6 80 16 14 80 16 14 60 12 10 100 20 17 3 3 3 6.0 30 35 22 8 6 22 8 6 19 7 6 22 8 6 6 2 2 23 70 85 40 to +85 40 to +125 UNIT

74HC/HCT107

TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0

max. min. max. min. max. 160 32 27 160 32 27 155 31 26 75 15 13 100 20 17 100 20 17 75 15 13 125 25 21 3 3 3 4.8 24 28 200 40 34 200 40 34 195 39 33 95 19 16 120 24 20 120 24 20 90 18 15 150 30 26 3 3 3 4.0 20 24 240 48 41 240 48 41 235 47 40 110 22 19 ns Fig.6

tPHL/ tPLH

ns

Fig.6

tPHL/ tPLH

ns

Fig.7

tTHL/ tTLH

output transition time

ns

Fig.6

tW

clock pulse width HIGH or LOW reset pulse width LOW removal time nR to nCP set-up time nJ, nK to nCP hold time nJ, nK to nCP maximum clock pulse frequency

ns

Fig.6

tW

ns

Fig.7

trem

ns

Fig.7

tsu

ns

Fig.6

th

ns

Fig.6

fmax

MHz

Fig.6

December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: flip-flops Note to HCT types

74HC/HCT107

The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT nK nR nCP, nJ

UNIT LOAD COEFFICIENT 0.60 0.65 1.00

AC CHARACTERISTICS FOR 74HCT GND = 0 V; tf = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW trem tsu th fmax propagation delay nCP to nQ propagation delay nCP to nQ propagation delay nR to nQ, nQ output transition time clock pulse width HIGH or LOW reset pulse width LOW removal time nR to nCP set-up time nJ, nK to nCP hold time nJ, nK to nCP maximum clock pulse frequency 16 20 14 20 5 30 +25 typ. 19 21 20 7 9 11 8 7 2 66 40 to +85 40 to +125 UNIT VCC WAVEFORMS (V) TEST CONDITIONS

max. min. max. min. max. 36 36 38 15 20 25 18 25 5 24 45 45 48 19 24 30 21 30 5 20 54 54 57 22 ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.6

December 1990

Philips Semiconductors

Product specication

Dual JK ip-op with reset; negative-edge trigger

AC WAVEFORMS

74HC/HCT107

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.6

Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7

Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and the nR to nCP removal time.

PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines.

December 1990