UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences B. Nikoli!

Homework #1 Due Thursday, February 6, 2014. EE 240B

Use the EE240B 32nm CMOS process in all homeworks and projects unless otherwise noted. The SPICE model and instructions for running the simulator are available on the course website. 1. Amplifier analysis As a brief review of some of the basic analysis you learned in EE140/240B, in this problem we will analyze the simple amplifier circuit shown below. You can ignore biasing for now, and the device operates in saturation. You can assume that the small signal output resistance (ro) of the transistor is infinite, and that the only parasitic capacitance associated with the transistor is its Cgs.

Rs Vi ~ Vo RL

a. Draw the small signal model of this circuit. b. What is the DC small signal gain (Vo/Vi) of the amplifier, as a function of the transistors gm and the resistor values Rs and RL? c. What is the loop gain of this amplifier at low frequencies? d. What is the gain of the amplifier at very high frequencies? e. Sketch the magnitude of the transfer function of this amplifier vs. frequency and label the location of the amplifiers poles and zeros (as a function of Rs, RL, gm, and Cgs). 2. Capacitor design In this problem we will look at the design of MOM capacitors in our 10-level metal process. Unless otherwise noted, you should assume that all metal layers have thicknesses as specified in the design rule manual. We will be using up to 9 metal layers, and excluding the top redistribution layer. The metal layers M1-M8 have the same thickness T = 95nm, minimum width W = 56nm, minimum horizontal spacing S = 56nm, vertical spacing H = 600nm, and that the insulator is SiO2. (!r = 3.9). The M9 layer is thicker with T=190nm, minimum width W=160nm, minimum horizontal spacing S = 160nm and the vertical spacing of 600nm. You can assume that the separation of the lowest layer of metal from the substrate is also H = 600nm, and that the inter-layer vias have the same width as the wires they are connected to. For simplicity, you can ignore fringing fields in all of these calculations. a. What is the maximum capacitance density (in fF/m2) you can achieve with a simple horizontal parallel plate? What is the ratio of capacitance to bottom plate parasitic? b. What is the maximum capacitance density (still in fF/m2) you can achieve with a vertical parallel plate? Now what is the ratio of capacitance to bottom plate parasitic? c. What is the structure that gives you the highest capacitance density, and what is that density?

3.

Capacitor matching a) Calculate the error in the ratio C2/C1 for the two layouts below when there is a 10nm overetch on each of the top plates. Overetch causes C1 to be 80nm x 80nm. The desired ratio is 11.

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Find the dimensions of the Cx capacitor below to obtain the ratio C2/C1 = 11.8. Minimize the effect of overetch as much as possible, assuming overetch is small relative to the dimensions of the capacitor. Do not design specifically for the case of 10nm overetch..

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Set up Cadence Virtuoso for the class and explore technology We would like to perform some basic characterization of the class technology. We would like to do it in Virtuoso, but you can use other schematic or netlist entry modes and a simulator of your choice. For this problem, you should plot the results for all of the process corners provided in the library (i.e. SS, TT, FF). Unless otherwise specified, use minimum length transistors with W=1m and a maximum |VGS| and |VDS| of 1.0V. a. Plot the magnitude of the threshold voltage of an NFET and PFET as a function of channel length L. You should sweep L from 30nm to 500nm be sure to use a step size small enough to measure a smooth curve. Plot the gm versus VGS of an NFET on a linear and log scale, biasing the transistor with VGS = VDS. Plot gm/ID as a function of |VGS| (still with VGS = VDS) for an NFET and PFET with L=30nm, 60nm, and 120nm. Then, use this data to plot V* = 2ID/gm as a function of |VGS|. Still using the data from part c., plot ID as a function of V*. Plot the output resistance ro and DC gain gmro versus VDS for an NFET and PFET. You should bias the transistors with V* = 200mV. What is the allowed output swing to maintain a DC gain of 80% of the peak value? Plot fT and fT(gm/ID) as a function of |VGS-VT| for L=30nm, 60nm, and 120nm. You should set VDS = VGS and vary |VGS-VT| from 0 to 500mV. What is the V* that achieves the maximum fT(gm/ID) for each channel length?.

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Keep these results handy for future design work!