EXPERIMENT #5 Multiplexers in Combinational logic design

Objecti e!
The goal of this experiment is to introduce multiplexers in the implementation of combinational logic design. In addition, procedural programming in VERILOG will be introduced to the student.

"iscussion!
Multiplexer or #elector! The basic function of the circuit is to select one of se eral inputs to connect to a single output line. T!pical multiplexers "#$%&s' come in ()*, +)*, ,)* and *-)*. . #$% is composed of n selections bits that maps (n inputs to a single output. . TTL series ,)* #$% is /+*0*, which is an eight to one ",)*' multiplexer. Examine the spec sheet in .ppendix . for /+*0*. The data select lines are 1 (, 1*, and 12 "often called the control 3 selection lines'. Each of the , possible combinations of 1 (, 1*, and 12 selects one of the , AND gates which maps one of , possible inputs to the output 4. The output of the selected AND gate will be the same as the input signal on the corresponding data input line. .ll other AND gate outputs will be 52&. The output of the OR function will be the same as the output of the selected AND gate. In this wa!, the input data associated with a selected line is routed to the output signal line. This operation is called #ultiplexing. The /+*0* has another input called the Enable Input "6'. The bar on the s!mbol specifies that the Enable input is acti e low. This means the output is enabled when the input signal is 7ero. Otherwise, the output is set to one when the recommended pull8up resistor is used. The 6 input allows two cascaded ,)* multiplexers to be combined together to form a single *-)* multiplexer. .lthough multiplexers are primaril! used for switching data paths the! can also be used to reali7e general logic functions. 9unction) 9"w,x,!,7' : "To be gi en out b! the laborator! instructor.'

Pre$%aborator& 'ssignment!
*. Gi en the 9unction 9"w, x, !, 7' generate this function&s truth table. ;ext, determine the min8terms "the combination of w, x, !, and 7 for which the output function 9 is one'. These combinations determine the input locations of the multiplexer which are set to one. The combinations, for which the output is 7ero, form the input locations of the multiplexer which are set to 7ero.

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(. <raw a logic schematic in !our noteboo= using two ,)* multiplexers. >onsider the enable input as acti e high "%ilinx has the Enable input as acti e high 8 E'. Three of the input ariables in the gi en function 9"w,x,!,7' are used as control inputs to the selection 3 control inputs of each of the ,)* multiplexers and the fourth input ariable is used to select between the two ,)* multiplexers using the E input. .n OR gate is used to OR the two ,)* multiplexer outputs. ?. @rite the test plan of this experiment on how it should be tested. +. @rite the <esign 1pecification Alan for this experiment 0. Read this experiment carefull! to become familiar with the experiment.

Procedure!
*. $sing %ilinx&s I1E and its schematic capture tool, design a *-)* multiplexer using two ,)* multiplexers "s!mbol #,B*E is located in the #$% categor!'. Three of the input ariables in the gi en function 9"w,x,!,7' are used as control inputs to the selection 3 control inputs of each of the ,)* multiplexers and the fourth input ariable is used to select between the two ,)* multiplexers using the E input "acti e high'. .n OR gate is used to OR the two ,)* multiplexer outputs. (. <efine a four bit input C$1 1 and a single output O. This four bit bus should be connected to 1@2, 1@*, 1@(, and 1@? and the O output should be lin=ed to LE</ on the C.141 board. ?. The sixteen inputs should be hard coded as D2 : groundE and D* : V>>E using the 5gnd& and 5 cc& from the .dd 1!mbol Tool next to the .dd Instance tool. There should onl! be four bits for input 1 and one bit for output O for this experiment. +. $se the count up option in the test bench wa eform tool to ar! the select input 1 from 2222 binar! to **** binar!. <ownload the implemented design of 1teps *8? to the 9AG. using the E%AORT program. >reate a new truth table to erif! that the design has implemented correctl!. 0. .t this point, steps * to + need to be repeated but this time using the VERILOG programming language. 9or the pre ious experiments * to +, the VERILOG modules created thus far ha e been combinational logic designs. .nother area of VERILOG programming is procedural programming, wherein 5if statement&, 5for loops&, and 5case statements& can be used. 9or this experiment, a procedural program will be written that implements a *-)* multiplexer. .ll procedural programs begin with the alwa!s function) al(a&s )* argument+

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The argument can be posedge "for positi e edge' or negedge "for negati e edge' of a signal or Fust the signal name, as shown below) al(a&s )* posedge cloc,+ al(a&s )* #+ In the first line, the procedure is executed e er! positi e edge of the cloc= and in the second case whene er 1 changes. The -or. and the -and. operators can be used to combine signals together. The -or. and the -and. operators are spelled out here as shown below) al(a&s )*# or /+ al(a&s )* # and /+ $nli=e > programming, which uses open and closed brac=ets to define a function, VERILOG uses the -begin. and the -end. statement) al(a&s )* posedge cloc,+ begin insert code 0ere end .ll procedural code must ha e on the left side of an eGuation, ariables that are defined as register. The 9AG. needs a method to store these alues between executions of the code depending on the al(a&s command) reg '1 reg 23!45 61 (ire I7 T1 assign I 8 91 assign T 8 41 al(a&s )* posedge cloc,+ begin 6245 8 T1 6295 :8 I1 ' :8 41 end This short piece of code defines the ariables I and T as wires and then assigns them the alue of * and 2 respecti el!. This code also defines the ariables ' as a * bit register "* flip8flop' and 6 as a + bit register. The reader ma! notice two t!pes of assignment declarations in the program. 9irst, onl! combinational logic uses the assign operator. The second set of operators : and :8 are used within the al(a&s procedure. The eGuals ":' onl! assignment is called a bloc,ing operation. ;o other

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parts of the al(a&s procedure is executed until this operation is executed. .ll other operations are bloc=ed until this line of code is executed, Fust li=e a regular > program. The greater than eGuals assignment "H:' implies parallelism. .ll H: assignments are executed in parallel. 9or the abo e code, 6245 8 T is executed first followed b! 6295 :8 T and ' :8 4 executed at the same time. $nli=e > programming, timing is important here. 9or example, consider a wire ' is assigned a alue of 0 *' 8 5+, a register C is assigned a alue of *2 *C894+ and a register 6 is defined. >onsider the execution of the following lines) C 8 '1 6 8 C1 .fter execution of the abo e code, C 8 5 and then 6 8 5. Each line of code is executed one line at a time. ;ow consider the code with ', 6, and C defined as shown below) C :8 '1 6 :8 C1 ;ow since both the lines of code are executed in parallel, C 8 5 and 6 8 94. 5If conditional statements&, 5for loops& and 5case statements& can be used within a procedural bloc=. The code below shows an example of using a case statement for a two8bit input C) reg '1 (ire 29!45 61 al(a&s )* posedge cloc,+ begin case *6+ ;<b44! ' 8 41 ;<b49! ' 8 91 ;<b94! ' 8 91 ;<b99! ' 8 41 endcase end .fter stud!ing the abo e VERILOG programming examples, write a VERILOG programming module that implements a *-)* multiplexer using procedural programming. .ssign a +8bit bus 1 for the select lines of the multiplexer and a signal O for the output "O needs to be reg t!pe'. 9or the sixteen inputs, hardcode the function 9"w, x, !, 7' using the assign operator. 1imulate this VERILOG *-)* multiplexer and compare the simulation output to the truth table de eloped for the experiment. $se the count up option in the test bench wa eform tool to ar! the select input 1 from 2222 binar! to **** binar!.

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-. .t this point, the VERILOG ersion of the multiplexer should be implemented assigning 1I2J to 1I?J to 1@2 8 1@? and the output O to LE<2. NOTE! .n interesting thing ma! happen depending on the set of *- inputs to multiplexer. The figure below shows the pace program for one set of *- inputs to multiplexer. The output O appears along with the bus 1 bits 2 and ?. Cits * and ( of bus 1 are missing. @hat happened is that the VERILOG compiler optimi7ed the design b! e aluating the *inputs to the multiplexer for the + bits of selection 3 control to the multiplexer and determined that 1I*J and 1I(J are 5do not cares terms& %. If the *- inputs to the multiplexer change, the 1elect bus bits used in the implementation will change.

The real Guestion is that the user designed a *-)* multiplexer, what did the compiler implement since inputs 1I*J and 1I(J were ignoredK This can be found b! loo=ing under =ie( Tec0nolog& #c0ematic under the 1&nt0esi>e$X#T in the Processes window. <ouble clic= this option and the following window appears showing the top le el schematic representation. #a=e sure the design has been s!nthesi7ed and implemented first. This schematic shows the top8le el diagram of what was implemented. It is a good chec= to ma=e sure that all inputs and outputs are defined as expected. The schematic shows an input bus 1 of four bits and an output O. <ouble clic= the schematic to obtain the next le el of detail as shown in the next 9igure. Coth the Arocesses and the 1ources windows were closed to ma=e it easier to see the detailed schematic. This schematic shows what is actuall! implemented within the 9AG.. The 9AG. selected to use a + word b! * bit loo=up table "L$T' to implement the multiplexer and used onl! two bits 1I?J and 1I2J to address this loo=up table "more on using a memor! de ice to perform logic functions is discussed later in this manual'. The 08 0

output from the loo=up table is then fed to a buffer and to the output O. Cits 1I*J and 1I(J are not used in this design. The actual bus bits used can be determined b! placing the mouse cursor o er the bus tap and reading which bit is used as displa!ed in the highlight popup window.

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$sing onl! the a ailable bits for the select input 1 as defined b! the A.>E program assign these bits to 1@2 8 1@? appropriatel! and assign the output O to LE<2. 9or example, if 1I(J is missing in the input and output list in the A.>E program, lea e 1@( blan=. ;ext re8build the VERILOG *-)* multiplexer so that the s!nthesis and implementation is up to date. 9inall!, generate the programming files to be downloaded to the C.141 board. /. <ownload the L.CIT file to the C.141 board and erif! that the VERLOG ersion of the *-)* multiplexer wor=s as designed.

/uestions!
"To be incorporated within the >onclusion section of !our lab report' *. In estigate the function of a loo=up table and describe how one wor=s. (. >onsider a *- word b! * bit loo=up table. Gi e the alues stored in each location 2222 binar! "word 7ero' to **** binar! "word fifteen' for the function 9"w, x, !, 7'. The truth table that was generated in the pre8laborator! will help here. ?. Ma e !ou met all the reGuirements of this lab "<esign 1pecification Alan'K +. Mow should !our design be tested "Test Alan'K

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