ARM Cortex-M0 Overview

By: Daniel Widyanto September 2010

Contents
Introduction to ARM Cortex-M0 ro!rammer"# Model : roce##or Mode# ro!rammer"# Model : Stac$# ro!rammer"# Model : Core Re!i#ter# ro!rammer"# Model : Interrupt# and %xception# &ui''e#

Introduction to ARM Cortex-M0

Introduction to ARM Cortex-M0

ARM Cortex-M0:
%ntry-le*el (2-bit ARM Cortex proce##or de#i!ned +or a broad ran!e o+ embedded application# #imple, ea#y-to-u#e pro!rammer# model -i!-ly e++icient ultra-lo. po.er operation excellent code den#ity determini#tic, -i!--per+ormance interrupt -andlin! up.ard compatibility .it- t-e re#t o+ t-e Cortex-M proce##or +amily

Bene+it#:

Cortex-M0 core perip-eral#

/0IC:

Sy#tem Control Bloc$:

An embedded interrupt controller t-at #upport# lo. latency interrupt proce##in!1 ro*ide# #y#tem implementation in+ormation and #y#tem control, includin! con+i!uration, control, and reportin! o+ #y#tem exception#1 A 2)-bit count-do.n timer1 I+ implemented, u#e t-i# a# a Real 4ime 2peratin! Sy#tem 3R42S5 tic$ timer or a# a #imple counter
)

2ptional #y#tem timer 3Sy#4ic$5:

Introduction to ARM Cortex-M0 (contd)

Programmers Model

roce##or Mode#

Programmers Model Processor Modes

4-read mode
9#ed to execute application #o+t.are1 4-e proce##or enter# 4-read mode .-en it come# out o+ re#et1

:andler mode
9#ed to -andle exception#1 4-e proce##or return# to 4-read mode .-en it -a# +ini#-ed all exception proce##in!1
Note 2t-er ARM arc-itecture# #upport t-e concept o+ pri*ile!ed or unpri*ile!ed #o+t.are execution1 4-i# proce##or doe# not #upport di++erent pri*ile!e le*el#1 So+t.are execution i# al.ay# pri*ile!ed, meanin! #o+t.are can acce## all t-e +eature# o+ t-e proce##or1

Programmers Model

Stac$#

Programmers Model !tac"s

=ull de#cendin!: #tac$ pointer indicate# t-e la#t #tac$ed item on t-e #tac$ memory1 4.o #tac$#, t.o independent #tac$ pointer#:
roce##or mode 4-read :andler 9#ed to execute Application# %xception -andler# Stac$ u#ed Main #tac$ or proce## #tac$ Main #tac$

:andler mode al.ay# u#e# t-e MS 3Main Stac$ ointer5 4-read mode can u#e MS 3Main Stac$ ointer5 by de+ault, or S 3 roce## Stac$ ointer5
Controlled by C2/4R2> re!i#ter

In an 2S en*ironment, ARM recommend# t-at t-read# runnin! in 4-read mode u#e t-e proce## #tac$ and t-e $ernel and exception -andler# u#e t-e main #tac$1
<

Programmers Model

Core Re!i#ter#

10

Programmers Model Core Registers

11

Programmers Model Core Registers

ro!ram Statu# Re!i#ter 3 SR5 combine#:
Application ro!ram Statu# Re!i#ter 3A SR5 Interrupt ro!ram Statu# Re!i#ter 3I SR5 %xecution ro!ram Statu# Re!i#ter 3% SR5
Mutually exclu#i*e eac- ot-er1 9#er can acce## t-e .-ole re!i#ter# a# ? SR", or indi*idual bloc$# a# ?A SR" @ ?I SR" @ ?% SR", or combination o+ t.o bloc$#

12

Programmers Model

Interrupt and %xception#

1(

Programmers Model Interru#ts and $xce#tions

4-e *ector table i# +ixed at addre## 0x00000000 1#t record i# #tac$ addre## +or MS 4-e re#t o+ t-e record are addre##e# +or exception -andler#
Addre## only1 /o in#truction #uc- a# ?brancAintB-andlerC"

Addre## +or exception -andler# mu#t be in ?odd" *alue, #ince ARM Cortex-M0 only #upport# 4-umb mode
BitD0E in addre## determined .-et-er 4-umb mode i# u#ed or not

:ard=ault exception .ill be tri!!ered +or ?e*en" addre##1

1)

Programmers Model Interru#ts and $xce#tions

%xception entry
ARM Cortex-M0 i# automatically #a*e t-e re!i#ter# into #tac$ 3pointed by MS 5 be+ore executin! exception -andler

4-e exception -andler addre## t-en +etc- and executed

%xception return

9#e ?%& 'R" to return t-e re!i#ter# *alue +rom #tac$ >R de+ine# t-e mode and #tac$ pointer +or t-e return addre##:
>R F 0x=======1: Return to :andler mode, u#e MS a+ter return >R F 0x=======<: Return to 4-read mode, u#e MS a+ter return >R F 0x=======D: Return to 4-read mode, u#e S a+ter return

16

Programmers Model Interru#ts and $xce#tions

De+inition:
An e*ent t-at alter# t-e normal #eGuence o+ execution Con+i!urable riority Sync-ronou# A#ync-ronou# S0Call endS0, Sy#4ic$, IR&0IR&(1 9ncon+i!ureable riority :ard=ault Re#et, /MI

9ncon+i!ureable priority exception# are un-ma#$able1 Con+i!urable priority exception# are ma#$able 3u#in! ?PRIMA!("5 riority *alue i# 0 3-i!-e#t5 to 1<2 3lo.e#t5
De+ault priority i# 0 3-i!-e#t5 =or IR&0-IR&(1, priority i# -andled by I R0 H I R8 re!i#ter =or S0Call, Sy#4ic$, and endS0, priority i# -andled by S: R2 H S: R( re!i#ter
17

Programmers Model Interru#ts and $xce#tions

Ma!ic .ord#:
4ail-c-ainin!
2n completion o+ an exception -andler, i+ t-ere i# a pendin! exception t-at meet# t-e reGuirement# +or exception entry, t-e #tac$ pop i# #$ipped and control tran#+er# to t-e ne. exception -andler1 :appen# i+ t-e later interrupt -a# #ame or lo.er priority

>ate-arri*in!
I+ a -i!-er priority exception occur# durin! #tate #a*in! +or a pre*iou# exception, t-e proce##or #.itc-e# to -andle t-e -i!-er priority exception and initiate# t-e *ector +etc+or t-at exception1 State #a*in! i# not a++ected by late arri*al becau#e t-e #tate #a*ed .ould be t-e #ame +or bot- exception#1 2n return +rom t-e exception -andler o+ t-e late-arri*in! exception, t-e normal tail-c-ainin! rule# apply1 :appen# i+ t-e later interrupt -a# -i!-er priority

18

Programmers Model Interru#ts and $xce#tions

/0IC: Connectin! external perip-eral# to t-e core IC%R IS%R S IR& D(1:0E R IC R IS R S R IR& endin! I R0I R8

IR& Ma#$I

rioriti'e

C 9

I5 Ma#$ acti*e mean# interrupt i# enabled

1;

)ui**es

1<

)ui**es
Run ?> CJpre##o" and do.nload ?CMSIS" example 2pen ?coreBcm01-" and ?coreBcm01c" +ile An#.er t-e#e Gue#tion#:
W-at a##embly in#truction t-at i# needed to enable interrupt# K :o. to #et MS K 3clue: C +unction name5 :o. to enable #peci+ic IR& K 3clue: C +unction name5 :o. to #et t-e IR& priority K 3clue: C +unction name5

20

ARM Cortex-M0 Overview

By: Daniel Widyanto September 2010

Contents
Introduction to ARM Cortex-M0 ro!rammer"# Model : roce##or Mode# ro!rammer"# Model : Stac$# ro!rammer"# Model : Core Re!i#ter# ro!rammer"# Model : Interrupt# and %xception# &ui''e#

Introduction to ARM Cortex-M0

Introduction to ARM Cortex-M0

ARM Cortex-M0:
%ntry-le*el (2-bit ARM Cortex proce##or de#i!ned +or a broad ran!e o+ embedded application# #imple, ea#y-to-u#e pro!rammer# model -i!-ly e++icient ultra-lo. po.er operation excellent code den#ity determini#tic, -i!--per+ormance interrupt -andlin! up.ard compatibility .it- t-e re#t o+ t-e Cortex-M proce##or +amily

Bene+it#:

Cortex-M0 core perip-eral#

/0IC:

Sy#tem Control Bloc$:

An embedded interrupt controller t-at #upport# lo. latency interrupt proce##in!1 ro*ide# #y#tem implementation in+ormation and #y#tem control, includin! con+i!uration, control, and reportin! o+ #y#tem exception#1 A 2)-bit count-do.n timer1 I+ implemented, u#e t-i# a# a Real 4ime 2peratin! Sy#tem 3R42S5 tic$ timer or a# a #imple counter
)

2ptional #y#tem timer 3Sy#4ic$5:

ARM Cortex-M0 have extra peripherals, other than its processing unit core: -NVIC: To control the interrupt - IC: a!eup interrupt controller, to "a!e the MC# $ro% po"er saving %o&e "ithout an' cloc! -('sTic!: (i%ple )*-+its ti%er, This ti%er can +e use& as RT-( ti%er to %a!e the RT-( porta+le $or all o$ ARM Cortex-M series .Cortex-M0, Cortex-M/, Cortex-M0, Cortex-M*1 -(erial ire 2e+ug .( 21: To ena+le si%ple external connection to &e+ug an& trace ARM Cortex-M series

Introduction to ARM Cortex-M0 (contd)

Programmers Model

roce##or Mode#

Programmers Model Processor Modes

4-read mode
9#ed to execute application #o+t.are1 4-e proce##or enter# 4-read mode .-en it come# out o+ re#et1

:andler mode
9#ed to -andle exception#1 4-e proce##or return# to 4-read mode .-en it -a# +ini#-ed all exception proce##in!1
Note 2t-er ARM arc-itecture# #upport t-e concept o+ pri*ile!ed or unpri*ile!ed #o+t.are execution1 4-i# proce##or doe# not #upport di++erent pri*ile!e le*el#1 So+t.are execution i# al.ay# pri*ile!ed, meanin! #o+t.are can acce## all t-e +eature# o+ t-e proce##or1

3or other ARM Cortex-M series .except ARM CortexM01, the 4unprivileged5 %o&e: has li%ite& access to the M(R an& MR( instructions, an& cannot use the C6( instruction cannot access the s'ste% ti%er, NVIC, or s'ste% control +loc! %ight have restricte& access to %e%or' or peripherals, The 4Handler5 %o&e is al"a's privilege&, The 4Thread5 %o&e can +e privilege& or unprivilege&, &epen&ing on the settings at 4CONTROL5 register, ARM Cortex-M0 retain the %o&e $or co%pati+ilit' "ith other ARM Cortex-M series,

Programmers Model

Stac$#

Programmers Model !tac"s

=ull de#cendin!: #tac$ pointer indicate# t-e la#t #tac$ed item on t-e #tac$ memory1 4.o #tac$#, t.o independent #tac$ pointer#:
roce##or mode 4-read :andler 9#ed to execute Application# %xception -andler# Stac$ u#ed Main #tac$ or proce## #tac$ Main #tac$

:andler mode al.ay# u#e# t-e MS 3Main Stac$ ointer5 4-read mode can u#e MS 3Main Stac$ ointer5 by de+ault, or S 3 roce## Stac$ ointer5
Controlled by C2/4R2> re!i#ter

In an 2S en*ironment, ARM recommend# t-at t-read# runnin! in 4-read mode u#e t-e proce## #tac$ and t-e $ernel and exception -andler# u#e t-e main #tac$1
<

The MSP an& PSP are usuall' use& in RT-( to &i$$erentiate application an& !ernel co&es, To si%pli$' the $ir%"are, in ARM Cortex-M0, the PSP can +e ignore&, #ser can al"a's use MSP $or all o$ their interrupt han&ling or nor%al co&es, -n reset, the processor loa&s the MSP "ith the value $ro% a&&ress 0x00000000,

Programmers Model

Core Re!i#ter#

10

Programmers Model Core Registers

11

Notes: (o%e ARM Cortex-M series instruction onl' "or!s "ith 4lo" registers5 .R0-R71, speciall' the %e%or' access instructions The 6RIMA(7 register prevents activation o$ all exceptions "ith con$igura+le priorit', The +it assign%ents are: 8its Na%e 3unction 90/:/: Reserve& 90: 6RIMA(7 0 ; no e$$ect / ; prevents the activation o$ all exceptions "ith con$igura+le priorit', The C-NTR-< register controls the stac! use& "hen the processor is in Threa& %o&e, The +it assign%ents are: 8its Na%e 3unction 90/:): Reserve& 9/: Active stac! 2e$ines the current stac!: pointer 0 ; M(6 is the current stac! pointer / ; 6(6 is the current stac! pointer, In =an&ler %o&e this +it rea&s as >ero an& ignores "rites, 90: Reserve&,

11

Programmers Model Core Registers

ro!ram Statu# Re!i#ter 3 SR5 combine#:
Application ro!ram Statu# Re!i#ter 3A SR5 Interrupt ro!ram Statu# Re!i#ter 3I SR5 %xecution ro!ram Statu# Re!i#ter 3% SR5
Mutually exclu#i*e eac- ot-er1 9#er can acce## t-e .-ole re!i#ter# a# ? SR", or indi*idual bloc$# a# ?A SR" @ ?I SR" @ ?% SR", or combination o+ t.o bloc$#

12

#ser can also access co%+ination o$ the t"o +loc!s: Register Co%+ination 6(R A6(R, ?6(R, an& I6(R I?6(R ?6(R an& I6(R IA6(R A6(R an& I6(R ?A6(R A6(R an& ?6(R A6(R +it assign%ents: 8its Na%e 3unction 90/: N Negative $lag 900: @ @ero $lag 9)A: C Carr' or +orro" $lag 9)B: V -ver$lo" $lag 9)C:0: Reserve& I6(R +it assign%ents: 8its Na%e 3unction 90/:D: Reserve& 9E:0: ?xception nu%+er This is the nu%+er o$ the current exception 0 ; Threa& %o&e / ; Reserve& ) ; NMI 0 ; =ar&3ault *-/0 ; Reserve&// ; (VCall /), /0 ; Reserve& /* ; 6en&(V /E ; ('sTic!, i$ i%ple%ente&9a: /D ; IRF0 nG/E ; IRF.n-/19+: .nG/D1 to D0 ; Reserve&, 9a: I$ the &evice &oes not i%ple%ent the ('sTic! ti%er, exception nu%+er /E is reserve&, 9+: The nu%+er o$ interrupts, n, is i%ple%entation-&e$ine&, in the range /-0), ?6(R +it assign%ents 8its Na%e 3unction 90/:)E: Reserve& 9)*: T Thu%+ state +it 9)0:0: Reserve&

12

Programmers Model

Interrupt and %xception#

1(

Programmers Model Interru#ts and $xce#tions

4-e *ector table i# +ixed at addre## 0x00000000 1#t record i# #tac$ addre## +or MS 4-e re#t o+ t-e record are addre##e# +or exception -andler#
Addre## only1 /o in#truction #uc- a# ?brancAintB-andlerC"

Addre## +or exception -andler# mu#t be in ?odd" *alue, #ince ARM Cortex-M0 only #upport# 4-umb mode
BitD0E in addre## determined .-et-er 4-umb mode i# u#ed or not

:ard=ault exception .ill be tri!!ered +or ?e*en" addre##1

1)

-ther ARM Cortex-M series supports vector a&&ress re%apping H relocation, ARM Cortex-M0 onl' support a&&ress 0x00 as vector ta+le +ase, 8it90: in a&&ress &eter%ine& "hether the C6# shoul& use Thu%+ %o&e or not, It5s part o$ ARMCT2MI co%pati+ilit',

14

Programmers Model Interru#ts and $xce#tions

%xception entry
ARM Cortex-M0 i# automatically #a*e t-e re!i#ter# into #tac$ 3pointed by MS 5 be+ore executin! exception -andler

4-e exception -andler addre## t-en +etc- and executed

%xception return

9#e ?%& 'R" to return t-e re!i#ter# *alue +rom #tac$ >R de+ine# t-e mode and #tac$ pointer +or t-e return addre##:
>R F 0x=======1: Return to :andler mode, u#e MS a+ter return >R F 0x=======<: Return to 4-read mode, u#e MS a+ter return >R F 0x=======D: Return to 4-read mode, u#e S a+ter return

16

15

Programmers Model Interru#ts and $xce#tions

De+inition:
An e*ent t-at alter# t-e normal #eGuence o+ execution Con+i!urable riority Sync-ronou# A#ync-ronou# S0Call endS0, Sy#4ic$, IR&0IR&(1 9ncon+i!ureable riority :ard=ault Re#et, /MI

9ncon+i!ureable priority exception# are un-ma#$able1 Con+i!urable priority exception# are ma#$able 3u#in! ?PRIMA!("5 riority *alue i# 0 3-i!-e#t5 to 1<2 3lo.e#t5
De+ault priority i# 0 3-i!-e#t5 =or IR&0-IR&(1, priority i# -andled by I R0 H I R8 re!i#ter =or S0Call, Sy#4ic$, and endS0, priority i# -andled by S: R2 H S: R( re!i#ter
17

Reset Invo!e& on po"er up or a "ar% reset, Non-Maskable nterr!pt "NM # Asserte& i$ NMI pin is pulle& =II= +' external circuitr', Not i%ple%ente& in <6C///x Hard$a!lt -ccurs +ecause o$ an error &uring nor%al or exception processing .eg, #n-aligne& %e%or' access1 S%Call ?xception that is triggere& +' the 4S%C5 instruction, In an -( environ%ent, applications can use (VC instructions to access -( !ernel $unctions an& &evice &rivers, PendS% Interrupt-&riven reJuest $or s'ste%-level service, In an -( environ%ent, use 6en&(V $or context s"itching "hen no other exception is active, Invo!e& +' setting P&N'S%S&T +it in 4 CSR, S(sTi)k ?xception "hen the s'ste% ti%er reaches >ero, nterr!pt " R*# ?xception signale& +' a peripheral, or generate& +' a so$t"are reJuest,

16

Programmers Model Interru#ts and $xce#tions

Ma!ic .ord#:
4ail-c-ainin!
2n completion o+ an exception -andler, i+ t-ere i# a pendin! exception t-at meet# t-e reGuirement# +or exception entry, t-e #tac$ pop i# #$ipped and control tran#+er# to t-e ne. exception -andler1 :appen# i+ t-e later interrupt -a# #ame or lo.er priority

>ate-arri*in!
I+ a -i!-er priority exception occur# durin! #tate #a*in! +or a pre*iou# exception, t-e proce##or #.itc-e# to -andle t-e -i!-er priority exception and initiate# t-e *ector +etc+or t-at exception1 State #a*in! i# not a++ected by late arri*al becau#e t-e #tate #a*ed .ould be t-e #ame +or bot- exception#1 2n return +rom t-e exception -andler o+ t-e late-arri*in! exception, t-e normal tail-c-ainin! rule# apply1 :appen# i+ t-e later interrupt -a# -i!-er priority

18

*!estion:

hat it ta!es to ena+le the tail chaining H late arriving $eature K

+ns,er: Nothing, It5s ena+le& +' har&"are +' &e$ault, *!estion: =o" to &isa+le the tail-chaining H late-arriving $eature K +ns,er: 2isa+le the 4con$igura+le exceptions5 through 6RIMA(7, The Reset, NMI, an& =ar&3ault cannot +e &isa+le&,

17

Programmers Model Interru#ts and $xce#tions

/0IC: Connectin! external perip-eral# to t-e core IC%R IS%R S IR& D(1:0E R IC R IS R S R IR& endin! I R0I R8

IR& Ma#$I

rioriti'e

C 9

I5 Ma#$ acti*e mean# interrupt i# enabled

1;

)ui**es

1<

)ui**es
Run ?> CJpre##o" and do.nload ?CMSIS" example 2pen ?coreBcm01-" and ?coreBcm01c" +ile An#.er t-e#e Gue#tion#:
W-at a##embly in#truction t-at i# needed to enable interrupt# K :o. to #et MS K 3clue: C +unction name5 :o. to enable #peci+ic IR& K 3clue: C +unction name5 :o. to #et t-e IR& priority K 3clue: C +unction name5

20