BI CHUN B THC HNH

THIT K VI MCH VI HDL

LAB3
GVHD: Nguyn ng Nhn
H tn: Nguyn Khnh Phong
MSSV: 10520477

Bi 1:
Thit k mch cng hai s BCD 2-digit, A1A0 v B1B0, kt qu tng l gi tr
s BCD 3-digit S2S1S0. S dng SW15-8 v SW 7-0 biu din hai s BCD
A1A0 v B1B0. Gi tr ca A1A0 c hin th trn led 7-on HEX7 v HEX6;
gi tr B1B0 c hin th trn HEX5 v HEX4. Hin th tng S2S1S0 ln cc led
7-on HEX2, HEX1, HEX0. V thit k ch p dng cng cc s BCD, kim tra
trng hp nu cc gi tr input ko phi l BCD v th hin li bng cch bt sng
LED.
module LAB3_10520477_PART1 (SW, LEDG, LEDR, HEX7, HEX6, HEX5, HEX4, HEX3,
HEX2, HEX1, HEX0);
input [17:0] SW;
output [8:0] LEDR, LEDG;
output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
assign LEDR[8:0] = SW[8:0];
assign HEX3 = 7'b1111111;
// show inputs A and B
b2d_7seg H7 (SW[15:12], HEX7);
b2d_7seg H6 (SW[11:8], HEX6);
b2d_7seg H5 (SW[7:4], HEX5);
b2d_7seg H4 (SW[3:0], HEX4);

// check for input errors

wire e1, e2, e3, e4;
comparator C0 (SW[3:0], e1);
comparator C1 (SW[7:4], e2);
comparator C2 (SW[11:8], e3);
comparator C3 (SW[15:12], e4);
assign LEDG[8] = e1 | e2 | e3 | e4;
// sum decimal "ones"
wire c1, c2, c3;
wire [4:0] S0;
2

fulladder FA0 (SW[0], SW[8], SW[16], S0[0], c1);

fulladder FA1 (SW[1], SW[9], c1, S0[1], c2);
fulladder FA2 (SW[2], SW[10], c2, S0[2], c3);
fulladder FA3 (SW[3], SW[11], c3, S0[3], S0[4]);
assign LEDG[3:0] = S0[3:0];
wire z0;
wire [3:0] A0, M0;
comparator9 C4 (S0[4:0], z0);
circuitA AA (S0[3:0], A0);
mux_4bit_2to1 MUX0 (z0, S0[3:0], A0, M0);
//circuitB BB (z, HEX1);
b2d_7seg H0 (M0, HEX0);
wire c4, c5, c6;
wire [4:0] S1;
fulladder FA4 (SW[4], SW[12], z0, S1[0], c4);
fulladder FA5 (SW[5], SW[13], c4, S1[1], c5);
fulladder FA6 (SW[6], SW[14], c5, S1[2], c6);
fulladder FA7 (SW[7], SW[15], c6, S1[3], S1[4]);
assign LEDG[7:4] = S1[3:0];
wire z1;
wire [3:0] A1, M1;

comparator9 C5 (S1[4:0], z1);

circuitA AB (S1[3:0], A1);
mux_4bit_2to1 MUX1 (z1, S1[3:0], A1, M1);
circuitB H2 (z1, HEX2);
b2d_7seg H1 (M1, HEX1);
endmodule

module fulladder (a, b, ci, s, co);

3

input a, b, ci;
output co, s;
wire d;
assign d = a ^ b;
assign s = d ^ ci;
assign co = (b & ~d) | (d & ci);
endmodule

module b2d_7seg (X, SSD);

input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) |
(~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] &
X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) |
(~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] &
X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) |
(~X[3] & X[2] & X[1] & X[0]));
endmodule

// 4 bit >9 comparator

module comparator (V, z);
input [3:0] V;
output z;
assign z = (V[3] & (V[2] | V[1]));
endmodule

// 5 bit >9 comparator

module comparator9 (V, z);
input [4:0] V;
output z;
assign z = V[4] | ((V[3] & V[2]) | (V[3] & V[1]));
endmodule

module circuitA (V, A);

input [3:0] V;
output [3:0] A;
assign A[0] = V[0];
assign A[1] = ~V[1];
assign A[2] = (~V[3] & ~V[1]) | (V[2] & V[1]);
assign A[3] = (~V[3] & V[1]);
endmodule
module circuitB (z, SSD);
input z;
output [0:6] SSD;
assign SSD[0] = z;
assign SSD[1:2] = 2'b00;
assign SSD[3:5] = {3{z}};
assign SSD[6] = 1;
endmodule
module mux_4bit_2to1 (s, U, V, M);
// if ~s, send U
input s;
input [3:0] U, V;
output [3:0] M;
assign M = ({4{~s}} & U) | ({4{s}} & V);
5

endmodule

Bi 2:
Thit k mch nhn mng (array multiplier) hai s nh phn 4-bit khng du A v
B. Thit lp gi tr cho s A bng cc SW 11-8 v hin th ln HEX6. Thit lp
gi tr cho s B bng cc SW 3-0 v hin th ln HEX4. Kt qu C=A*B s
c hin th ln HEX1 v HEX0

Mch Decoder_7seg:
module Decoder_7seg(SW, HEX);
input [3:0] SW;
output [6:0] HEX;
reg [6:0] HEX;
always @(SW)
case (SW)
4'h0:HEX = 7'b1000000;
4'h1:HEX = 7'b1111001;
4'h2:HEX = 7'b0100100;
4'h3:HEX = 7'b0110000;
4'h4:HEX = 7'b0011001;
4'h5:HEX = 7'b0010010;
4'h6:HEX = 7'b0000010;
4'h7:HEX = 7'b1111000;
4'h8:HEX = 7'b0000000;
4'h9:HEX = 7'b0010000;
4'hA:HEX = 7'b0001000;
4'hB:HEX = 7'b0000011;
4'hC:HEX = 7'b1000110;
4'hD:HEX = 7'b0100001;
6

4'hE:HEX = 7'b0000110;
4'hF:HEX = 7'b0001110;
default HEX = 7'b1111111;
endcase
endmodule

Code chnh

module Lab3_10520477_part2 (SW, LEDR, HEX6, HEX4, HEX1, HEX0);

input [17:0] SW;
output [17:0] LEDR;
output [6:0] HEX6, HEX4, HEX1, HEX0;
multiplier M0 (SW[11:8], SW[3:0], LEDR[7:0]);
Decoder_7seg H6 (SW[11:8], HEX6); //A
Decoder_7seg H4 (SW[3:0], HEX4); //B
Decoder_7seg H1 (LEDR[7:4], HEX1); //C1
Decoder_7seg H0 (LEDR[3:0], HEX0); //C0
endmodule
// Mach nhan
module multiplier (A, B, P);
input [3:0] A, B;
output [7:0] P;
wire c01, c02, c03, c04;
wire s02, s03, s04;
wire c12, c13, c14, c15;
wire s13, s14, s15;
wire c23, c24, c25, c26;
assign P[0] = A[0] & B[0];
7

fA F01 (A[1] & B[0], A[0] & B[1], 0, P[1], c01);

fA F02 (A[2] & B[0], A[1] & B[1], c01, s02, c02);
fA F03 (A[3] & B[0], A[2] & B[1], c02, s03, c03);
fA F04 (0, A[3] & B[1], c03, s04, c04);
fA F12 (s02, A[0] & B[2], 0, P[2], c12);
fA F13 (s03, A[1] & B[2], c12, s13, c13);
fA F14 (s04, A[2] & B[2], c13, s14, c14);
fA F15 (c04, A[3] & B[2], c14, s15, c15);
fA F23 (s13, A[0] & B[3], 0, P[3], c23);
fA F24 (s14, A[1] & B[3], c23, P[4], c24);
fA F25 (s15, A[2] & B[3], c24, P[5], c25);
fA F26 (c15, A[3] & B[3], c25, P[6], P[7]);
endmodule

module fA (a, b, ci, s, co);

input a, b, ci;
output co, s;
wire d;
assign d = a ^ b;
assign s = d ^ ci;
assign co = (b & ~d) | (d & ci);
endmodule

Bi 3:
Code delay:
module Delay_1s (Clock, Clock_1);
input Clock;
output Clock_1;
parameter m = 26;
8

reg [m-1:0] slow_count;

reg [0:0] tmp = 0;
always @(posedge Clock)
begin
if(slow_count == 26'd 24999999)

//dem tu 0-24999999

slow_count = 26'd 0;
else
slow_count <= slow_count + 1'b1;
end
always @ (posedge Clock)
if (slow_count == 0)
tmp = ~tmp;
assign Clock_1 = tmp;
endmodule

Code chnh:
module Lab3_10520477_part3 (CLOCK_50, KEY, HEX1, HEX0);
input CLOCK_50;
input [0:0]KEY;//KEY[0] : RESET
output [6:0] HEX1, HEX0;
wire Clk, Reset;
reg [7:0] Q;
assign Reset = KEY[0];

always @(posedge Clk or posedge Reset)

begin
if (Reset)
Q <= 0;
9

else
begin
Q <= Q+1;
if(Q[3:0]==4'b1010)
Q[3:0] <=0;
if(Q[7:4]==4'b1010)
Q[7:4] <=0;
end
end
Delay_1s (CLOCK_50,Clk);
Decoder7seg (Q[7:4], HEX1);
Decoder7seg (Q[3:0], HEX0);
endmodule

Bi 4:
Hin thc mt ng h hin th gi trong ngy. ng h s th hin gi tr gi (t
0 n 23) ln cc led 7-on HEX7-6, gi tr pht (t 0 n 60) ln cc led
HEX5-4, v gi tr pht (t 0 n 60) ln cc led HEX3-2. S dng cc SW15-0
reset li gi tr gi v pht cho ng h.
module LAB3_10520498_PART4 (CLOCK_50, KEY, SW, HEX7, HEX6, HEX5, HEX4,
HEX3, HEX2);
input CLOCK_50;
input [0:0]KEY;
input [15:0]SW;
output [0:6]HEX7, HEX6, HEX5, HEX4, HEX3, HEX2;
wire Clk;
reg [3:0]h1,h0,m1,m0,s1,s0;
always @(posedge Clk)

10

if (KEY[0]==0)
begin
h1 <= SW[15:12];
h0 <= SW[11:8];
m1 <= SW[7:4];
m0 <= SW[3:0];
end
else begin
s0 = s0 + 1;
if (s0 == 4'b1010)
begin
s0 = 0;
s1 = s1 + 1;
if (s1 == 4'b0110)
begin
s1 = 0;
m0 = m0 + 1;
if (m0 == 4'b1010)
begin
m0 = 0;
m1 = m1 + 1;
if (m1 == 4'b0110)
begin
m1 = 0;
h0 = h0 + 1;
if (h0 == 4'b0100)
begin
if(h1 == 4'b0010)
begin
h0 = 0;
11

h1 = 0;
end
end
else if (h0 == 4'b1010)
begin
h0 = 0;
h1 = h1 + 1;
end
end
end
end
end
end

Delay_1s (CLOCK_50,Clk);
Decoder7seg(h1,HEX7);
Decoder7seg(h0,HEX6);
Decoder7seg(m1,HEX5);
Decoder7seg(m0,HEX4);
Decoder7seg(s1,HEX3);
Decoder7seg(s0,HEX2);
endmodule

module Decoder7seg(SW, HEX);

input [3:0]SW;
output [0:6] HEX;
reg [0:6]HEX;

always @(SW)
case (SW)
12

4'b0000 : HEX = 7'b0000001; //0

4'b0001 : HEX = 7'b1001111; //1
4'b0010 : HEX = 7'b0010010; //2
4'b0011 : HEX = 7'b0000110; //3
4'b0100 : HEX = 7'b1001100; //4
4'b0101 : HEX = 7'b0100100; //5
4'b0110 : HEX = 7'b0100000; //6
4'b0111 : HEX = 7'b0001111; //7
4'b1000 : HEX = 7'b0000000; //8
4'b1001 : HEX = 7'b0000100; //9

default HEX = 7'b1111111;

endcase
endmodule

module Delay_1s (Clock, Clock_1);

input Clock;
output Clock_1;
parameter m = 26;
reg [m-1:0] slow_count;
reg [0:0] tmp = 0;
always @(posedge Clock)
begin
if(slow_count == 26'd 24999999)

//dem tu 0-49999999

slow_count = 26'd 0;
else
slow_count <= slow_count + 1'b1;
end
always @ (posedge Clock)
if (slow_count == 0)
13

tmp = ~tmp;
assign Clock_1 = tmp;
endmodule

14