1

4-bit Carry Look Ahead Adder

Samira Sharma
Suneera Sharma
Advisor: Dave Parent
12/6/04
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Agenda
Abstract
Introduction
Why
Simple Theory
Summary of Results
Project (Experimental) Details
Results
Cost Analysis
Conclusions
3
Abstract
We designed an 4-bit carry look ahead
adder that operated at 200 MHz and
used 16mW of Power and occupied an
area of 420x440mm
2
4
Introduction
Why is a Carry Look Ahead Adder important?
- The CLA is used in most ALU designs
- It is faster compared to ripple carry logic adders or
full adders especially when adding a large number
of bits.
The Carry Look Ahead Adder is able to generate
carries before the sum is produced using the
propage and generate logic to make addition much
faster.

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C
1
= G
0
+ P
0
.C
0

C
2
= G
1
+ P
1
.C
1
= G
1
+ P1.G
0
+ P
1
.P
0
.C
0

C
3
= G
2
+ P
2
.G
1
+ P
2
.P
1
.G
0
+ P
2
.P
1
.P
0
.C
0

C
4
= G
3
+ P
3
.G
2
+ P
3
.P
2
.G
1
+ P
3
P
2
.P
1
.G
0
+ P
3
P
2
.P
1
.P
0
.C
0

S
i
= A
i
B
i
C
i
= P
i
C
i
.
G
i
= A
i
.B
i
Pi = (A
i
B
i
)
Equations for Logic of 4-bit CLA
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4-Bit Carry Look Ahead Adder Gate Level Design
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Project Summary
We used the gate design methodology
instead the AOI design method for Carry
logic because of its lesser drain caps we
were able to meet timing specifications,
also, made hand calculations easier to do.
We used a less complicated design and
created separate cells in order make
debugging easier and also allow for a neater
layout.


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Design Flow
Functions and
Specs
Designing
For Logic
Hand
Calculations
Initial
Sizing
Stick
Diagrams
Layout
DRC
& Extraction
LVS
Post
Extraction
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Longest Path Calculations
Note: All widths are in microns
and capacitances in fF
t
PHL
= 5ns/11 = 0.45ns
Logic Level Gate Cg to Drive NSN NSP N M WN (H.C) WP (H.C) WN (S) WP (S) WN (L) WP (L)
1 XOR2 30 2 2 6 6 5.53 9.56 5.55 9.6 5.55 9.6
2 INV 23 1 1 1 1 2.65 4.78 2.65 4.45 2.65 4.45
3 OR5 21 1 5 6 10 1.51 10.05 1.5 9 1.5 9
4 OR4 18 1 4 5 8 1.45 8.02 1.5 8 1.5 8
5 AND5 12 4 1 8 5 7.81 3.35 7.8 3.35 7.8 3.35
6 XOR2 10 2 2 6 6 5.36 9.3 5.8 9.3 5.8 9.3
7 AND2 5.5 2 1 4 3 6.82 6.07 6.8 6.07 6.8 6.07
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Schematic: DFF
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Schematic: Generate and
Propagate
12
Schematic:
Carry Generator
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Schematic: Sum Generator
14
Final Schematic
15
Schematic TB
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Final Simulation
A=1
B=0
Cin=
Test Vectors
1111

+0000
1111
1111
1
0000
10000
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Final Layout
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Net-lists match!
LVS
Verification
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Cost Analysis
verifying logic = 10 hours
verifying timing = 20 hours
Layout = 50 hours
post extracted timing = 5 hours
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Lessons Learned
Learn the tradeoffs of AOI vs. Gate Design
Methodology
-Area Constraints
-Timing Constraints
Develop Good testing and debugging skills.
Have Fun!
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Summary
We met specifications by designing a 4-bit
Carry Look Ahead Adder
-Rise time= Fall time= 2.65 ns
-Total Area= 420x440mm
2
-Power= 16 mW
In the future this circuit design can be
designed using less power and operating at
a higher frequency.
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Acknowledgements
Thanks to Cadence Design Systems for the
VLSI lab
Thanks to all our classmates that helped us
in the lab
Professor David Parent for setting us up for
success!
Undo, Stretch, Copy, Move and Metal 1,2
and 3!