I.

CIRCUIT BASICS

Electrical quantities
Current:
dt
dq
I = [Units: C/s = Amps (A)] Voltage:
dq
dw
V = [Units: J/C = Volts (V)]
Power: VI P
dt
dq
dq
dw
dt
dw
= = =
[Units: J/s = Watts (W)]
avg power:

=
T
T
dt t V t I P
0
1
) ( ) (
P = IV > 0: power delivered
P = IV < 0: power extracted

Primitive circuit elements
Voltage Source Current Source

Resistor follows Ohms Law: V IR = (note polarity)
R = resistance [Units: V/A = Ohms ()]
G = 1/R = conductance [Units: Siemens (S)]
Resistor power dissipation:
R
R I IV P = = =
V
2
2

=
=
n
k
k eq
R R
1


Circuit definitions
Node point where 2 or more circuit elements are connected
Series elements same current flows through all elements
Parallel elements same voltage across all elements

II. CIRCUIT ANALYSIS BASICS

KCL (Kirchhoffs Current Law)
Sum of all currents entering a node = 0
Sum of all currents leaving a node = 0
(currents in) = (currents out)
KVL (Kirchhoffs Voltage Law)
Sum of voltage drops around a loop = 0
Sum of voltage rises around a loop = 0
(voltage drops) = (voltage rises)

Series resistors: Parallel resistors:

=
=
n
k
k eq
R R
1
1 1


2
R +
1
R R
eq
=

2 1
2 1
2 1
||
R R
R R
R R R
eq
+
= =

3 2 1
1 1 1 1
R R R R
eq
+ + =

Voltage divider Current divider


S
V
R R
R
V
2 1
2
2
+
=

S
V
R R R
R
V
3 2 1
3
3
+ +
=

S
I
R R
R
I
2 1
1
2
+
=

S
I
R R R
R
I
3 2 1
3
3
1 1 1
1
+ +
=

Source combinations (series voltage sources and parallel current sources)


III. CIRCUIT ANALYSIS METHODS

Nodal Analysis finds unknown node voltages in a circuit; once all node voltages are known,
currents can be found through IV relationships of circuit elements (e.g., Ohms Law)
1. Choose a reference node (ground)
2. Define unknown voltages (those not fixed by voltage sources)
3. Write KCL at each unknown node, expressing current in terms of node voltages
- use IV relationships of the circuit elements (e.g., I=V/R for resistors)
4. Solve the set of independent equations (N eqns for N unknown node voltages)
Supernode for a floating voltage source (where both terminals are unknown voltages), define
a supernode around the source, write KCL at supernode, and use the voltage source equation

x y F
y
x
V V V
R
V
R
V
I I
=
+ = +
2 1
2 1

Superposition In any linear circuit containing multiple independent sources, any I or V in the
circuit can be calculated as the sum of the individual contributions of each source acting alone
o Linear circuit circuit with only independent sources and linear elements (linear RLC,
linear dependent sources). Linear elements have linear IV characteristics.
1. Leave one source on and turn off all other sources
replace voltage source with short circuit (V=0)
replace current source with open circuit (I=0)
2. Find the contribution from the on source
3. Repeat for each independent source.
4. Sum the individual contributions from each source to obtain the final result

Note: Superposition doesnt work for power, since power is nonlinear (P=I
2
R=V
2
/R)
Thevenin/Norton Equivalent Circuit Models Any linear 2-terminal network of independent
sources and linear resistors can be replaced by an equivalent circuit consisting of 1 independent
voltage source in series with 1 resistor (Thevenin) or 1 independent current source in parallel
with 1 resistor (Norton). The circuit models have the same IV characteristics.

Three variables: V
th
=V
oc
, R
th
=R
N
, I
N
=I
sc
.
Thevenin/Norton relationship: V
th
=I
N
R
th
only 2 of the 3 variables are required
V
th
= V
oc
: open-circuit voltage Leave the port open (I
L
=0) and solve for V
oc
.
I
N
= I
sc
: short-circuit current Short the port (V
L
=0) and solve for I
N
.
R
thc
: Thevenin/Norton resistance Turn off all independent sources (leave the dependent
sources alone). If there are no dependent sources, simplify the resistive network using
series and parallel reductions to find the equivalent resistance. If dependent sources are
present, attach I
test
or V
test
and use KCL/KVL to find R
th
=V
test
/I
test
.

test
test
th
I
V
R =
note the direction of I
test

and the polarity of V
test

Source Transformations conversion between Thevenin and Norton equivalent circuits

Maximum Power Transfer Theorem
power transferred to load resistor R
L

is maximized when R
L
=R
th




Load-line Analysis graphical method solving circuits with 1 nonlinear circuit element
graph the IV curves for the nonlinear circuit element and the Thevenin/Norton equivalent of
the rest of the circuit on the same axes; the operating point is where the two curves intersect


IV. CAPACITORS AND INDUCTORS

Capacitor passive circuit element that stores electric energy
Capacitance: C = Q/V [Units: Coulombs/Volt = Farads (F)]
IV relationship:
dt
dv
c
c
C i =

Energy stored: E
c
= CV
2

voltage across capacitor v
c
cannot change instantaneously: v
c
(0
-
)=v
c
(0
+
)
note polarity!
in steady-state, capacitor is an open circuit (dv
c
/dt=0i
c
=0)
low freq: open circuit; high freq: short-circuit
Parallel capacitors: Series capacitors:

=
=
n
k
k eq
C C
1

=
=
n
k
k eq
C C
1
1 1

Capacitive voltage divider


S
V
C C
C
V
2 1
1
2
+
=

S
V
C C C
C
V
3 2 1
3
3
1 1 1
1
+ +
=


Inductor passive circuit element that stores magnetic energy
Inductance: L = /I [Units: Webers/Amps = Henrys (H)]
IV relationship:
dt
di
L
L
L v =

Energy stored: E
L
= LI
2

current through inductor i
L
cannot change instantaneously: i
L
(0
-
)=i
L
(0
+
)
note polarity!
in steady-state, inductor is a short circuit (di
L
/dt=0v
L
=0)
low freq: short circuit; high freq: open-circuit
Series inductors: Parallel inductors:

=
=
n
k
k eq
L L
1

=
=
n
k
k eq
L L
1
1 1


Capacitor and Inductor Summary :

Capacitor Inductor
IV relationship
dt
dv
C i =

dt
di
L v =

Energy storage E
c
= CV
2
E
L
= LI
2

Continuity Voltage: v
c
(0
-
)=v
c
(0
+
) Current: i
L
(0
-
)=i
L
(0
+
)
Steady-state Open circuit (I=0) Short circuit (V=0)
Series

=
=
n
k
k eq
C C
1
1 1

=
=
n
k
k eq
L L
1

Parallel

=
=
n
k
k eq
C C
1

=
=
n
k
k eq
L L
1
1 1

V

. FIRST-ORDER CIRCUITS
RC circuit contains only sources, resistors, and 1 capacitor
RL circuit contains only sources, resistors, and 1 inductor
voltages and currents are described by 1
st
-order ODE (ordinary differential equation)
RC Circuits RL Circuits

) ( ) (
) (
t v t v
dt
t dv
RC
i c
c
= +

R t i t v
dt
t dv
RC
i c
c
= + ) ( ) (
) (

R
t v
t i
dt
t d L i
R
i
L
L
) (
) (
) (
= +

) ( ) (
) (
t i t i
dt
t di
R
L
i L
L
= +


Time constant: = RC Time constant: = L/R
Tim
erest X(t), using KCL/KVL and IV
Ke
-t/
as

e-domain Analysis for 1
st
-order Circuits
1. Write the ODE in terms of the variable of int
relationships for R, L, C.
2. Find the homogeneous solution X
h
(t) by setting input to 0 and substituting X
h
(t)=
the solution to find the time constant (=RC for RC circuit and =L/R for RL circuit) .
(Note: The value of K cannot be found until the complete solution is found in Step 4.)
3. Find the particular solution X
p
(t). Remember the output follows the form of the input:
input function constant exponential sinusoid
particular solution A
-t -t
Acos( (wt) A e + Bte wt)+Bsin
Gues ut lve d nts. s the form of the sol ion so and the ODE to fin any arbitrary consta
(Note: For sinusoidal inputs, the particular solution can be found more easily using complex imped
Combine the homogeneous and particular solutions to get the complete solution: X
ance.)
4. (t) =
X
h
(t)+X
p
(t). Use the initial conditions to find the missing variables (i.e., the K in X
h
(t)).
Example: Find v
c
(t>0) for RC circuit w/ v
i
(t)=V
DD
, v
c
(0
-
)=0V.
1) ) ( ) (
) (
t v t v
t dv
RC
i c
c
= + 2) v
c,h
(t) = Ke
-t/

0 = +

RC
dt

t t
Ke e
K
= RC
Since v
i
(t) is a constant, s g nto the ODE, A=V
DD
=v
-t/
D
- +
c n .
No
3) gues v
c,p
(t)=A. Plug ing i
c,p
(t).
4) v
c
(t) = v
c,h
(t) + v
c,p
(t) = Ke + V
D
. v
c
(0 )=v
c
(0 ) by capacitor voltage onti uity

-t/
v
c
(0)=0=K+V
DD
K=-V
DD
. So, v
c
(t) = V
DD
-V
DD
e .
te: X
h
(t) represents the transient response of the circuit and should decay to 0 as time
sponse e to decay by 63%
passes. X
p
(t) represents the steady-state response of the circuit which persists after the
transients have died away and which takes the form of the input.
Time constant amount of time for the transient exponential re
-t/
-1
(e = 0.63). In 5 time constants, the response decays by 99%. Faster circuits have smaller .
General 1
st
-order Transient Response for Voltage/Current Step
[ ]

) (
) ( ) (
+

+
+ =
o
t t
f
e X t X X t X (X is any voltage or cur
f o
rent in the circuit)
X
f
= final value, t
o
= time voltage/c n
(1)
+
ty (x(0 )=x(0 )) and steady-state
rule circuit, =L/R for LR circuit). R
is the Thevenin equivalent resistance seen by the cap/ind.
urre t step occurred
- +
Find initial value X(t
o
) and final value X
f
. Use continui
s (open/short) for cap/ind. (2) Calculate (=RC for RC
VI. SE


inary differential equation)
E: Error! Bookmark not
COND-ORDER CIRCUITS
RLC circuit contains only sources, resistors, 1 capacitor, and 1 inductor
voltages and currents are described by 2
nd
-order ODE (ord
General 2
nd
-order OD
defined. ) ( ) ( 2
2
2
t f t x
o
= + +
) ( ) (
2
t dx t x d
dt
dt
= /
= damping coefficient,
o
= undamped natural freq (AKA resonant freq)

o
= damping ratio, f(t) = forcing function (related to the input)
Series RLC Circuit Parallel RLC Circuit

dt
dv
L
t i
LC dt
t di
L
R
dt
t i d
i
1
) (
1 ) ( ) (
2
2
= + +
t) (

dt
t di
C
t v
LC dt
t dv
RC
dt
t v d
i
) ( 1
) (
1 ) ( 1 ) (
2
2
= + +


Time-domain Analysis for 2
st
-order Circuits
1. Write the ODE in terms of the va X(t), using KCL/KVL and IV
hips for R, L, C.
g the input to 0 and substituting X(t)=Ke
st
into
n are
riable of interest
relations
2. Obtain the characteristic equation by settin
the ODE: s
2
+2s+
o
2
=0. Find and
o
. The roots of the characteristic equatio
2 2
s =
; the f
2 , 1 o
o
3. Find the homogeneous solution X
h
(t) depending on :
>
o
, > 1
orm of the solution depends on the damping ratio = / .
overdamped:
t t
h
o o
e K e K t X
) (
2
) (
1
2 2 2 2
) (
+
+ =
critically damped: =
o
, = 1
h
e K t X =
1
) (
t t
te K

+
2

underdamped: <
o
, < 1 ) sin( ) cos( ) (
2 1
t e K t e K t X
n
t
n
t
h


+ =
2 2
=
o n
= damped natural frequency
(Note: The value of
1
d K
2
cannot be f
particular solution X (t). Reme
K an ound until the complete solution is found.)
4. Find the
p
mber the output follows the form of the input:
input function constant exponential Sinusoid
particular solution A Ae
-t
+ Bte
-t
Acos(wt)+Bsin(wt)
Guess the form of the solution and solve the ODE to find any arbitrary constants.
(Note: F s, the olut more ea mplex impedance.)
5. Com us an rticul ge n: X(t) =
X
h
(t)).
or sinusoidal input particular s ion can be found sily using co
bine the homogeneo d pa ar solutions to t the complete solutio
X
h
(t)+X
p
(t). Use the initial conditions to find the missing variables (i.e., K
1
, K
2
in
LC
o
1
=
L
R
2
1
=
LC
RC
o
1
2
1
=
=

V

II. SINUSOIDAL STEADY-STATE ANALYSIS
Any steady-state (SS) voltage or current in a linear time-invariant (LTI) circuit with a sinusoidal input source is
sinusoidal with the same frequency. Only the magnitude and phase (relative to the source) may be different.
Phasors vectors (i.e., complex numbers) that represent sinusoids. Since all V,I in the circuit
are sinusoids with the same frequency, only magnitude & phase are needed to describe any V,I.
sinusoids: v(t) = Vcos(t+) = Re[Ve
j(t+)
] = Re[Ve
j
e
t
] phasor: Ve
j
= V
v(t) = Vsin(t+) = Vcos(t+-/2) phasor: V(-/2)
For convenience, define phasors in terms of cosine (i.e., the real part of a complex exponential)
, ( )
jx jx
j
e e x

=
2
1
) sin( ( ) Eulers Identity: , ) sin( ) cos( x j x e
jx
+ =
jx jx
e e x

+ =
2
1
) cos(
Differentiation/integration become algebraic operations w/ phasors (i.e., complex exponentials)
j
dt
d

j
dt
1

Ex: ( )
) ( ) (

+ +
=
t j t j
dt
d
e j e
Capacitor Impedance:
C j
Z
C

1
=
ICE Current (I) LEADS Voltage (EMF) by 90
Inductor Impedance: L j Z
L
= ELI Voltage (EMF) LEADS Current (I) by 90
Complex Impedance/Generalized Ohms Law:
I
V
Z =

allows for easy nodal analysis (no differential equations); series/parallel resistor laws apply
Maximum Average Power Transfer Theorem
power transferred to load impedance Z
L

is maximized when Z
L
=Z
th
*

Decibel (dB) unit of measure for ratios of power, voltage, and current levels (often used to
express gain). Power: 1dB=10log
10
(P
1
/P
2
); V,I: 1dB=20log
10
(V
1
/V
2
)=20log
10
(I
1
/I
2
)
Frequency Response systems inputoutput transfer function vs. frequency (given
sinusoidal input). Both magnitude and phase plots are needed (output freq = input freq)
General transfer function can be written as a product of poles and zeroes
Error! Bookmark not defined.
( )

1 1
j j
j

=
2 1
) (
p p
j
Ae H

+
2 1
1 1
z z n
j j

zeroes roots of the numerator
poles roots of the denominator
Break point frequency
BP
poles and zeros are break point freqs
at a zero frequency, the magnitude is +3dB (=2) and the phase is +45
at a pole frequency, the magnitude is -3dB (=1/2) and the phase is -45
Bode Plot logarithmic plots for frequency response
Ae
j
j 1/j (1+j/
z
) 1/(1+j/
p
) ) ( j H


to draw Bode plot for general transfer function, add individual pole and zero plots
z

z
10
10
z

dB 40
dec
dB
20 +
dB 0
dB 20
z

z
10
10
z

+
0
4

+
p

p
10
10
p

dec
dB
20 +
dec
dB
20
A
) ( j H dB 0 dB 0 dB 0
1 1
dB 20
dB 40
dec
dB
20
p

10
p

p
10
2

0
) ( j H
2

0 0
2

Filters
Lowpass Filter (LPF) V
C
in RC circuit / V
R
in RL circuit / V
C
and RLC circuit
(for current output, switch from series to parallel and switch L and C)

R L j V
V
in
out
H

+
= =
1
1
) (
RC j V
V
in
out
H

+
= =
1
1
) (
( ) LC j RC j
V
V
in
out
H
2
1
1
) (

+ +
= =
Highpass Filter (HPF) V
L
in RL circuit / V
R
in RC circuit / V
L
in RLC circuit
(for current output, switch from series to parallel and switch L and C)

R L j
R L j
V
V
in
out
H

+
= =
1
) (
RC j
RC j
V
V
in
out
H

+
= =
1
) (
( )
( ) LC j RC j
LC j
V
V
in
out
H
2
2
1
) (

+ +
= =

Bandpass Filter (BPF) V
R
, I
R
in RLC circuit


( ) LC j RC j
RC j
V
V
in
out
H
2
1
) (

+ +
= =

at low freq, cap. impedance
C j
C
Z

1
=
dominates
in out in
Z
V
Z
V
RCV j IR V CV j I
C
in
tot
in
= = = ,

at high freq, ind. impedance L j Z
L
= dominates
R L j
V
out
L j
V
Z
V
Z
V
in in
L
in
tot
in
IR V I

= = = ,

Resonant Frequency
LC
o
1
=
At
o
,
o
C
L
C j
C
jZ j Z
o
= = =

1
,
o
C
L
o L
jZ j L j Z + = + = =
in out
V V =
(capacitor and inductor impedances are equal in magnitude, opposite in sign)
Characteristic Impedance: C L Z
o
=

BPF Bandwidth = 2 = difference between half-power frequencies
Quality Factor Q (1) measure of peakiness or filter selectivity (high Q low bandwidth)
(2) measure of energy stored vs. energy dissipated (high Q low loss)

2
1
2
= = =

o o
Q series RLC:
R
C L
R
Z
o
Q = = parallel RLC:
C L
R
Z
R
o
Q = =
Tradeoffs: Bandwidth/selectivity/speed/energy loss
(e.g., high Q low (high selectivity) low slow transients e
-t
)
V

III. DIODES
Passive devices that only pass current in one direction
Shockley Diode Equation: ( ) 1 =
th D
V v
S D
e I i
I
S
= reverse-bias saturation current (~10
-12
A for Silicon)
V
th
= k
B
T/q = thermal voltage (~26mV @ room temp T=300K)
Large-Signal Diode Model (simplifies circuit analysis)
2 states: on forward bias (v
D
= V
T
): i
D
0
off reverse bias (v
D
< V
T
): i
D
= 0
V
T
= threshold voltage ~ 0.6V
Ideal Diode Model (Perfect Rectifier)
large-signal diode model with V
T
= 0
Zener Diode (simplified)
3 states: forward bias: v
D
= V
T
, i
D
0
reverse bias: V
BD
< v
D
< V
T
, i
D
= 0
breakdown: v
D
= V
BD
, i
D
0

Diode Circuit Analysis Method of Assumed States
(1) Guess the state of each diode (on or off). For large-signal diode model, replace on
diodes with voltage source with voltage drop V
T
and off diodes with open circuits.
(2) Solve the circuit using KCL/KVL.
(3) Check if assumptions for diode states were correct (i.e., check that on diodes have i
D
0
and off diodes have v
D
< V
T
). If not, start over, guessing new states for the diodes.

Rectifier Circuit

Peak Detector Circuit (V
T
=0)

AC-DC Converter (V
T
=0)

I

X. MOSFET
Metal Oxide Semiconductor Field Effect Transistor
(transistor a 3+ terminal device in which one terminal controls the current flow between the other two terminals)
For a MOSFET, the gate controls the current flow between source and drain.
For an n-channel MOSFET (NMOS), a positive gate voltage produces current flow
For a p-channel MOSFET (PMOS), a negative gate voltage produces current flow










NMOS PMOS
analog



digital
Circuit Symbols: NMOS Physical Structure:
NMOS IV Characteristic Square Law Model
3 regions of operation:
cutoff V
GS
< V
Tn
I
DS
= 0
triode/linear
V
GS
> V
Tn
V
DS
V
GS
- V
Tn
I
DS
= K
n
(V
GS
-V
Tn
-V
DS
/2)V
DS

saturation
V
GS
> V
Tn
V
DS
V
GS
-V
Tn
I
DSAT
= K
n
(V
GS
-V
Tn
)
2

V
GS
= V
G
V
S
, V
DS
= V
D
V
S

V
Tn
= threshold voltage (NMOS)
V
DSAT
= V
GS
- V
Tn
= saturation voltage
I
DSAT
= saturation current
K
n
= constant determined by manufacturing process and transistor size (units: A/V
2
)
Channel-Length Modulation Parameter
In the saturation region, I
DS
is not perfectly constant for all V
DS
V
DSAT
; as V
DS
increases,
I
DS
also increases. An additional factor (1+V
DS
) in the IV equation models this effect (the
factor is also added to the triode equation to make the IV curve continuous):
cutoff V
GS
< V
Tn

I
DS
= 0
triode/linear
V
GS
> V
Tn
V
DS
V
DSAT
I
DS
= K
n
(V
GS
-V
Tn
-V
DS
/2)V
DS
(1+
n
V
DS
)
saturation
V
GS
> V
Tn
V
DS
V
DSAT
I
DS
= K
n
(V
GS
-V
Tn
)
2
(1+
n
V
DS
)

PMOS IV Characteristic Square Law Model
Same as NMOS, but switch polarity for everything (V
Tp
is typically negative)
cutoff V
SG
< -V
Tp
I
SD
= 0
triode/linear
V
SG
> -V
Tp
V
SD
V
SG
+ V
Tp
I
SD
= K
p
(V
SG
+V
Tp
-V
SD
/2)V
SD
(1+
p
V
SD
)
saturation
V
SG
> -V
Tp
V
SD
V
SG
+V
Tp
I
SD
= K
p
(V
SG
+V
Tp
)
2
(1+
p
V
SD
)
X

. MOSFET CIRCUIT ANALYSIS
Notation: uppercase w/ uppercase subscript (e.g., V
IN
, V
OUT
) DC large signal
lowercase w/ lowercase subscript (e.g., v
in
, v
out
) AC small signal
lowercase w/ uppercase subscript (e.g., v
IN
, v
OUT
) total signal, DC+AC
Large-signal Analysis find DC operating point (models nonlinearity of MOSFET IV equation)
Method 1: Load-line (graphical) Analysis. Requires MOSFET IV curves.
Method 2: Method of Assumed States.
(1) Guess region of operation for each MOSFET.
(2) Solve circuit with KCL/KVL/nodal analysis, substituting
appropriate IV equation for MOSFET I
DS
.
(3) Check that assumptions for MOSFET operating regions were
correct (triode: V
GS
V
T
, V
DS
V
GS
-V
T
; saturation: V
GS

V
T
, V
DS
V
GS
-V
T
). If not, start over, guessing new operating
regions for the MOSFETs.

Large-signal
Circuit Model
Small-signal Analysis find small-signal gain, R
in
, R
out
(use a linearized circuit model for the MOSFET)
small-signal circuit model is a linearized model for the MOSFET, only valid for small
signals near a given DC operating point (AKA quiescent point)
allows for linear circuit theory (superposition, phasor analysis)
transconductance:
Q
v
i
m
GS
DS
g

= output resistance:
Q
DS

= =
1
1
v
i g
o
DS ds
r
Note: Evaluate small-signal parameters at DC operating point
small-signal parameter G
m
r
o

Small-signal
Circuit Model
triode/linear KV
DS
(1+V
DS
) small V
DS
: 1/[K(V
GS
-V
T
)]
saturation K(V
GS-
V
T
)(1+V
DS
) 1/[K(V
GS
-V
T
)
2
]

MOSFET Amplifier Analysis
(1) Large-signal analysis Find DC operating point w/ load-line analysis or method of assumed states.
(2) Small-signal analysis Zero out all DC sources, replace MOSFETs with small-signal model, and
find g
m
and r
o
for each MOSFET at the DC operating point.
To find voltage gain A
v
= v
out
/v
in
, solve for v
out
using KCL/KVL/nodal analysis.
To find R
in
and R
out
, zero out all independent sources and find R
th
at the input and the output (this
may require V
TEST
/I
TEST
method).
Common Source Amplifier
Large Signal Small Signal

A
v
=v
out
/v
in
= -g
m
(r
o
|| R
D
)
R
in
=
R
out
= r
o
|| R
D

XI. OP-AMPS
Operational amplifier high-gain voltage amplifier with differential inputs and single output
Circuit Symbol Circuit Model Input/Output Characteristic

V
o
= A(V
p
-V
n
), V
o
= [V
SS
,V
DD
] Note: V
o
cannot exceed the power supply rails V
DD
and V
SS
A = Gain, R
in
= input resistance, R
out
= output resistance
Ideal op-amp: A , R
in
, R
out
0
Negative Feedback since its hard to make the op-amp gain stable over all operating
conditions (the gain fluctuates with temperature, process variation, and power supply noise),
negative feedback is used to stabilize the op-amp output
negative feedback usually occurs when the output is connected to the negative input terminal
Suuming Point Constraint for ideal op-amp in negative feedback
(1) i
p
=i
n
=0 (since R
in
=) (2) v
p
=v
n
(for stable V
o
=A(V
p
-V
n
), A=)
Op-amp Analysis (1) Check for negative feedback. (2) Apply summing point constraint.
(3) Solve the circuit using circuit-analysis techniques (remember that V
o
cannot exceed the supply rails).
Op-amp Circuits
Inverting Amplifier Noninverting Amplifier Unity-gain Buffer

Adder Subtractor




1 =
in
out
V
V
1
2
R
R
V
V
in
out
=
2
1
1
R
R
V
V
in
out
+ =
( )
2 1
1
2
V V V
R
R
out
=

+ =
2 1
2
3
1
3
V V V
R
R
R
R
out
Integrators
( ) LC j
V
V
in
out
2
1

=
R L j V
V
in
out

1
=
RC j V
V
in
out

1
=
Differentiators
R L j
in
out
V
V
= ( ) LC j
in
out
V
V
2
=
RC j
in
out
V
V
=
Cascading Op-amp Circuits Find gain of each stage and multiply them together to get total gain
XII. DIGITAL CIRCUITS

analog: signals (voltage and current) are continuous with time
digital: signals are discrete (e.g., 0 and 1) advantage: less sensitive to noise, easier to transmit
Booelan Algebra Primitive Rules
Associative A + (B + C) = (A + B) + C A (B C) = (A B) C
Commutative A + B = B + A A B = B A
Distributive A + (B C) = (A + B) (A + C) A (B + C) = (A B) + (A C)
Identity A + 1 = 1 A 0 = 0
Identity A + 0 = A A 1 = A
Complement
A + A= 1 A A= 0
Idempotence A + A = A A A = A
Absorption A + (A B) = A A (A + B) = A
Absorption
A + ( A B) = A + B A ( A+ B) = A B

Common Gates (Note: Bubble means inversion)

DeMorgans Laws (AKA bubble pushing)
(1) B A B A + =

(2) B A B A = +
Truth Tables list output value for each input combination (2
n
entries for n inputs)
Sum of Products Form write output logic expression as sum (OR) of
products (ANDs), where each product corresponds to each 1 entry in the truth table
A B C Out
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
Ex: C B A C B A C B A Out + + =
MOSFET Switch Models (NMOS)
Ideal Switch Model Switch-Resistor Model

Noise Margins
Voltage Output High/Low:
V
OH
=F(V
OL
), V
OL
=F(V
OH
)
Voltage Input High/Low (V
IH
, V
w
IL
):
here voltage transfer curve slope=-1
N
L V
OL

oise Margin High/Low:
NM
H
= V
OH
V
IH

NM
L
= V
IL
V
OL
ogic Swing: V
OH
NMOS Inverter (Resistor Pull-up)

Loadline Analysis:
NMOS Inverter Disadvantages:
No rail-to-rail swing (low noise margins)
Large R
D
required to keep V
OL
low and power low [I=V
DD
/(R
D
+R
on
)]
Large R
D
means large area and slow transient response for V
out
=0V
DD

CMOS Inverter

Voltage-Transfer Characteristic:

Loadline
Analysis:
CMOS Inverter Advantages: Rail-to-rail swing (big noise margins)
No static power consumption (either NMOS or PMOS off)
NMOS Pass Strong 0, Weak 1 For V
in
=V
DD
: Since V
GS
V
Tn
for NMOS on and
V
GS
=V
DD
V
OUT
, V
DD
V
out
V
Tn
, V
out
V
DD
V
Tn
NMOS cant pass strong 1

PMOS Pass Strong 1 , Weak 0 (same analysis as above)

General CMOS Logic Gate Implementation

Pull-up network (PUN) and Pull-down n
(PDN) are complementary (only one is on at a
time), so V
out
is either V
DD
or GND (0 or 1)
PUN
etwork

and PDN are duals of each other (parallel
Procedure
transistors in one network are series transistors
in the other network)


: (1) Express logic as ( ) X F = , the NOT of some logic expression X.
ND, parallel NMOS=OR.

CMOS Inverter Propagation Delay delay from input to output due to output load capacitance

measured between 50%
put
use switch-resistor model for
high-to-low delay (NMOS on): low-to-high delay (PMOS on):

p
= (t
pHL
+t
pLH

eral CMOS Gate Delay
itch-resistor model, find R
eq
for PUN or PDN, t
p
=0.69R
eq
C
L

(2) Since F=0 when X=1, construct PDN from X. Series NMOS=A
(3) Construct the PUN as the dual of the PDN.

transition points of the in

and output signals

MOSFETs





t
pHL
=0.69R
n
C
L
t
pLH
=0.69R
p
C
L








average propagation delay: t )/2

Gen
replace MOSFETs with sw