Comparadores:

Comparador 1 bit: Comparador 2 bits

library IEEE;
use IEEE.std_logic_1164.all;
entity COMP1 is
port(
A: in std_logic;
B: in std_logic;
A_mayor_B : out std_logic;
A_igual_B : out std_logic;
A_menor_B : out std_logic);
end COMP1;
architecture arch1 of COMP1 is
begin
process (A,B)
begin
if A=B then
A_igual_B <= '1';
A_mayor_B <='0';
A_menor_B <='0';
elsif (A='1') and (B='0') then
A_igual_B <= '0';
A_mayor_B <='1';
A_menor_B <='0';
elsif (A='0') and (B='1') then
A_igual_B <= '0';
A_mayor_B <='0';
A_menor_B <='1';
end if;
end process;
end arch1;
library IEEE;
use IEEE.std_logic_1164.all;
entity COMP2 is
port(
A: in std_logic_vector(1 downto 0);
B: in std_logic_vector(1 downto 0);
A_igual_B: out std_logic;
A_mayor_B: out std_logic;
A_menor_B: out std_logic);
end COMP2;
architecture arch1 of COMP2 is
begin
process (A,B) begin
if (A(1)=B(1)) and (A(0)=B(0)) then
A_igual_B <='1';
A_mayor_B <='0';
A_menor_B <='0';
elsif (A(1)='1') and (B(1)='0') then
A_mayor_B <='1';
A_igual_B <='0';
A_menor_B <='0';
elsif (A(1)='0') and (B(1)='1') then
A_menor_B <='1';
A_mayor_B <='0';
A_igual_B <='0';
elsif (A(0)='1') and (B(0)='0') then
A_mayor_B <='1';
A_igual_B <='0';
A_menor_B <='0';
elsif (A(0)='0') and (B(0)='1') then
A_menor_B <='1';
A_mayor_B <='0';
A_igual_B <='0';
end if;
end process;
end arch1;