Austin Wahl

ECE 241 Lab Report Lab #10

Introduction
In this lab we created two separate finite state machines (FSM), one being a Moore machine and the
other a Mealy machine. These FSMs were to detect a pattern in a bit stream and output a 1 every time
the pattern was detected.
Process
To begin this lab a schematic needed to be designed for both the Mealy and Moore machines. Both of
these machines used positive-edge-triggered flip-flops, and logic gates to get from the current state to
the next state. Both of these machines also were programmed to apply the input on the falling edge of
the clock. Once the schematic for both of these machines were created and implemented using the
Xilinx software, a post-route simulation was completed. A bit stream of 0011010001010011was
simulated during the post-route simulation and the output was pulled high when a 010 was detected.
Both the Moore and Mealy machines gave the same output, but the difference was that the Mealy
machine output a 1 at the instance when the input was changing, and the Moore machine output a 1
when the next clock cycle began. This is because the Mealy machines output is dependent on input and
the current state while the Moore machines output is only dependent on the current state.
Conclusion
After the completion of this lab one Moore machine and one Mealy machine were created to detect the
same sequence in a bit stream. They both had the same output, but were output at different times due
to the design of the machines.