Aatreyo De Exp No.

5 118EC0805

National Institute of Technology (NIT), Rourkela

Dept. of Electronics and Communication Engg
EC 4715: VLSI Design Laboratory
Name : Aatreyo Shashwat De
Roll No. : 118EC0805
Exp. No. : 5
Date : 06.10.2021

AIM OF THE EXPERIMENT:

1. To detect 1001 sequence using Mealy FSM

2. To detect 1001 sequence using Moore FSM

SOFTWARE: Xilinx Vivado 2020.2

THEORY:

A finite-state machine (FSM) or finite-state automaton (FSA, plural:

automata), finite automaton, or simply a state machine, is a mathematical
model of computation. It is an abstract machine that can be in exactly
one of a finite number of states at any given time. The FSM can change
from one state to another in response to some inputs;

FSMs are of two types:

• Mealy FSM: Here, outputs are dependent on input and state of the
system.
• Moore FSM: Here, outputs depend solely on the state of the system,
irrespective of the inputs.

1. State Diagram of Mealy 1001 detector

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Design Source Code:

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Testbench Code:

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Schematic Diagram:

Waveforms:

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State Diagram of Moore 1001 detector:

Design Source Code:

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Testbench Code:

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Schematic Diagram

Waveforms:

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DISCUSSION :

As we can see Mealy FSM requires less number of states than Moore FSM
because, in Mealy FSM, there can be more that one path between two
states with different outputs depending on the input.

Here, the transition S3 -> S0 given Dout = 0 for Din = 0, Dout = 1 for
Din = 1.

In Moore machine, transition from a state must give same output

irrespective of the input. So, to detect the end of the sequence and
simultaneously return to start requires an extra state (S4).
It is triggered when the desired end bit arrives at the input.

Here, Din = 1 triggers the transition S3 -> S4, which then gives Dout =
1 on further transition to other states.

CONCLUSION:

A ‘1001’ detector was synthesized & simulated with Mealy and Moore
machine both using behavioral modelling in Vivado.
A thorough discussion on their algorithm, state and bits usage was
also presented.

The schematics obtained verify the logic diagrams.

Submitted By: Aatreyo De - 118EC0805