CD4094BMS: Pinout Features

CD4094BMS
CMOS 8-Stage Shift-and-Store

Bus Register
December 1992
Features
Pinout
High Voltage Type (20V Rating)
CD4094BMS
TOP VIEW
3-State Parallel Outputs for Connection to Common

Bus
Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading
16 VDD
STROBE 1
Medium Speed Operation - 5MHz at 10V (typ)
15 OUTPUT ENABLE
DATA 2
Standardized Symmetrical Output Characteristics
CLOCK
14 Q5
100% Tested for Quiescent Current at 20V
Q1
13 Q6
Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
Q2
12 Q7
Q3
11 Q8
Q4
10 QS
VSS
9 QS
Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, Standard Specifications for Description of
B Series CMOS Devices
Functional Diagram
Applications
Serial-to-Parallel Data Conversion
Remote Control Holding Register
DATA
CLOCK
STROBE
OUTPUT
ENABLE
15
Dual-Rank Shift, Hold, and Bus Applications
SERIAL
OUTPUTS
10 QS
8-STAGE
SHIFT
REGISTER
QS
Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The
same serial information, available at the QS terminal on the next
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow.
8-BIT
STORAGE
REGISTER
3-STATE
OUTPUTS
VDD = 16
VSS = 8
PARALLEL OUTPUTS Q1 - Q8
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
The CD4094BMS is supplied in these 16 lead outline packages:

Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
7-1083
File Number
3194
Specifications CD4094BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
SYMBOL
IDD
IIL
IIH
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
+25oC
10
+125 C
1000
-55oC
10
VIN = VDD or GND
+25oC
-100
nA
+125oC
-1000
nA
VDD = 18V
-55oC
-100
nA
VDD = 20
+25oC
100
nA
+125oC
1000
nA
-55oC
100
nA
50
mV
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC,
+125oC,
-55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
+25oC
0.53
mA
IOL10
+25oC
1.4
mA
IOL15
+25oC
3.5
mA
Output Current (Source)
IOH5A
+25oC
-0.53
mA
IOH5B
+25oC
-1.8
mA
IOH10
+25oC
-1.4
mA
mA
IOH15
VDD = 15V, VOUT = 13.5V
+25oC
-3.5
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10A
+25oC
-2.8
-0.7
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10A
+25oC
0.7
2.8
VDD = 2.8V, VIN = VDD or GND
+25oC
+25oC
8A
+125oC
8B
-55oC
Functional
VOH > VOL <

VDD/2 VDD/2
Input Voltage Low

(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
1.5
Input Voltage High

(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
Input Voltage Low

(Note 2)
VIL
VDD = 15V, VOH > 13.5V,

VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
Input Voltage High

(Note 2)
VIH
VDD = 15V, VOH > 13.5V,

VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
Tri-State Output
Leakage
IOZL
VIN = VDD or GND

VOUT = 0V
+25oC
-0.4
Tri-State Output
Leakage
IOZH
VIN = VDD or GND

VOUT = VDD
VDD = 20V
+125oC
-12
VDD = 18V
-55oC
-0.4
VDD = 20V
+25oC
0.4
+125oC
12
-55oC
0.4
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1084
3. For accuracy, voltage is measured differentially to VDD. Limit

is 0.050V max.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
Propagation Delay
Clock to Serial Output QS
TPHL1
TPLH1
GROUP A
SUBGROUPS TEMPERATURE
CONDITIONS
(Note 1, 2)
Propagation Delay
Clock to Serial Output
QS
TPHL2
TPLH2

(Note 1, 2)
Propagation Delay
Clock to Parallel Output
TPHL3
TPLH3

(Note 1, 2)
Propagation Delay
Strobe to Parallel Output
TPHL4
TPLH4

(Note 1, 2)
Propagation Delay
Output Enable to Parallel
Output
TPHZ
TPZH

(Note 2, 3)
Propagation Delay
Output
TPLZ
TPZL

(Note 2, 3)
Transition Time
TTHL
TTLH

(Note 1, 2)
Maximum Clock Input

Frequency
FCL

(Note 1, 2)
9
10, 11
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
600
ns
810
ns
460
ns
621
ns
+25oC
840
ns
10, 11
+125oC, -55oC
1134
ns
+25oC
580
ns
783
ns
10, 11
+125 C, -55 C
o
+25 C
280
ns
10, 11
+125oC, -55oC
378
ns
+25oC
200
ns
270
ns
200
ns
10, 11
9
10, 11
+125oC,
-55oC
+25oC
+125oC,
-55oC
270
ns
+25oC
1.25
MHz
10, 11
+125oC, -55oC
.93
MHz
MIN
MAX
UNITS
A
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
150
-55oC, +25oC
10
+125oC
300
10
+125oC
600
+25oC, +125oC,
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
IOL5
1, 2
+125oC
0.36
mA
-55oC
0.64
mA
IOL10
7-1085
1, 2
+125oC
0.9
mA
-55oC
1.6
mA
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
IOL15
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
2.4
mA
IOH5A
1, 2
-55 C
4.2
mA
+125oC
-0.36
mA
-0.64
mA
-55
IOH5B
IOH10
1, 2
1, 2
oC
+125oC
-1.1
mA
-55oC
-2.0
mA
+125oC
-0.9
mA
-2.6
mA
-2.4
mA
-55o
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125oC
oC
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
VDD = 10V
1, 2, 3
+25oC
250
ns
VDD = 15V
1, 2, 3
+25oC
190
ns
1, 2, 3
+25oC
220
ns
oC
150
ns
390
ns
1, 2, 3
+25 C
270
ns
VDD = 10V
1, 2, 3
+25
oC
290
ns
VDD = 15V
1, 2, 3
+25oC
200
ns
1, 2, 4
+25
oC
120
ns
90
ns
-55
Propagation Delay
Clock to Serial Output Qs
TPHL1
TPLH1
Propagation Delay
Clock to Serial Output Qs
TPHL2
TPLH2
VDD = 10V
VDD = 15V
1, 2, 3
+25
Propagation Delay
Clock to Parallel Output
TPHL3
TPLH3
VDD = 10V
1, 2, 3
+25oC
Propagation Delay
Strobe to Parallel Output
TPHL4
TPLH4
VDD = 15V
Propagation Delay
Output
TPHZ
TPZH
VDD = 10V
VDD = 15V
1, 2, 4
+25oC
Propagation Delay
Output
TPLZ
TPZL
VDD = 10V
1, 2, 4
+25oC
100
ns
VDD = 15V
1, 2, 4
+25oC
80
ns
Transition Time
TTLH
TTHL
VDD = 10V
1, 2, 3
+25oC
100
ns
1, 2, 3
+25
oC
80
ns
VDD = 10V
1, 2, 3
+25oC
2.5
MHz
VDD = 15V
1, 2, 3
+25oC
MHz
1, 2, 3
+25oC
125
ns
VDD = 10V
1, 2, 3
+25oC
55
ns
VDD = 15V
1, 2, 3
+25oC
35
ns
VDD = 5V
1, 2, 3, 5
+25oC
15
VDD = 10V
1, 2, 3, 5
+25oC
1, 2, 3, 5
+25oC
VDD = 5V
1, 2, 3
+25oC
200
ns
VDD = 10V
1, 2, 3
+25oC
100
ns
1, 2, 3
+25oC
83
ns
Maximum Clock Input

Frequency
Minimum Data Setup
Time
Maximum Clock Input

Rise and Fall Time
FCL
TS
TRCL
TFCL
VDD = 15V
VDD = 5V
VDD = 15V
Minimum Clock Pulse
Width
TW
VDD = 15V
7-1086
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Minimum Strobe Pulse
Width
Input Capacitance
SYMBOL
TW
CONDITIONS
VDD = 5V
CIN
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
200
ns
VDD = 10V
1, 2, 3
+25 C
80
ns
VDD = 15V
1, 2, 3
+25oC
70
ns
oC
7.5
pF
Any Input
1, 2
+25
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
1, 4
+25oC
25
1, 4
+25oC
-2.8
-0.2
VDD = 10V, ISS = -10A
1, 4
+25oC
VSS = 0V, IDD = 10A
1, 4
+25oC
0.2
2.8
1, 4
+25oC
+25oC
VOH >
VDD/2
VOL <
VDD/2
1, 2, 3, 4
+25oC
1.35 x
+25oC
Limit
ns
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
VTP
Functional
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A

Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.

4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
1.0A
IOL5
20% x Pre-Test Reading
IOH5A
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP
Initial Test (Pre Burn-In)
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
7-1087
READ AND RECORD

IDD, IOL5, IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
CONFORMANCE GROUP
PDA (Note 1)
PDA (Note 1)
Final Test
Group A
Group B
IDD, IOL5, IOH5A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
(Note 1)
4 - 7, 9 - 14
1 - 3, 8, 15
16
Static Burn-In 2
(Note 1)
4 - 7, 9 - 14
1 - 3, 15, 16
Dynamic BurnIn (Note 1)
1, 15, 16
4 - 7, 9 - 14
1 - 3, 15, 16
Irradiation
(Note 2)
9V -0.5V
50kHz
25kHz
4 - 7, 9 - 14
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V 0.5V
7-1088
CD4094BMS
SERIAL
IN
CL
p
SERIAL
OUT
*
D
2
CL
CL
D
CL
CL
D
CL
CL
10
n
QS
8
Q
CL
CL
p
p n
CLOCK
TR
*
CL
STAGES
3-7
CL
SERIAL
OUT
CL
STROBE
TR
TR
QS
TR
TR
TR
OUTPUT
ENABLE
TR
TR
LATCH
2
TR
LATCH
1
TR
LATCH
8
VDD
*
15
3-STATE
1
3STATE
2
3STATE
8
VDD
VSS
* ALL INPUTS
PROTECTED BY
CMOS PROTECTION
NETWORK
VSS
4
Q1
Q2
14 13 12
11
Q3 Q4 Q5 Q6 Q7
Q8
FIGURE 1. LOGIC DIAGRAM

TRUTH TABLE
CL
PARALLEL OUTPUTS
SERIAL OUTPUTS
OUTPUT
ENABLE
STROBE
DATA
Q1
QN
QS*
QS
OC
OC
Q7
NC
OC
OC
NC
Q7
NC
NC
Q7
NC
QN-1
Q7
NC
QN-1
Q7
NC
NC
NC
NC
Q7
= Level Change
Logic 1 = High
X = Dont Care
Logic 0 = Low
NC = No Change
OC = Open Circuit
* At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage
and the QS output
7-1089
CD4094BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
10
15
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT

TRANSFER CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

-15
-10
-5

-15
-10
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-5
-10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V

300
10V
15V
20
-15
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS
400
-10
-15V
100
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS
200
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
300
250
200
150
10V
100
15V
50
FIGURE 6. CLOCK-TO-SERIAL OUTPUT QS PROPAGATION

DELAY vs CL
20
40
60
80
100
FIGURE 7. CLOCK-TO-SERIAL OUTPUT QS PROPAGATION

DELAY vs CL
7-1090
CD4094BMS
(Continued)
600
Typical Performance Characteristics

500
400
300
10V
200
15V
100
20

300
200
10V
100
15V
20
40
60
80
100
FIGURE 9. STROBE-TO-PARALLEL OUTPUT PROPAGATION

DELAY vs CL
300
tPHL
250
tPLH
TRANSITION TIME (tTHL, tTLH) (ns)
400
40
60
80
100
FIGURE 8. CLOCK-TO-PARALLEL OUTPUT PROPAGATION

DELAY vs CL
200
10V
5V
10V
15V
15V
150
100
50
20
150
100
10V
5V
50
0
0
20
40
60
80
100
POWER DISSIPATION /PACKAGE (PD) (W)
FIGURE 11. TYPICAL TRANSITION TIME vs LOAD

CAPACITANCE
+25oC
AMBIENT TEMPERATURE (TA) =

LOAD CAPACITANCE (CL) = 50PF
15
200
40
60
80
100
FIGURE 10. OUTPUT ENABLE-TO-PARALLEL OUTPUT

PROPAGATION DELAY vs CL
MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz)
10

ALTERNATING 0 AND 1 PATTERN
OUTPUT ENABLE HIGH
STROBE HIGH EVERY 8 CLOCK PULSES
106
105
104
10V
103
10V
5V
102
CL = 50pF
CL = 15pF
10
0
10
15
SUPPLY VOLTAGE (VDD) (V)
20
FIGURE 12. TYPICAL MAXIMUM-CLOCK-FREQUENCY vs

SUPPLY VOLTAGE
10
102
103
104
105
INPUT FREQUENCY (fI) (kHz)
FIGURE 13. DYNAMIC POWER DISSIPATION vs INPUT CLOCK

FREQUENCY
7-1091
CD4094BMS
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
INTERNAL Q1
3 - STATE
3
STATE
OUTPUT Q1
INTERNAL Q7
3 - STATE
3
STATE
OUTPUT Q7
SERIAL QS
OUTPUT
SERIAL QS
OUTPUT
FIGURE 14. TIMING DIAGRAM
DIGITALLY CONTROLLED
EQUIPMENT
(REQUIRES CONTINUOUS
DIGITAL CONTROL)
CD4094BMS
STROBE
CLOCK
EQUIPMENT
QS
CD4094BMS
STROBE
EQUIPMENT
QS
CLOCK
CONTROL
AND
SYNC
CIRCUITRY
DATA CLOCK
FROM REMOTE
CONTROL PANEL
FIGURE 15. REMOTE CONTROL HOLDING REGISTER
7-1092
CD4094BMS
STROBE
CLOCK
CD4094BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11k 14k,
AL.
10.4k - 15.6k, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
1093
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

CD4094BMS: Pinout Features

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CD4094BMS: Pinout Features

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CD4094BMS

CMOS 8-Stage Shift-and-Store

High Voltage Type (20V Rating)

3-State Parallel Outputs for Connection to Common

Medium Speed Operation - 5MHz at 10V (typ)

Standardized Symmetrical Output Characteristics

100% Tested for Quiescent Current at 20V

Noise Margin (Over Full Package/Temperature Range)

Dual-Rank Shift, Hold, and Bus Applications

The CD4094BMS is supplied in these 16 lead outline packages:

Frit Seal DIP

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Input Leakage Current

Input Leakage Current

VDD = 18V, VIN = VDD or GND

VIN = VDD or GND

VIN = VDD or GND

VDD = 15V, No Load

VDD = 15V, No Load (Note 3)

+25oC, +125oC, -55oC 14.95

Output Current (Sink)

VDD = 5V, VOUT = 0.4V

Output Current (Sink)

VDD = 10V, VOUT = 0.5V

Output Current (Sink)

VDD = 15V, VOUT = 1.5V

Output Current (Source)

VDD = 5V, VOUT = 4.6V

Output Current (Source)

VDD = 5V, VOUT = 2.5V

Output Current (Source)

VDD = 10V, VOUT = 9.5V

Output Current (Source)

VDD = 15V, VOUT = 13.5V

VDD = 10V, ISS = -10A

VSS = 0V, IDD = 10A

VDD = 2.8V, VIN = VDD or GND

VDD = 20V, VIN = VDD or GND

VDD = 18V, VIN = VDD or GND

VDD = 3V, VIN = VDD or GND

VOH > VOL <

Input Voltage Low

VDD = 5V, VOH > 4.5V, VOL < 0.5V

+25oC, +125oC, -55oC

Input Voltage High

VDD = 5V, VOH > 4.5V, VOL < 0.5V

+25oC, +125oC, -55oC

Input Voltage Low

VDD = 15V, VOH > 13.5V,

+25oC, +125oC, -55oC

Input Voltage High

VDD = 15V, VOH > 13.5V,

+25oC, +125oC, -55oC

VIN = VDD or GND

VIN = VDD or GND

3. For accuracy, voltage is measured differentially to VDD. Limit

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND