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Theory
Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design,
Addison-Wesley, 3/e, 2004
Outline
MOS Structure
Gate and body form
MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
No channel
Ids = 0
pMOS Transistor
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Channel Charge
MOS structure looks like parallel
plate capacitor while operating in
inversion:
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = coxWL
V = Vgc Vt = (Vgs Vds/2) Vt
cox = ox / tox
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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral
E-field between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v
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I ds =
= Cox
W
L
V V Vds
gs
t
2
V
= Vgs Vt ds Vds
2
V
ds
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(V
2
gs
Vt )
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V
I ds = Vgs Vt ds
2
2
V
V
(
)
gs
t
Vgs < Vt
V V < V
ds
ds
dsat
cutoff
linear
saturation
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Example
0.6 m process from AMI Semiconductor
2.5
Vgs = 5
2
Ids (mA)
tox = 100
m = 350 cm2/V*s
Vt = 0.7 V
1.5
Vgs = 4
Vgs = 3
0.5
0
Vgs = 2
Vgs = 1
Vds
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V
I ds = Vgs Vt ds
2
2
Vgs Vt )
(
Vgs < Vt
V V < V
ds
ds
dsat
cutoff
linear
saturation
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Gate Capacitance
Gate Capacitance
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Linear
Saturation
Cgb (total)
C0
Cgd (total)
CoxWLD
C0/2 + CoxWLD
CoxWLD
Cgs (total)
CoxWLD
C0/2 + CoxWLD
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Diffusion Capacitance
Csb, Cdb
Undesired capacitance (parasitic)
Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
Capacitance depends on area and
perimeter
Use small diffusion nodes
Comparable to Cg for
contacted diffusion
Cg for uncontacted
Varies with process
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Body Effect
The potential difference between source and
body Vsb affects (increases) the threshold
voltage
Threshold voltage depends on:
Vsb
Process
Doping
Temperature
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Subthreshold Conduction
The ideal transistor I-V model assumes current only flows
from source to drain when Vgs > Vt.
In real transistors, current doesnt abruptly cut off below
threshold, but rather drop off exponentially
This leakage current when the transistor is nominally OFF
depends on:
process (ox, tox)
doping levels (NA, or ND)
device geometry (W, L)
temperature (T)
( Subthreshold voltage (Vt) )
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Junction Leakage
The p-n junctions between diffusion and the substrate or
well for diodes.
The well-to-substrate is another diode
Substrate and well are tied to GND and VDD to ensure
these diodes remain reverse biased
But, reverse biased diodes still conduct a small amount of
current that depends on:
Doping levels
Area and perimeter of the diffusion region
The diode voltage
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Tunneling
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Temperature dependence
Transistor characteristics are
influenced by temperature
decreases with T
Vt decreases linearly with T
Ileakage increases with T
ON current decreases with T
OFF current increases with T
Thus, circuit performances are
worst at high temperature
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Geometry Dependence
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Pass Transistors
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded 1
Approach degraded value slowly (low Ids)
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Tri-state Inverter
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RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
or maybe 1 m wide device
Doesnt matter as long as you are consistent
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RC Delay Models
Use equivalent circuits for MOS transistors
ideal switch + capacitance and ON resistance
unit nMOS has resistance R, capacitance C
unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
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delay = 6RC
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Summary
Models are only approximations to reality, not reality itself
Models cannot be perfectly accurate
Little value in using excessively complicated models, particularly
for hand calculations
To first order current is proportional to W/L
But, in modern transistors Leff is shorter than Ldrawn
Doubling the Ldrawn reduces current more than a factor of two
Two series transistors in a modern process deliver more than half
the current of a single transistor
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