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Pic16F627A/628A/648A Data Sheet: Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology
Pic16F627A/628A/648A Data Sheet: Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology
Data Sheet
Flash-Based, 8-Bit CMOS
Microcontrollers with nanoWatt Technology
DS40044F
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Companys quality system processes and procedures are for its PIC
MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchips quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS40044F-page ii
PIC16F627A/628A/648A
18-pin Flash-Based, 8-Bit CMOS Microcontrollers
with nanoWatt Technology
High-Performance RISC CPU:
Low-Power Features:
Standby Current:
- 100 nA @ 2.0V, typical
Operating Current:
- 12 A @ 32 kHz, 2.0V, typical
- 120 A @ 1 MHz, 2.0V, typical
Watchdog Timer Current:
- 1 A @ 2.0V, typical
Timer1 Oscillator Current:
- 1.2 A @ 32 kHz, 2.0V, typical
Dual-speed Internal Oscillator:
- Run-time selectable between 4 MHz and
48 kHz
- 4 s wake-up from Sleep, 3.0V, typical
Device
Program
Memory
Peripheral Features:
16 I/O pins with individual direction control
High current sink/source for direct LED drive
Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Selectable internal or external reference
- Comparator outputs are externally accessible
Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Timer1: 16-bit timer/counter with external crystal/
clock capability
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM module:
- 16-bit Capture/Compare
- 10-bit PWM
Addressable Universal Synchronous/Asynchronous
Receiver/Transmitter USART/SCI
Data Memory
I/O
CCP
(PWM)
128
16
2/1
128
16
2/1
256
16
2/1
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F627A
1024
224
PIC16F628A
2048
224
PIC16F648A
4096
256
USART Comparators
Timers
8/16-bit
DS40044F-page 1
PIC16F627A/628A/648A
Pin Diagrams
PDIP, SOIC
18
RA1/AN1
RA3/AN3/CMP1
17
RA0/AN0
16
RA7/OSC1/CLKIN
15
RA6/OSC2/CLKOUT
14
VDD
13
RB7/T1OSI/PGD
RA5/MCLR/VPP
PIC16F627A/628A/648A
RA4/T0CKI/CMP2
27A/628A/648A
RB0/INT
RB1/RX/DT
12
RB6/T1OSO/T1CKI/PGC
RB2/TX/CK
11
RB5
RB3/CCP1
10
RB4/PGM
RA5/MCLR/VPP
DS40044F-page 2
RA1/AN1
RA0/AN0
1
21
NC 2
20
VSS
3
19
NC 4 PIC16F627A/628A 18 NC
PIC16F648A
VSS
17
5
NC 6
16
RB0/INT
7
15
8
9
10
NC 11
12
RB4/PGM
13
RB5
NC 14
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
VSS
VSS
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
1
2
3
4
5
6
7
8
9
10
PIC16F627A/628A/648A
28
27
26
25 NC
24
23
22 NC
RA4/T0CKI/CMP2
RA3/AN3/CMP1
RA2/AN2/VREF
28-Pin QFN
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5
RB4/PGM
VSS
20
19
18
17
16
15
14
13
12
11
SSOP
RA2/AN2/VREF
PIC16F627A/628A/648A
Table of Contents
1.0 General Description..................................................................................................................................................................... 5
2.0 PIC16F627A/628A/648A Device Varieties .................................................................................................................................. 7
3.0 Architectural Overview ................................................................................................................................................................ 9
4.0 Memory Organization ................................................................................................................................................................ 15
5.0 I/O Ports .................................................................................................................................................................................... 31
6.0 Timer0 Module .......................................................................................................................................................................... 45
7.0 Timer1 Module .......................................................................................................................................................................... 48
8.0 Timer2 Module .......................................................................................................................................................................... 52
9.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 55
10.0 Comparator Module................................................................................................................................................................... 61
11.0 Voltage Reference Module........................................................................................................................................................ 67
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module....................................................................... 71
13.0 Data EEPROM Memory ............................................................................................................................................................ 89
14.0 Special Features of the CPU..................................................................................................................................................... 95
15.0 Instruction Set Summary ......................................................................................................................................................... 115
16.0 Development Support.............................................................................................................................................................. 129
17.0 Electrical Specifications........................................................................................................................................................... 133
18.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 149
19.0 Packaging Information............................................................................................................................................................. 161
Appendix A: Revision History............................................................................................................................................................ 167
Appendix B: Device Differences ....................................................................................................................................................... 167
Appendix C: Device Migrations - PIC16C63/65A/73A/74A > PIC16C63A/65B/73B/74B .............................................................. 168
Appendix D: Migration from Baseline to Mid-Range Devices ........................................................................................................... 168
The Microchip Web Site .................................................................................................................................................................... 169
Customer Change Notification Service ............................................................................................................................................. 169
Customer Support ............................................................................................................................................................................. 169
Reader Response ............................................................................................................................................................................. 170
Product Identification System ........................................................................................................................................................... 175
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40044F-page 3
PIC16F627A/628A/648A
NOTES:
DS40044F-page 4
PIC16F627A/628A/648A
1.0
GENERAL DESCRIPTION
TABLE 1-1:
Clock
Memory
Peripherals
1.1
Development Support
PIC16F628A
PIC16F648A
PIC16LF627A
PIC16LF628A
PIC16LF648A
20
20
20
20
20
20
Flash Program
Memory (words)
1024
2048
4096
1024
2048
4096
224
224
256
224
224
256
EEPROM Data
Memory (bytes)
128
128
256
128
128
256
Timer module(s)
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
Comparator(s)
Capture/Compare/
PWM modules
USART
USART
USART
USART
USART
USART
Yes
Yes
Yes
Yes
Yes
Yes
Maximum Frequency
of Operation (MHz)
Serial Communications
Internal Voltage
Reference
Features
Interrupt Sources
10
10
10
10
10
10
I/O Pins
16
16
16
16
16
16
3.0-5.5
3.0-5.5
3.0-5.5
2.0-5.5
2.0-5.5
2.0-5.5
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
All PIC family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability.
All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7.
DS40044F-page 5
PIC16F627A/628A/648A
NOTES:
DS40044F-page 6
PIC16F627A/628A/648A
2.0
PIC16F627A/628A/648A
DEVICE VARIETIES
2.1
Flash Devices
2.2
Quick-Turnaround-Production
(QTP) Devices
2.3
DS40044F-page 7
PIC16F627A/628A/648A
NOTES:
DS40044F-page 8
PIC16F627A/628A/648A
3.0
ARCHITECTURAL OVERVIEW
TABLE 3-1:
Device
Flash
Program
RAM
Data
EEPROM
Data
PIC16F627A
1024 x 14
224 x 8
128 x 8
PIC16F628A
2048 x 14
224 x 8
128 x 8
PIC16F648A
4096 x 14
256 x 8
256 x 8
PIC16LF627A
1024 x 14
224 x 8
128 x 8
PIC16LF628A
2048 x 14
224 x 8
128 x 8
PIC16LF648A
4096 x 14
256 x 8
256 x 8
DS40044F-page 9
PIC16F627A/628A/648A
FIGURE 3-1:
BLOCK DIAGRAM
13
Flash
Program
Memory
RAM
File
Registers
8-Level Stack
(13-bit)
Program
Bus
14
Data Bus
Program Counter
PORTA
Addr MUX
Instruction Reg
Direct Addr
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Indirect
Addr
FSR Reg
Status Reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W Reg
PORTB
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Low-Voltage
Programming
MCLR
Comparator
Timer0
VREF
CCP1
Note
1:
VDD, VSS
Timer1
USART
Timer2
Data EEPROM
DS40044F-page 10
PIC16F627A/628A/648A
TABLE 3-2:
Name
Function
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
Description
RA0
ST
AN0
AN
RA1
ST
CMOS
AN1
AN
RA2
ST
CMOS
AN2
AN
VREF
AN
VREF output
RA3
ST
CMOS
AN3
AN
CMP1
CMOS
Comparator 1 output
RA4
ST
OD
T0CKI
ST
CMP2
OD
Comparator 2 output
RA5
ST
Input port
MCLR
ST
VPP
RA6
ST
CMOS
OSC2
XTAL
CLKOUT
CMOS
RA7
ST
CMOS
OSC1
XTAL
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
CLKIN
ST
RB0/INT
RB0
TTL
CMOS
INT
ST
RB1/RX/DT
RB1
TTL
CMOS
RX
ST
DT
ST
CMOS
RB2
TTL
CMOS
RB2/TX/CK
RB3/CCP1
O = Output
= Not used
TTL = TTL Input
External interrupt
Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
USART receive pin
TX
CMOS
CK
ST
CMOS
RB3
TTL
CMOS
ST
CMOS
Capture/Compare/PWM I/O
CCP1
Legend:
P = Power
ST = Schmitt Trigger Input
AN = Analog
DS40044F-page 11
PIC16F627A/628A/648A
TABLE 3-2:
Name
RB4/PGM
Function
Description
RB4
TTL
CMOS
PGM
ST
RB5
RB5
TTL
CMOS
RB6/T1OSO/T1CKI/PGC
RB6
TTL
CMOS
T1OSO
XTAL
T1CKI
ST
PGC
ST
RB7
TTL
CMOS
T1OSI
XTAL
PGD
ST
CMOS
VSS
VSS
Power
VDD
VDD
Power
RB7/T1OSI/PGD
Legend:
O = Output
= Not used
TTL = TTL Input
DS40044F-page 12
P = Power
ST = Schmitt Trigger Input
AN = Analog
PIC16F627A/628A/648A
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC + 1
PC + 2
CLKOUT
Fetch INST (PC)
Execute INST (PC - 1)
EXAMPLE 3-1:
1. MOVLW 55h
Fetch 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, 3
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
Note:
All instructions are single cycle except for any program branches. These take two cycles since the fetch
instruction is flushed from the pipeline while the new instruction is being fetched and then executed.
DS40044F-page 13
PIC16F627A/628A/648A
NOTES:
DS40044F-page 14
PIC16F627A/628A/648A
4.0
MEMORY ORGANIZATION
4.1
4.2
TABLE 4-1:
Bank0
FIGURE 4-1:
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
On-chip Program
Memory
PIC16F648A
20-7Fh
20-7Fh
Bank1
A0h-FF
A0h-FF
Bank2
120h-14Fh, 170h-17Fh
120h-17Fh
Bank3
1F0h-1FFh
1F0h-1FFh
Stack Level 8
Interrupt Vector
PIC16F627A/628A
13
Reset Vector
TABLE 4-2:
000h
0004
0005
4.2.1
PIC16F627A,
PIC16F628A and
PIC16F648A
03FFh
On-chip Program
Memory
PIC16F628A and
PIC16F648A
ACCESS TO BANKS OF
REGISTERS
Bank
RP1
RP0
07FFh
On-chip Program
Memory
PIC16F648A only
0FFFh
1FFFh
DS40044F-page 15
PIC16F627A/628A/648A
FIGURE 4-2:
Indirect addr.(1)
00h
Indirect addr.(1)
80h
Indirect addr.(1)
100h
Indirect addr.(1)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PCL
105h
PORTB
106h
185h
TRISB
186h
07h
87h
107h
187h
08h
88h
108h
188h
89h
109h
09h
189h
8Ah
PCLATH
10Ah
PCLATH
18Ah
8Bh
INTCON
10Bh
INTCON
18Bh
PCLATH
0Ah
INTCON
0Bh
PCLATH
INTCON
PIR1
0Ch
PIE1
8Ch
10Ch
18Ch
8Dh
10Dh
18Dh
8Eh
10Eh
18Eh
10Fh
18Fh
0Dh
TMR1L
0Eh
TMR1H
0Fh
8Fh
T1CON
10h
90h
TMR2
11h
T2CON
12h
PCON
91h
PR2
92h
13h
93h
14h
94h
CCPR1L
15h
95h
CCPR1H
16h
96h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
99h
RCREG
1Ah
SPBRG
EEDATA
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
1Eh
CMCON
1Fh
9Ah
9Eh
VRCON
20h
9Fh
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
General
Purpose
Register
48 Bytes
11Fh
120h
14Fh
150h
80 Bytes
6Fh
70h
16 Bytes
accesses
70h-7Fh
7Fh
Bank 0
EFh
F0h
accesses
70h-7Fh
1EFh
1F0h
accesses
70h-7Fh
17Fh
FFh
Bank 1
16Fh
170h
Bank 2
1FFh
Bank 3
DS40044F-page 16
PIC16F627A/628A/648A
FIGURE 4-3:
Indirect addr.(1)
00h
Indirect addr.(1)
80h
Indirect addr.(1)
100h
Indirect addr.(1)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PCL
105h
PORTB
106h
185h
TRISB
186h
07h
87h
107h
187h
08h
88h
108h
188h
89h
109h
189h
09h
8Ah
PCLATH
10Ah
PCLATH
18Ah
8Bh
INTCON
10Bh
INTCON
18Bh
PCLATH
0Ah
PCLATH
INTCON
0Bh
INTCON
PIR1
0Ch
PIE1
8Ch
10Ch
18Ch
8Dh
10Dh
18Dh
8Eh
10Eh
18Eh
10Fh
18Fh
0Dh
TMR1L
0Eh
TMR1H
0Fh
8Fh
T1CON
10h
90h
TMR2
11h
T2CON
12h
PCON
91h
PR2
92h
13h
93h
14h
94h
CCPR1L
15h
95h
CCPR1H
16h
96h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
99h
RCREG
1Ah
SPBRG
EEDATA
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
1Eh
CMCON
1Fh
9Ah
9Eh
VRCON
20h
9Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
11Fh
120h
A0h
80 Bytes
6Fh
70h
16 Bytes
accesses
70h-7Fh
7Fh
Bank 0
EFh
F0h
accesses
70h-7Fh
1EFh
1F0h
accesses
70h-7Fh
17Fh
FFh
Bank 1
16Fh
170h
Bank 2
1FFh
Bank 3
DS40044F-page 17
PIC16F627A/628A/648A
4.2.2
The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
28
01h
TMR0
xxxx xxxx
45
0000 0000
28
02h
PCL
03h
STATUS
04h
FSR
IRP
RP1
RP0
TO
PD
DC
0001 1xxx
22
xxxx xxxx
28
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx 0000
31
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
36
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
---0 0000
28
0Ah
PCLATH
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
24
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
0000 -000
26
0Dh
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
48
xxxx xxxx
48
0Fh
TMR1H
10h
T1CON
11h
TMR2
12h
T2CON
13h
Unimplemented
14h
Unimplemented
xxxx xxxx
55
xxxx xxxx
55
15h
T1CKPS1
T1CKPS0
TOUTPS3
TOUTPS2 TOUTPS1
16h
CCPR1H
CCP1CON
18h
RCSTA
T1SYNC
TMR1CS
TMR1ON
CCPR1L
17h
T1OSCEN
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
--00 0000
48
0000 0000
52
-000 0000
52
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
55
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
72
19h
TXREG
0000 0000
77
1Ah
RCREG
0000 0000
80
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh
Unimplemented
0000 0000
61
1Fh
Legend:
Note 1:
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044F-page 18
PIC16F627A/628A/648A
TABLE 4-4:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
xxxx xxxx
28
1111 1111
23
0000 0000
28
0001 1xxx
22
xxxx xxxx
28
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
31
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
36
87h
Unimplemented
88h
Unimplemented
89h
Unimplemented
---0 0000
28
8Ah
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
RP1
RP0
TO
PD
DC
PCLATH
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
24
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
0000 -000
25
OSCF
POR
BOR
---- 1-0x
27
8Dh
8Eh
PCON
8Fh
Unimplemented
90h
Unimplemented
91h
Unimplemented
1111 1111
52
92h
PR2
Unimplemented
93h
Unimplemented
94h
Unimplemented
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
98h
TXSTA
0000 -010
71
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
99h
SPBRG
0000 0000
73
9Ah
EEDATA
xxxx xxxx
89
9Bh
EEADR
xxxx xxxx
90
9Ch
EECON1
---- x000
90
9Dh
EECON2
---- ----
90
9Eh
WRERR
WREN
WR
RD
VRR
000- 0000
67
9Fh
VRCON
Legend:
Note 1:
- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
VROE
VR3
VR2
VR1
VR0
DS40044F-page 19
PIC16F627A/628A/648A
TABLE 4-5:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
28
101h
TMR0
xxxx xxxx
45
102h
PCL
0000 0000
28
103h
STATUS
0001 1xxx
22
104h
FSR
xxxx xxxx
28
IRP
RP1
RP0
TO
PD
DC
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
Unimplemented
xxxx xxxx
36
Unimplemented
Unimplemented
Unimplemented
---0 0000
28
RB7
RB6
RB5
GIE
PEIE
T0IE
RB4
RB3
RB2
RB1
RB0
0000 000x
24
10Ch
Unimplemented
10Dh
Unimplemented
10Eh
Unimplemented
10Fh
Unimplemented
110h
Unimplemented
111h
Unimplemented
112h
Unimplemented
113h
Unimplemented
114h
Unimplemented
115h
Unimplemented
116h
Unimplemented
117h
Unimplemented
118h
Unimplemented
119h
Unimplemented
11Ah
Unimplemented
11Bh
Unimplemented
11Ch
Unimplemented
11Dh
Unimplemented
11Eh
Unimplemented
11Fh
Unimplemented
Legend:
Note 1:
INTE
RBIE
T0IF
INTF
RBIF
- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044F-page 20
PIC16F627A/628A/648A
TABLE 4-6:
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 3
180h
INDF
181h
OPTION
182h
PCL
183h
STATUS
184h
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
RP1
RP0
TO
PD
DC
185h
186h
TRISB
187h
188h
189h
18Ah
PCLATH
18Bh
INTCON
Unimplemented
1111 1111
28
23
0000 0000
28
0001 1xxx
22
xxxx xxxx
28
1111 1111
36
Unimplemented
Unimplemented
Unimplemented
---0 0000
28
TRISB7
TRISB6
TRISB5
GIE
PEIE
T0IE
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
0000 000x
24
18Ch
Unimplemented
18Dh
Unimplemented
18Eh
Unimplemented
18Fh
Unimplemented
190h
Unimplemented
191h
Unimplemented
192h
Unimplemented
193h
Unimplemented
194h
Unimplemented
195h
Unimplemented
196h
Unimplemented
197h
Unimplemented
198h
Unimplemented
199h
Unimplemented
19Ah
Unimplemented
19Bh
Unimplemented
19Ch
Unimplemented
19Dh
Unimplemented
19Eh
Unimplemented
19Fh
Unimplemented
Legend:
Note 1:
INTE
RBIE
T0IF
INTF
RBIF
- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044F-page 21
PIC16F627A/628A/648A
4.2.2.1
Status Register
REGISTER 4-1:
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
DC
bit 7
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for Borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
DS40044F-page 22
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
4.2.2.2
OPTION Register
Note:
REGISTER 4-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 23
PIC16F627A/628A/648A
4.2.2.3
INTCON Register
Note:
REGISTER 4-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40044F-page 24
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
4.2.2.4
PIE1 Register
REGISTER 4-4:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 25
PIC16F627A/628A/648A
4.2.2.5
PIR1 Register
Note:
REGISTER 4-5:
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40044F-page 26
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
4.2.2.6
PCON Register
REGISTER 4-6:
Note:
U-0
U-0
U-0
R/W-1
U-0
R/W-0
R/W-x
OSCF
POR
BOR
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 27
PIC16F627A/628A/648A
4.3
FIGURE 4-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
4.4
PCH
PCL
12
PC
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
EXAMPLE 4-1:
4.3.1
COMPUTED GOTO
4.3.2
NEXT
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
STACK
DS40044F-page 28
PIC16F627A/628A/648A
FIGURE 4-5:
Status
Register
RP1 RP0
Direct Addressing
6
from opcode
bank select
location select
00
00h
Indirect Addressing
7
bank select
01
10
FSR Register
location select
11
180h
RAM
File
Registers
7Fh
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.
DS40044F-page 29
PIC16F627A/628A/648A
NOTES:
DS40044F-page 30
PIC16F627A/628A/648A
5.0
I/O PORTS
5.1
EXAMPLE 5-1:
PORTA
MOVLW
MOVWF
0x07
CMCON
BCF
BSF
MOVLW
STATUS, RP1
STATUS, RP0 ;Select Bank1
0x1F
;Value used to initialize
;data direction
TRISA
;Set RA<4:0> as inputs
;TRISA<5> always
;read as 1.
;TRISA<7:6>
;depend on oscillator
;mode
MOVWF
;Initialize PORTA by
;setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
FIGURE 5-1:
Data
Bus
WR
PORTA
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
Q
CK
VDD
Data Latch
D
WR
TRISA
Q
CK
RD
TRISA
I/O Pin
TRIS Latch
INITIALIZING PORTA
CLRF
Analog
Input Mode
(CMCON Reg.)
VSS
Schmitt Trigger
Input Buffer
D
EN
RD PORTA
To Comparator
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high-impedance output. The user must configure
TRISA<2> bit as an input and use high-impedance
loads.
DS40044F-page 31
PIC16F627A/628A/648A
FIGURE 5-2:
Data
Bus
BLOCK DIAGRAM OF
RA2/AN2/VREF PIN
WR
PORTA
Q
CK
VDD
Data Latch
D
WR
TRISA
Q
RA2 Pin
CK
Analog
Input Mode
(CMCON Reg.)
TRIS Latch
RD
TRISA
VSS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
VROE
VREF
FIGURE 5-3:
Data
Bus
Comparator Output
WR
PORTA
CK
Data Latch
D
WR
TRISA
VDD
Q
RA3 Pin
CK
Analog
Input Mode
(CMCON Reg.)
TRIS Latch
RD
TRISA
VSS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
DS40044F-page 32
PIC16F627A/628A/648A
FIGURE 5-4:
Data
Bus
(CMCON Reg.)
Q
Comparator Output
WR
PORTA
CK
Q
0
Data Latch
D
WR
TRISA
Q
RA4 Pin
CK
Q
Vss
Vss
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
FIGURE 5-5:
BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
From OSC1
OSC
Circuit
1
MCLR Filter
WR
PORTA
Schmitt Trigger
Input Buffer
HV Detect
RA5/MCLR/VPP
Data
Bus
VSS
CK Q
FOSC =
Data Latch
(2)
101, 111
WR
TRISA
VSS
CK Q
TRIS Latch
RD
TRISA
RD
TRISA
VDD
CLKOUT(FOSC/4)
MCLR
circuit
Program
mode
FIGURE 5-6:
FOSC =
011, 100, 110 (1)
VSS
Q
Schmitt
Trigger
Input Buffer
EN
EN
RD
PORTA
RD PORTA
Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with
RA6 = CLKOUT.
DS40044F-page 33
PIC16F627A/628A/648A
FIGURE 5-7:
To Clock Circuits
VDD
Data Bus
WR PORTA
Q
RA7/OSC1/CLKIN Pin
CK
Data Latch
D
WR TRISA
CK
VSS
Q
Q
TRIS Latch
RD TRISA
FOSC = 100, 101(1)
D
EN
Schmitt Trigger
Input Buffer
RD PORTA
Note 1:
DS40044F-page 34
PIC16F627A/628A/648A
TABLE 5-1:
PORTA FUNCTIONS
Name
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Legend:
Function
Input
Type
Output
Type
RA0
ST
CMOS
AN0
AN
RA1
ST
CMOS
AN1
AN
RA2
ST
CMOS
AN2
AN
VREF
AN
VREF output
RA3
ST
CMOS
AN3
AN
CMP1
CMOS
RA4
ST
OD
T0CKI
ST
CMP2
OD
Comparator 2 output
RA5
ST
Input port
MCLR
ST
VPP
HV
RA6
ST
CMOS
OSC2
XTAL
CLKOUT
CMOS
RA7
ST
CMOS
OSC1
XTAL
CLKIN
ST
O = Output
= Not used
TTL = TTL Input
TABLE 5-2:
Description
P = Power
ST = Schmitt Trigger Input
AN = Analog
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
05h
PORTA
RA7
RA6
RA5(1)
RA4
RA3
RA2
RA1
RA0
xxxx 0000
qqqu 0000
85h
TRISA
1111 1111
1111 1111
1Fh
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
9Fh
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend:
- = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition. Shaded cells
are not used for PORTA.
MCLRE configuration bit sets RA5 functionality.
Address
Note 1:
DS40044F-page 35
PIC16F627A/628A/648A
5.2
FIGURE 5-8:
BLOCK DIAGRAM OF
RB0/INT PIN
VDD
RBPU
P Weak Pull-up
VDD
Data Bus
WR PORTB
RB0/INT
CK
VSS
Data Latch
WR TRISB
CK
TRIS Latch
TTL
Input
Buffer
RD TRISB
Q
D
EN
EN
RD PORTB
INT
Schmitt
Trigger
DS40044F-page 36
PIC16F627A/628A/648A
FIGURE 5-9:
BLOCK DIAGRAM OF
RB1/RX/DT PIN
FIGURE 5-10:
BLOCK DIAGRAM OF
RB2/TX/CK PIN
VDD
Weak
P Pull-up
VDD
RBPU
SPEN
CK
RB1/
RX/DT
WR TRISB
CK
Data Bus
WR PORTB
Data Latch
D
SPEN
1
D
VDD
Weak
P Pull-up
VDD
RBPU
1
D
CK
Data Latch
VSS
WR TRISB
TRIS Latch
CK
VSS
TRIS Latch
Peripheral OE(1)
Peripheral OE(1)
TTL
Input
Buffer
RD TRISB
Q
TTL
Input
Buffer
RD TRISB
EN
RD PORTB
RD PORTB
USART Slave Clock In
Schmitt
Trigger
1:
D
EN
Note
RB2/
TX/CK
Schmitt
Trigger
Note
1:
DS40044F-page 37
PIC16F627A/628A/648A
FIGURE 5-11:
BLOCK DIAGRAM OF
RB3/CCP1 PIN
VDD
Weak
P Pull-up
VDD
RBPU
CCP1CON
CCP output
Data Bus
WR PORTB
CK
RB3/
CCP1
Data Latch
WR TRISB
CK
VSS
TRIS Latch
Peripheral OE(2)
TTL
Input
Buffer
RD TRISB
Q
D
EN
RD PORTB
CCP In
Schmitt
Trigger
Note
1:
DS40044F-page 38
PIC16F627A/628A/648A
FIGURE 5-12:
RBPU
P weak pull-up
Data Bus
WR PORTB
CK
VDD
Data Latch
WR TRISB
CK
RB4/PGM
VSS
TRIS Latch
RD TRISB
RD PORTB
PGM input
TTL
input
buffer
Schmitt
Trigger
EN
Q1
Set RBIF
From other
RB<7:4> pins
D
EN
Note:
Q3
The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.
DS40044F-page 39
PIC16F627A/628A/648A
FIGURE 5-13:
RBPU
weak VDD
P pull-up
Data Bus
CK
RB5 pin
WR PORTB
Data Latch
VSS
D
CK
WR TRISB
TRIS Latch
TTL
input
buffer
RD TRISB
RD PORTB
EN
Q1
Set RBIF
From other
RB<7:4> pins
EN
DS40044F-page 40
Q3
PIC16F627A/628A/648A
FIGURE 5-14:
RBPU
P weak pull-up
Data Bus
WR PORTB
CK
VDD
Data Latch
WR TRISB
CK
RB6/
T1OSO/
T1CKI/
PGC
pin
VSS
TRIS Latch
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
From RB7
Schmitt
Trigger
TMR1 oscillator
EN
Q1
Set RBIF
From other
RB<7:4> pins
D
Q3
EN
DS40044F-page 41
PIC16F627A/628A/648A
FIGURE 5-15:
RBPU
P weak pull-up
TMR1 oscillator
To RB6
VDD
Data Bus
WR PORTB
CK
RB7/T1OSI/
PGD pin
Data Latch
WR TRISB
CK
VSS
TRIS Latch
RD TRISB
T10SCEN
TTL
input
buffer
RD PORTB
EN
Q1
Set RBIF
From other
RB<7:4> pins
EN
DS40044F-page 42
Q3
PIC16F627A/628A/648A
TABLE 5-3:
PORTB FUNCTIONS
Name
RB0/INT
RB1/RX/DT
Output
Type
RB0
TTL
CMOS
INT
ST
RB1
TTL
CMOS
Description
Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
External interrupt
Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
RX
ST
DT
ST
CMOS
RB2
TTL
CMOS
TX
CMOS
CK
ST
CMOS
RB3
TTL
CMOS
CCP1
ST
CMOS
Capture/Compare/PWM/I/O
RB4
TTL
CMOS
PGM
ST
RB5
RB5
TTL
CMOS
RB6/T1OSO/T1CKI/
PGC
RB6
TTL
CMOS
T1OSO
XTAL
T1CKI
ST
PGC
ST
RB7
TTL
CMOS
T1OSI
XTAL
PGD
ST
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB7/T1OSI/PGD
Legend:
O = Output
= Not used
TTL = TTL Input
TABLE 5-4:
CMOS
P = Power
ST = Schmitt Trigger Input
AN = Analog
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
06h, 106h
PORTB
RB7
RB6
RB5
RB4(1)
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h, 186h
TRISB
TRISB7
TRISB6
1111 1111
81h, 181h
OPTION
RBPU
INTEDG
Legend:
Note 1:
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
DS40044F-page 43
PIC16F627A/628A/648A
5.3
5.3.1
EXAMPLE 5-2:
FIGURE 5-16:
5.3.2
PC
Instruction
fetched
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Q2 Q3 Q4 Q1
PC
MOVWF PORTB
Write to PORTB
Q2 Q3 Q4
PC + 1
MOVF PORTB, W
Read to PORTB
Q1
Q2 Q3 Q4 Q1
PC + 2
NOP
Q2 Q3 Q4
PC + 3
NOP
Port pin
sampled here
TPD
Execute
MOVWF
PORTB
Note 1:
2:
Execute
MOVF
PORTB, W
Execute
NOP
DS40044F-page 44
PIC16F627A/628A/648A
6.0
TIMER0 MODULE
8-bit timer/counter
Read/write capabilities
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
6.1
6.2
6.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
Timer0 Interrupt
DS40044F-page 45
PIC16F627A/628A/648A
6.3
Timer0 Prescaler
FIGURE 6-1:
FOSC/4
T0CKI
pin
SYNC
2
Cycles
T0SE
T0CS
Watchdog
Timer
PSA
TMR0 Reg
WDT Postscaler/
TMR0 Prescaler
8
PSA
8-to-1MUX
PS<2:0>
WDT
Time-out
PSA
Note:
DS40044F-page 46
PIC16F627A/628A/648A
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
EXAMPLE 6-1:
BCF
CLRWDT
CLRF
TMR0
BSF
MOVLW
STATUS, RP0
'00101111b
MOVWF
OPTION_REG
CLRWDT
MOVLW
'00101xxxb
MOVWF
OPTION_REG
BCF
STATUS, RP0
Address
01h, 101h
85h
Legend:
Note 1:
CHANGING PRESCALER
(WDT TIMER0)
CLRWDT
;Skip if already in
;Bank 0
;Clear WDT
;Clear TMR0 and
;Prescaler
;Bank 1
;These 3 lines
;(5, 6, 7)
;are required only
;if desired PS<2:0>
;are
;000 or 001
;Set Postscaler to
;desired WDT rate
;Return to Bank 0
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx
MOVWF
BCF
OPTION_REG
STATUS, RP0
TMR0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
81h, 181h
EXAMPLE 6-2:
CHANGING PRESCALER
(TIMER0 WDT)
STATUS, RP0
TABLE 6-1:
OPTION(2)
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used for Timer0.
Option is referred by OPTION_REG in MPLAB IDE Software.
DS40044F-page 47
PIC16F627A/628A/648A
7.0
TIMER1 MODULE
REGISTER 7-1:
U-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
R/W-0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
bit 2
bit 1
bit 0
DS40044F-page 48
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
7.1
7.2.1
7.2
FIGURE 7-1:
Synchronized
TMR1
Clock Input
TMR1L
1
TMR1ON
T1SYNC
T1OSC
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
Sleep Input
T1CKPS<1:0>
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS40044F-page 49
PIC16F627A/628A/648A
7.3
Timer1 Operation in
Asynchronous Counter Mode
7.3.1
7.3.2
EXAMPLE 7-1:
DS40044F-page 50
PIC16F627A/628A/648A
7.4
Timer1 Oscillator
7.5
TABLE 7-1:
C1
C2
32.768 kHz
15 pF
15 pF
Note:
Freq
7.6
7.7
Timer1 Prescaler
TABLE 7-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
10h
T1CON
--00 0000
--uu uuuu
Legend:
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used by the Timer1 module.
DS40044F-page 51
PIC16F627A/628A/648A
8.0
TIMER2 MODULE
8.1
8.2
TMR2 Output
FIGURE 8-1:
Sets flag
bit TMR2IF
TMR2
output
Reset
EQ
TMR2 Reg
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS<1:0>
PR2 Reg
TOUTPS<3:0>
DS40044F-page 52
PIC16F627A/628A/648A
REGISTER 8-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS0
R/W-0
R/W-0
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
TABLE 8-1:
Address
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Name
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used by the Timer2 module.
DS40044F-page 53
PIC16F627A/628A/648A
NOTES:
DS40044F-page 54
PIC16F627A/628A/648A
9.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 9-1:
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
Additional information on the CCP module is available
in the PIC Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 9-1:
U-0
R/W-0
R/W-0
R/W-0
CCP1X
CCP1Y
CCP1M3
R/W-0
R/W-0
R/W-0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 55
PIC16F627A/628A/648A
9.1
9.1.4
Capture Mode
9.1.1
In Capture mode, the RB3/CCP1 pin should be configured as an input by setting the TRISB<3> bit.
Note:
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
1, 4, 16
RB3/CCP1
pin
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON<3:0>
Qs
9.1.2
9.1.3
EXAMPLE 9-1:
CLRF
MOVLW
MOVWF
9.2
SOFTWARE INTERRUPT
DS40044F-page 56
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Compare Mode
FIGURE 9-2:
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
CCP PRESCALER
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q S Output
Logic
match
RB3/CCP1
R
pin
TRISB<3>
Output Enable CCP1CON<3:0>
Mode Select
Note:
Comparator
TMR1H
TMR1L
PIC16F627A/628A/648A
9.2.1
9.2.4
9.2.2
In this mode (CCP1M<3:0>=1011), an internal hardware trigger is generated, which may be used to initiate
an action. See Register 9-1.
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
Note:
TABLE 9-2:
Address
Removing the match condition by changing the contents of the CCPR1H, CCPR1L
register pair between the clock edge that
generates the special event trigger and
the clock edge that generates the TMR1
Reset will preclude the Reset from
occuring.
Value on
POR
Value on
all other
Resets
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
EEIF CMIF
RCIF
TXIF
CCP1IF
TMR2IF
8Ch
PIE1
EEIE CMIE
RCIE
TXIE
CCP1IE
TMR2IE
86h, 186h
TRISB
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
CCPR1L
16h
CCPR1H
17h
CCP1CON
Legend:
CCP1X
CCP1Y
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used by Capture and Timer1.
DS40044F-page 57
PIC16F627A/628A/648A
9.3
PWM Mode
FIGURE 9-4:
Period
Duty Cycle
TMR2 = PR2
FIGURE 9-3:
PWM OUTPUT
9.3.1
PWM PERIOD
CCP1CON<5:4>
CCPR1L
Comparator
Q
RB3/CCP1
(1)
TMR2
S
TRISB<3>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note
1:
TMR2 is cleared
The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
DS40044F-page 58
PIC16F627A/628A/648A
9.3.2
Fosc
log -------------------------------------------------------------
PWM
F PWM TMR2 Prescaler
Resolution = --------------------------------------------------------------------------- bits
log(2)
Note:
9.3.3
2.
3.
4.
TABLE 9-3:
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
TABLE 9-4:
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.5
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
86h, 186h
TRISB
TRISB7
1111 1111
1111 1111
11h
TMR2
0000 0000
0000 0000
92h
PR2
1111 1111
1111 1111
12h
T2CON
-000 0000
uuuu uuuu
15h
CCPR1L
xxxx xxxx
uuuu uuuu
16h
CCPR1H
xxxx xxxx
uuuu uuuu
17h
CCP1CON
--00 0000
--00 0000
Legend:
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used by PWM and Timer2.
DS40044F-page 59
PIC16F627A/628A/648A
NOTES:
DS40044F-page 60
PIC16F627A/628A/648A
10.0
COMPARATOR MODULE
REGISTER 10-1:
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 7
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 61
PIC16F627A/628A/648A
10.1
Comparator Configuration
FIGURE 10-1:
VIN-
RA3/AN3/CMP1
VIN+
RA1/AN1
VIN-
RA2/AN2/VREF
VIN+
C1
Off (Read as 0)
RA0/AN0
VIN-
RA3/AN3/CMP1
VIN+
VIN-
VIN+
RA1/AN1
C2
Off (Read as 0)
RA2/AN2/VREF
C1
Off (Read as 0)
C2
Off (Read as 0)
VSS
Four Inputs Multiplexed to Two Comparators
CM<2:0> = 010
RA0/AN0
VIN+
RA3/AN3/CMP1
RA0/AN0
VIN-
RA1/AN1
VIN-
RA2/AN2/VREF
VIN+
C1
C2
C1VOUT
A
CIS = 0
CIS = 1
RA3/AN3/CMP1 A
RA1/AN1
RA2/AN2/VREF
CIS = 0
CIS = 1
C2VOUT
VINVIN+
C1
C1VOUT
C2
C2VOUT
VINVIN+
From VREF
Module
Two Common Reference Comparators with Outputs
CM<2:0> = 110
A
D
VIN+
RA1/AN1
VIN-
RA2/AN2/VREF
VIN+
RA3/AN3/CMP1
VIN-
RA3/AN3/CMP1
VIN+
RA1/AN1
VIN-
RA2/AN2/VREF
VIN+
RA0/AN0
VINC1
C2
C1VOUT
C2VOUT
C1
C1VOUT
C2
C2VOUT
RA3/AN3/CMP1 D
VINVIN+
RA0/AN0
C1
Off (Read as 0)
RA3/AN3/CMP1 A
CIS = 0
CIS = 1
VINVIN+
C1
C1VOUT
C2
C2VOUT
VSS
RA1/AN1
RA2/AN2/VREF
VIN-
VIN+
C2
DS40044F-page 62
RA1/AN1
VIN-
RA2/AN2/VREF
VIN+
C2VOUT
D = Digital Input.
PIC16F627A/628A/648A
The code example in Example 10-1 depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 10-1:
BCF
BSF
BSF
BCF
BSF
BSF
10.2
0X20
;Init flag register
;Init PORTA
;Load comparator bits
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM<2:0> = 011
;Select Bank1
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read 0
STATUS,RP0 ;Select Bank 0
DELAY10
;10s delay
CMCON,F
;Read CMCON to end change
;condition
PIR1,CMIF ;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE ;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
VIN+
VIN-
Result
VINVIN+
Result
10.3.1
Comparator Operation
10.3
SINGLE COMPARATOR
INITIALIZING
COMPARATOR MODULE
FLAG_REG
EQU
CLRF
FLAG_REG
CLRF
PORTA
MOVF
CMCON, W
ANDLW
0xC0
IORWF
FLAG_REG,F
MOVLW
0x03
MOVWF
CMCON
BSF
STATUS,RP0
MOVLW
0x07
MOVWF
TRISA
BCF
CALL
MOVF
FIGURE 10-2:
Comparator Reference
10.3.2
10.4
DS40044F-page 63
PIC16F627A/628A/648A
10.5
Comparator Outputs
FIGURE 10-3:
CnINV
To RA3/AN3/CMP1 or
RA4/T0CK1/CMP2 pin
To Data Bus
CMCON<7:6>
CnVOUT
Q
D
Q3
EN
RD CMCON
EN
CL
Q1
DS40044F-page 64
PIC16F627A/628A/648A
10.6
Comparator Interrupts
10.7
10.8
Effects of a Reset
10.9
DS40044F-page 65
PIC16F627A/628A/648A
FIGURE 10-4:
RS < 10 K
RIC
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
500 nA
VSS
Legend: CPIN
VT
ILEAKAGE
RIC
RS
VA
TABLE 10-1:
Address
1Fh
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the Pin
Interconnect Resistance
Source Impedance
Analog Voltage
Value on
All Other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON
C2OUT
C1OUT
C2INV
C1NV
CIS
CM2
CM1
CM0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Bh, 8Bh,
INTCON
10Bh, 18Bh
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
85h
Legend:
TRISA
TRISA2
TRISA1
TRISA0
DS40044F-page 66
PIC16F627A/628A/648A
11.0
VOLTAGE REFERENCE
MODULE
11.1
VR <3:0>
VREF = ----------------------- VDD
24
if VRR = 0:
VR <3:0>
1
VREF = VDD --- + ----------------------- VDD
4
32
The setting time of the Voltage Reference module must
be considered when changing the VREF output
(Table 17-3). Example 11-1 demonstrates how voltage
reference is configured for an output voltage of 1.25V
with VDD = 5.0V.
REGISTER 11-1:
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 67
PIC16F627A/628A/648A
FIGURE 11-1:
VREN
16 Stages
8R
8R
VSS
VREF
Note:
11.2
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
STATUS,RP0
DELAY10
VOLTAGE REFERENCE
CONFIGURATION
;4 Inputs Muxed
;to 2 comps.
;go to Bank 1
;RA3-RA0 are
;outputs
;enable VREF
;low range set VR<3:0>=6
;go to Bank 0
;10s delay
11.3
VSS
VR3
(From VRCON<3:0>)
VR0
EXAMPLE 11-1:
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
VRR
11.5
Connection Considerations
11.4
Effects of a Reset
DS40044F-page 68
PIC16F627A/628A/648A
FIGURE 11-2:
R(1)
VREF
Op Amp
RA2
Module
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration VRCON<3:0> and VRCON<5>.
TABLE 11-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
Resets
9Fh
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
1Fh
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
85h
TRISA
TRISA7 TRISA6
TRISA5
TRISA4
TRISA3
Legend:
TRISA2 TRISA1
- = Unimplemented, read as 0.
DS40044F-page 69
PIC16F627A/628A/648A
NOTES:
DS40044F-page 70
PIC16F627A/628A/648A
12.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
REGISTER 12-1:
R/W-0
TX9
R/W-0
TXEN
R/W-0
U-0
R/W-0
R-1
R/W-0
SYNC
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 71
PIC16F627A/628A/648A
REGISTER 12-2:
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40044F-page 72
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
12.1
EQUATION 12-1:
CALCULATING BAUD
RATE ERROR
Fosc
Desired Baud Rate = ----------------------64 ( x + 1 )
16000000
9600 = -----------------------64 ( x + 1 )
x = 25.042
16000000
Calculated Baud Rate = --------------------------- = 9615
64 ( 25 + 1 )
9615 9600
= ------------------------------ = 0.16%
9600
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
TABLE 12-1:
SYNC
NA
1
Legend:
TABLE 12-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other Resets
98h
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
99h
SPBRG
0000 0000
0000 0000
Legend:
x = unknown, - = unimplemented read as 0. Shaded cells are not used for the BRG.
DS40044F-page 73
PIC16F627A/628A/648A
TABLE 12-3:
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
1.2
NA
2.4
NA
9.6
19.2
BAUD
RATE (K)
FOSC = 20 MHz
16 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
NA
NA
NA
NA
19.53
+1.73%
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
NA
NA
NA
NA
9.766
+1.73%
255
255
19.23
+0.16%
207
19.23
+0.16%
129
76.8
76.92
+0.16%
64
76.92
+0.16%
51
75.76
-1.36%
32
96
96.15
+0.16%
51
95.24
-0.79%
41
96.15
+0.16%
25
300
294.1
-1.96
16
307.69
+2.56%
12
312.5
+4.17%
500
500
500
500
HIGH
5000
4000
2500
LOW
19.53
255
15.625
255
9.766
255
5.0688 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
NA
NA
1.2
NA
NA
NA
2.4
NA
NA
NA
BAUD
RATE (K)
4 MHz
9.6
9.622
+0.23%
185
9.6
131
9.615
+0.16%
103
19.2
19.24
+0.23%
92
19.2
65
19.231
+0.16%
51
76.8
77.82
+1.32
22
79.2
+3.13%
15
75.923
+0.16%
12
96
94.20
-1.88
18
97.48
+1.54%
12
1000
+4.17%
300
298.3
-0.57
316.8
5.60%
NA
500
NA
NA
NA
HIGH
1789.8
1267
100
LOW
6.991
255
4.950
255
3.906
255
32.768 kHz
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
ERROR
SPBRG
value
(decimal)
1 MHz
KBAUD
0.3
NA
NA
0.303
+1.14%
26
1.2
NA
1.202
+0.16%
207
1.170
-2.48%
2.4
NA
2.404
+0.16%
103
NA
9.6
9.622
+0.23%
92
9.615
+0.16%
25
NA
19.2
19.04
-0.83%
46
19.24
+0.16%
12
NA
76.8
74.57
-2.90%
11
83.34
+8.51%
NA
96
99.43
+3.57%
NA
NA
300
298.3
0.57%
NA
NA
500
NA
NA
NA
HIGH
894.9
250
8.192
LOW
3.496
255
0.9766
255
0.032
255
DS40044F-page 74
PIC16F627A/628A/648A
TABLE 12-4:
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
1.2
1.221
2.4
2.404
9.6
19.2
BAUD
RATE (K)
FOSC = 20 MHz
16 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
NA
+1.73%
255
1.202
+0.16%
129
2.404
9.469
-1.36%
32
19.53
+1.73%
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
NA
+0.16%
207
1.202
+0.16%
129
+0.16%
103
2.404
+0.16%
64
9.615
+0.16%
25
9.766
+1.73%
15
15
19.23
+0.16%
12
19.53
+1.73V
76.8
78.13
+1.73%
83.33
+8.51%
78.13
+1.73%
96
104.2
+8.51%
NA
NA
300
312.5
+4.17%
NA
NA
500
NA
NA
NA
HIGH
312.5
250
156.3
LOW
1.221
255
0.977
255
0.6104
255
SPBRG
value
(decimal)
5.0688 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
ERROR
SPBRG
value
(decimal)
207
BAUD
RATE (K)
ERROR
4 MHz
KBAUD
0.3
NA
0.31
+3.13%
255
0.3005
-0.17%
1.2
1.203
+0.23%
92
1.2
65
1.202
+1.67%
51
2.4
2.380
-0.83%
46
2.4
32
2.404
+1.67%
25
9.6
9.322
-2.90%
11
9.9
+3.13%
NA
19.2
18.64
-2.90%
19.8
+3.13%
NA
76.8
NA
79.2
+3.13%
NA
96
NA
NA
NA
300
NA
NA
NA
500
NA
NA
NA
HIGH
111.9
79.2
62.500
LOW
0.437
255
0.3094
255
3.906
255
32.768 kHz
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
0.301
+0.23%
185
0.300
+0.16%
51
0.256
-14.67%
1.2
1.190
-0.83%
46
1.202
+0.16%
12
NA
2.4
2.432
+1.32%
22
2.232
-6.99%
NA
9.6
9.322
-2.90%
NA
NA
19.2
18.64
-2.90%
NA
NA
76.8
NA
NA
NA
96
NA
NA
NA
300
NA
NA
NA
BAUD
RATE (K)
1 MHz
500
NA
NA
NA
HIGH
55.93
15.63
0.512
LOW
0.2185
255
0.0610
255
0.0020
255
DS40044F-page 75
PIC16F627A/628A/648A
TABLE 12-5:
KBAUD
ERROR
SPBRG
value
(decimal)
9.615
+0.16%
19200
19.230
38400
37.878
BAUD
RATE (K)
9600
FOSC = 20 MHz
16 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
129
9.615
+0.16%
+0.16%
64
19.230
-1.36%
32
38.461
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
103
9.615
+0.16%
64
+0.16%
51
18.939
-1.36%
32
+0.16%
25
39.062
+1.7%
15
57600
56.818
-1.36%
21
58.823
+2.12%
16
56.818
-1.36%
10
115200
113.636
-1.36%
10
111.111
-3.55%
125
+8.51%
250000
250
250
NA
625000
625
NA
625
1250000
1250
NA
NA
5.068 MHz
ERROR
SPBRG
value
(decimal)
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
KBAUD
4 MHz
9600
9.520
-0.83%
46
9598.485
0.016%
32
9615.385
0.160%
25
19200
19.454
+1.32%
22
18632.35
-2.956%
16
19230.77
0.160%
12
38400
37.286
-2.90%
11
39593.75
3.109%
35714.29
-6.994%
57600
55.930
-2.90%
52791.67
-8.348%
62500
8.507%
115200
111.860
-2.90%
105583.3
-8.348%
125000
8.507%
250000
NA
316750
26.700%
250000
0.000%
625000
NA
NA
NA
1250000
NA
NA
NA
32.768 kHz
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
ERROR
SPBRG
value
(decimal)
1 MHz
9600
9725.543
1.308%
22
8.928
-6.994%
NA
NA
NA
19200
18640.63
-2.913%
11
20833.3
8.507%
NA
NA
NA
38400
37281.25
-2.913%
31250
-18.620%
NA
NA
NA
57600
55921.88
-2.913%
62500
+8.507
NA
NA
NA
115200
111243.8
-2.913%
NA
NA
NA
NA
250000
223687.5
-10.525%
NA
NA
NA
NA
625000
NA
NA
NA
NA
NA
1250000
NA
NA
NA
NA
NA
DS40044F-page 76
PIC16F627A/628A/648A
12.2
In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8-bit. A dedicated 8-bit baud rate generator is used to
derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USARTs transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The baud rate generator produces a clock either
x16 or x64 of the bit shift rate, depending on bit BRGH
(TXSTA<2>). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
12.2.1
USART ASYNCHRONOUS
TRANSMITTER
DS40044F-page 77
PIC16F627A/628A/648A
FIGURE 12-1:
TXREG register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR register
RB2/TX/CK pin
Interrupt
TXEN
SPEN
SPBRG
TX9
TX9D
2.
3.
4.
5.
6.
7.
8.
FIGURE 12-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG output
(shift clock)
RB2/TX/CK (pin)
Word 1
Start bit
DS40044F-page 78
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
bit 0
Word 1
Transmit Shift Reg.
PIC16F627A/628A/648A
FIGURE 12-3:
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
Word 2
Start bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
bit 0
bit 1
Word 1
bit 7/8
Word 1
Transmit Shift Reg.
Start bit
Word 2
Stop bit
bit 0
Word 2
Transmit Shift Reg.
Note:
TABLE 12-6:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
19h
0000 0000
0000 0000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
0000 0000
0000 0000
Legend:
DS40044F-page 79
PIC16F627A/628A/648A
12.2.2
USART ASYNCHRONOUS
RECEIVER
FIGURE 12-4:
FERR
OERR
CREN
SPBRG
64
or
16
RSR register
MSb
Stop (8)
LSb
0 Start
RB1/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADEN
Enable
Load of
RX9
ADEN
RSR<8>
Receive
Buffer
8
RX9D
RCREG register
RX9D
RCREG register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
DS40044F-page 80
PIC16F627A/628A/648A
FIGURE 12-5:
RB1/RX/DT (Pin)
bit 0
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
Read RCV
Buffer Reg
RCREG
Word 1
RCREG
RCIF
(interrupt flag)
ADEN = 1
(Address Match
Enable)
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
FIGURE 12-6:
RB1/RX/DT (pin)
bit 0
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
Read RCV
Buffer Reg
RCREG
Word 1
RCREG
RCIF
(Interrupt Flag)
ADEN = 1
(Address Match
Enable)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
FIGURE 12-7:
RB1/RX/DT (pin)
Start
bit
bit 0
RCV Shift
Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
bit 1
bit 8
Stop
bit
Start
bit
Word 1
RCREG
bit 0
bit 8
Stop
bit
Word 2
RCREG
RCIF
(Interrupt Flag)
ADEN
(Address Match
Enable)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a 0, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.
DS40044F-page 81
PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
1.
TABLE 12-7:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
1Ah
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
99h
Legend:
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
OERR
RX9D
TRMT
TX9D
x = unknown, - = unimplemented locations read as 0. Shaded cells are not used for asynchronous reception.
DS40044F-page 82
PIC16F627A/628A/648A
12.3
12.3.1
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = 1). When ADEN is
disabled (= 0), all data bytes are received and the 9th
bit can be used as the parity bit.
Reception is
(RCSTA<4>).
12.3.1.1
bit
CREN
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
1Ah
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
OERR
RX9D
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
99h
Legend:
setting
1.
Address
by
TABLE 12-8:
enabled
TRMT
TX9D
x = unknown, - = unimplemented locations read as 0. Shaded cells are not used for asynchronous
reception.
DS40044F-page 83
PIC16F627A/628A/648A
12.4
12.4.1
DS40044F-page 84
2.
3.
4.
5.
6.
7.
8.
PIC16F627A/628A/648A
TABLE 12-9:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
19h
8Ch
PIE1
EEIE
CMIE
98h
TXSTA
CSRC
TX9
99h
Legend:
RCIE
Bit 3
Bit 2
TXEN SYNC
Bit 0
Value on
POR
ADEN
TXIE
Bit 1
FERR
OERR
RX9D
TRMT
TX9D
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
Value on all
other Resets
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as 0. Shaded cells are not used for synchronous master transmission.
FIGURE 12-8:
SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 0
RB1/RX/DT pin
bit 1
bit 2
bit 7
bit 0
Word 1
bit 1
Word 2
bit 7
RB2/TX/CK pin
Write to
TXREG Reg
Write Word 1
TXIF bit
(Interrupt Flag)
Write Word 2
TRMT
TRMT
bit
1
TXEN bit
Note:
FIGURE 12-9:
RB1/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RB2/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
DS40044F-page 85
PIC16F627A/628A/648A
12.4.2
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
1Ah
8Ch
PIE1
EPIE
CMIE
98h
TXSTA
CSRC
TX9
99h
Legend:
RCIE
Bit 3
ADEN
TXIE
TXEN SYNC
Bit 2
Bit 1
Bit 0
Value on:
POR
OERR
RX9D
Value on all
other Resets
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
-000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented read as 0. Shaded cells are not used for synchronous master reception.
DS40044F-page 86
PIC16F627A/628A/648A
FIGURE 12-10:
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RB2/TX/CK pin
WRITE to
Bit SREN
SREN bit
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
12.5
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
12.5.1
e)
2.
3.
4.
5.
6.
7.
8.
DS40044F-page 87
PIC16F627A/628A/648A
12.5.2
2.
3.
4.
5.
6.
7.
8.
9.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
18h
RCSTA
SPEN
RX9
SREN CREN
19h
EEIE
CMIE
98h
TXSTA
CSRC
TX9
99h
8Ch
Legend:
RCIE
ADEN
TXIE
TXEN SYNC
Bit 2
Bit 1
Bit 0
Value on
POR
OERR
RX9D
Value on all
other Resets
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented read as 0. Shaded cells are not used for synchronous slave transmission.
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
1Ah
EEIE
CMIE
98h
TXSTA
CSRC
TX9
99h
8Ch
RCIE
Bit 3
ADEN
TXIE
TXEN SYNC
Bit 2
Bit 1
Bit 0
Value on
POR
OERR
RX9D
0000 000x
Value on all
other Resets
0000 -000
0000 000x
0000 0000
0000 0000
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for synchronous slave reception.
DS40044F-page 88
PIC16F627A/628A/648A
13.0
EECON1
EECON2 (Not a physically implemented register)
EEDATA
EEADR
REGISTER 13-1:
R/W-x
R/W-x
R/W-x
R/W-x
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-x
R/W-x
EEDAT2 EEDAT1
R/W-x
EEDAT0
bit 7
bit 7-0
bit 0
EEDATn: Byte value to Write to or Read from data EEPROM memory location.
Legend:
REGISTER 13-2:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EADR7
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 7
bit 0
PIC16F627A/628A
Unimplemented Address: Must be set to 0
PIC16F648A
EEADR: Set to 1 specifies top 128 locations (128-255) of EEPROM Read/Write Operation
bit 6-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40044F-page 89
PIC16F627A/628A/648A
13.1
EEADR
13.2
REGISTER 13-3:
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40044F-page 90
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F627A/628A/648A
13.3
EXAMPLE 13-1:
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
;Bank 1
;
;Address to read
;EE Read
;W = EEDATA
;Bank 0
13.4
Required
Sequence
EXAMPLE 13-2:
BSF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS, RP0
EECON1, WREN
INTCON, GIE
INTCON,GIE
$-2
55h
EECON2
AAh
EECON2
EECON1,WR
;Bank 1
;Enable write
;Disable INTs.
;See AN576
;
;Write 55h
;
;Write AAh
;Set WR bit
;begin write
;Enable INTs.
13.5
Write Verify
EXAMPLE 13-3:
BSF
MOVF
BSF
WRITE VERIFY
;
;Is the value written
;read (in EEDATA) the
;
SUBWF
EEDATA, W
BTFSS
STATUS, Z
GOTO
WRITE_ERR
:
:
13.6
DS40044F-page 91
PIC16F627A/628A/648A
13.7
EXAMPLE 13-4:
BANKSEL
CLRF
BCF
BTFSC
GOTO
BSF
Loop
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
GOTO
;select Bank1
;start at address 0
;disable interrupts
;see AN576
EECON1, RD
0x55
EECON2
0xAA
EECON2
EECON1, WR
EECON1, WR
$ - 1
;enable EE writes
#IFDEF __16F648A
INCFSZ
#ELSE
INCF
BTFSS
#ENDIF
EEADR, f
EEADR, f
EEADR, 7
GOTO
Loop
BCF
BSF
EECON1, WREN
INTCON, GIE
;disable EE writes
;enable interrupts (optional)
DS40044F-page 92
PIC16F627A/628A/648A
13.8
TABLE 13-1:
Value on all
other
Resets
xxxx xxxx
xxxx xxxx
---- x000
uuuu uuuu
uuuu uuuu
---- q000
---- ---9Dh
EECON2(1) EEPROM Control Register 2
Legend:
x = unknown, u = unchanged, - = unimplemented read as 0, q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register.
---- ----
Address
9Ah
9Bh
9Ch
Name
EEDATA
EEADR
EECON1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WRERR
Bit 2
WREN
Bit 1
WR
Bit 0
RD
DS40044F-page 93
PIC16F627A/628A/648A
NOTES:
DS40044F-page 94
PIC16F627A/628A/648A
14.0
OSC selection
Reset
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Sleep
Code protection
ID Locations
In-Circuit Serial Programming (ICSP)
14.1
Configuration Bits
DS40044F-page 95
PIC16F627A/628A/648A
REGISTER 14-1:
CP
CPD
LVP
BOREN
MCLRE
FOSC2
PWRTE
WDTE
F0SC1
bit 13
F0SC0
bit 0
bit 13:
bit 12-9:
Unimplemented: Read as 0
bit 8:
bit 7:
bit 6:
bit 5:
bit 3:
bit 2:
bit 4, 1-0:
1:
2:
3:
4:
Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it does on the
PIC16F627/628 devices.
The code protection scheme has changed from the code protection scheme used on the PIC16F627/628 devices. The
entire Flash program memory needs to be bulk erased to set the CP bit, turning the code protection off. See
PIC16F627A/628A/648A EEPROM Memory Programming Specification (DS41196) for details.
The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See PIC16F627A/
628A/648A EEPROM Memory Programming Specification (DS41196) for details.
When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS40044F-page 96
x = bit is unknown
PIC16F627A/628A/648A
14.2
TABLE 14-1:
Oscillator Configurations
14.2.1
OSCILLATOR TYPES
LP
Low Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Precision Oscillator (2 modes)
EC
External Clock In
14.2.2
FIGURE 14-1:
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note:
C1(2)
XTAL
RF
Sleep
OSC2
RS(1)
C2(2)
1:
2:
FOSC
PIC16F627A/628A/648A
TABLE 14-2:
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
15-30 pF
0-15 pF
15-30 pF
0-15 pF
XT
100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
HS
8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
Note:
OSC1
Note
Mode
DS40044F-page 97
PIC16F627A/628A/648A
14.2.3
FIGURE 14-2:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To other
Devices
10K
4.7K
74AS04
PIC16F627A/628A/648A
CLKIN
74AS04
10K
FIGURE 14-3:
330 K
330 K
74AS04
74AS04
DS40044F-page 98
74AS04
CLKIN
PIC16F627A/
628A/648A
XTAL
14.2.4
14.2.5
EXTERNAL CLOCK IN
FIGURE 14-4:
10K
C2
To other
Devices
0.1 pF
XTAL
C1
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Clock from
ext. system
RA6
RA6/OSC2/CLKOUT
PIC16F627A/628A/648A
14.2.6
RC OSCILLATOR
14.2.8
FIGURE 14-5:
VDD
RC OSCILLATOR MODE
PIC16F627A/628A/648A
REXT
RA7/OSC1/
CLKIN
Internal
Clock
CEXT
VSS
FOSC/4
RA6/OSC2/CLKOUT
14.2.7
CLKOUT
14.3
Reset
DS40044F-page 99
PIC16F627A/628A/648A
FIGURE 14-6:
MCLR/
VPP Pin
Sleep
WDT
Module
VDD Rise
Detect
WDT
Time-out
Reset
Power-on Reset
VDD
Brown-out
Reset
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
PWRT
On-chip(1)
OSC
10-bit Ripple-counter
Enable PWRT
Enable OST
Note
1:
DS40044F-page 100
PIC16F627A/628A/648A
14.4
14.4.1
14.4.3
14.4.4
14.4.2
FIGURE 14-7:
VBOR
TBOR
Internal
Reset
72 ms
VDD
VBOR
Internal
Reset
<72 ms
72 ms
VDD
VBOR
Internal
Reset
Note:
72 ms
DS40044F-page 101
PIC16F627A/628A/648A
14.4.5
14.4.6
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-11). This is useful for testing purposes
or to synchronize more than one PIC16F627A/628A/
648A device operating in parallel.
TABLE 14-3:
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
XT, HS, LP
72 ms +
1024TOSC
1024TOSC
72 ms +
1024TOSC
1024TOSC
1024TOSC
RC, EC
72 ms
72 ms
INTOSC
72 ms
72 ms
6 s
Oscillator Configuration
TABLE 14-4:
POR
BOR
TO
PD
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
1
Legend:
Condition
u = unchanged, x = unknown
DS40044F-page 102
PIC16F627A/628A/648A
TABLE 14-5:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
Resets(1)
03h, 83h,
103h, 183h
STATUS
IRP
RP1
RPO
TO
PD
DC
0001 1xxx
000q quuu
PCON
OSCF
POR
BOR
---- 1-0x
---- u-uq
8Eh
Legend:
Note
1:
TABLE 14-6:
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- 1-0x
000h
000u uuuu
---- 1-uu
000h
0001 0uuu
---- 1-uu
WDT Reset
000h
0000 uuuu
---- 1-uu
PC + 1
uuu0 0uuu
---- u-uu
000h
000x xuuu
---- 1-u0
uuu1 0uuu
---- u-uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
PC + 1
(1)
DS40044F-page 103
PIC16F627A/628A/648A
TABLE 14-7:
Register
Address
Power-on Reset
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h, 80h,
100h, 180h
TMR0
01h, 101h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h, 82h,
102h, 182h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h, 83h,
103h, 183h
0001 1xxx
000q quuu(4)
uuuq 0uuu(4)
FSR
04h, 84h,
104h, 184h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
xxxx 0000
xxxx 0000
uuuu uuuu
PORTB
06h, 106h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
0Ah, 8Ah,
10Ah, 18Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh, 8Bh,
10Bh,18Bh
0000 000x
0000 000u
uuuu uqqq(2)
PIR1
0Ch
0000 -000
0000 -000
qqqq -qqq(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
--00 0000
--uu uuuu(6)
--uu uuuu
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
CCPR1L
15h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
16h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
17h
--00 0000
--00 0000
--uu uuuu
RCSTA
18h
0000 000x
0000 000x
uuuu uuuu
TXREG
19h
0000 0000
0000 0000
uuuu uuuu
RCREG
1Ah
0000 0000
0000 0000
uuuu uuuu
CMCON
1Fh
0000 0000
0000 0000
uu-- uuuu
OPTION
81h,181h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
1111 1111
1111 1111
uuuu uuuu
TRISB
86h, 186h
1111 1111
1111 1111
uuuu uuuu
PIE1
8Ch
0000 -000
0000 -000
uuuu -uuu
PCON
8Eh
---- 1-0x
---- 1-uq(1,5)
---- u-uu
PR2
92h
1111 1111
1111 1111
uuuu uuuu
TXSTA
98h
0000 -010
0000 -010
uuuu -uuu
SPBRG
99h
0000 0000
0000 0000
uuuu uuuu
EEDATA
9Ah
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
9Bh
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
VRCON
9Fh
000- 0000
000- 0000
uuu- uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
DS40044F-page 104
PIC16F627A/628A/648A
FIGURE 14-8:
VDD
MCLR
Internal POR
TPWRT
PWRT Time Out
TOST
Internal Reset
FIGURE 14-9:
VDD
MCLR
Internal POR
TPWRT
PWRT Time Out
TOST
Internal Reset
FIGURE 14-10:
VDD
MCLR
Internal POR
TPWRT
PWRT Time Out
TOST
Internal Reset
DS40044F-page 105
PIC16F627A/628A/648A
FIGURE 14-11:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 14-13:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
VDD
VDD
R1
Q1
MCLR
PIC16F627A/628A/648A
R2
R1
40k
MCLR
PIC16F627A/628A/648A
Note 1:
2:
3:
FIGURE 14-12:
R1
R1 + R2
= 0.7 V
R1
0.7 V be
2: Internal
x Brown-out Reset= should
R1 + R2
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
10k
MCLR
40k
PIC16F627A/628A/648A
DS40044F-page 106
PIC16F627A/628A/648A
14.5
Interrupts
FIGURE 14-14:
INTERRUPT LOGIC
TMR1IF
TMR1IE
TMR2IF
TMR2IE
T0IF
T0IE
INTF
INTE
CCP1IF
CCP1IE
CMIF
CMIE
TXIF
TXIE
RCIF
RCIE
EEIF
EEIE
RBIF
RBIE
Interrupt to CPU
PEIE
GIE
Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is
suspended during Sleep, only those peripherals which do not depend upon the system
clock will wake the part from Sleep. See Section 14.8.1 Wake-up from Sleep.
DS40044F-page 107
PIC16F627A/628A/648A
14.5.1
RB0/INT INTERRUPT
14.5.3
14.5.2
PORTB INTERRUPT
14.5.4
COMPARATOR INTERRUPT
for
TMR0 INTERRUPT
FIGURE 14-15:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT
(3)
(4)
INT pin
(1)
INTF flag
(INTCON<1>)
(1)
(5)
GIE bit
(INTCON<7>)
Instruction Flow
PC
PC
Instruction
Fetched
Inst (PC)
Instruction
Executed
Inst (PC - 1)
Note 1:
2:
3:
4:
5:
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
DS40044F-page 108
PIC16F627A/628A/648A
TABLE 14-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
Resets(1)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
0000 -000
0000 -000
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
14.6
EXAMPLE 14-1:
MOVWF
SWAPF
BCF
MOVWF
W_TEMP
:
:(ISR)
:
SWAPF
STATUS_TEMP,W;swap STATUS_TEMP
register
;into W, sets bank to
original
;state
MOVWF
STATUS
;move W into STATUS
;register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
14.7
14.7.1
WDT PERIOD
14.7.2
WDT PROGRAMMING
CONSIDERATIONS
DS40044F-page 109
PIC16F627A/628A/648A
FIGURE 14-16:
M
U
1X
Watchdog
Timer
WDT Postscaler/
TMR0 Prescaler
8
8 to 1 MUX
PSA
PS<2:0>
WDT
Enable Bit
To TMR0
(Figure 6-1)
MUX
PSA
WDT
Time-out
Note:
TABLE 14-9:
Address
Name
Bit 7
2007h
CONFIG
LVP
81h, 181h
OPTION
Bit 6
Bit 5
Bit 4
RBPU INTEDG
T0CS
T0SE
Value on
POR Reset
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
PWRTE
WDTE
FOSC1
FOSC0
PSA
PS2
PS1
PS0
14.8
DS40044F-page 110
PIC16F627A/628A/648A
14.8.1
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT wake-up occurred.
FIGURE 14-17:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(1,2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
14.9
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy cycle
0004h(3)
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
Code Protection
PC + 2
DS40044F-page 111
PIC16F627A/628A/648A
14.11 In-Circuit Serial Programming
(ICSP)
The PIC16F627A/628A/648A microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH. See PIC16F627A/
628A/648A
EEPROM
Memory
Programming
Specification (DS41196) for details. RB6 becomes the
programming clock and RB7 becomes the programming
data. Both RB6 and RB7 are Schmitt Trigger inputs in
this mode.
After Reset, to place the device into Programming/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depending
on the command, 14 bits of program data are then
supplied to or from the device, depending if the command
was a load or a read. For complete details of serial
programming, please refer to PIC16F627A/628A/648A
EEPROM
Memory
Programming
Specification
(DS41196).
A typical In-Circuit Serial Programming connection is
shown in Figure 14-18.
FIGURE 14-18:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16F627A/628A/648A
+5V
VDD
0V
VSS
VPP
RA5/MCLR/VPP
CLK
RB6/PGC
Data I/O
RB7/PGD
VDD
To Normal
Connections
DS40044F-page 112
PIC16F627A/628A/648A
14.13 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB ICD 2 development with
an 18-pin device is not practical. A special 28-pin
PIC16F648A-ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user. Debugging of all
three versions of the PIC16F627A/628A/648A is
supported by the PIC16F648A-ICD.
This special ICD device is mounted on the top of a
header and its signals are routed to the MPLAB ICD 2
connector. On the bottom of the header is an 18-pin
socket that plugs into the users target via an 18-pin
stand-off connector.
When the ICD pin on the PIC16F648A-ICD device is
held low, the In-Circuit Debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB ICD 2. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 14-19
shows which features are consumed by the background
debugger.
ICDCLK, ICDDATA
Stack
1 level
Program Memory
DS40044F-page 113
PIC16F627A/628A/648A
NOTES:
DS40044F-page 114
PIC16F627A/628A/648A
15.0
15.1
Byte-oriented operations
Bit-oriented operations
Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 s. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 s.
Table 15-2 lists the instructions recognized by the
MPASM assembler.
Figure 15-1 shows the three general formats that the
instructions can have.
Note 1: Any unused opcode is reserved. Use of
any reserved opcode may cause unexpected operation.
2: To maintain upward compatibility with
future PIC MCU products, do not use the
OPTION and TRIS instructions.
Read-Modify-Write Operations
TABLE 15-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
FIGURE 15-1:
General
13
8 7
OPCODE
k (literal)
TO
Time-out bit
OPCODE
PD
Power-down bit
f (FILE #)
b (BIT #)
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
k (literal)
DS40044F-page 115
PIC16F627A/628A/648A
TABLE 15-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BCF
BSF
BTFSC
BTFSS
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
01
01
01
01
1, 2
1, 2
3
3
1:
2:
3:
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data
will be written back with a 0.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.
DS40044F-page 116
PIC16F627A/628A/648A
15.2
Instruction Descriptions
ADDLW
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDLW
Operands:
0 k 255
Operands:
(W) + k (W)
0 k 255
Operation:
Operation:
Status Affected:
C, DC, Z
Status Affected:
Encoding:
11
Encoding:
11
Description:
Description:
Words:
Cycles:
Words:
Example
ADDLW
Cycles:
Example
ANDLW
111x
ANDLW
kkkk
kkkk
0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
1001
kkkk
kkkk
0x5F
Before Instruction
W = 0xA3
After Instruction
W = 0x03
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
C, DC, Z
Status Affected:
Encoding:
00
Encoding:
00
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Example
ADDWF
Example
ANDWF
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0111
f,d
dfff
REG1, 0
Before Instruction
W
= 0x17
REG1 = 0xC2
After Instruction
W
= 0xD9
REG1 = 0xC2
Z
= 0
C
= 0
DC
= 0
ffff
0101
f,d
dfff
ffff
REG1, 1
Before Instruction
W
= 0x17
REG1 = 0xC2
After Instruction
W
= 0x17
REG1 = 0x02
DS40044F-page 117
PIC16F627A/628A/648A
BCF
Bit Clear f
BTFSC
Syntax:
[ label ] BCF
Syntax:
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
Description:
Words:
Cycles:
Example
BCF
f,b
00bb
bfff
ffff
Encoding:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Encoding:
01
Description:
Words:
Cycles:
Example
BSF
01bb
f,b
bfff
ffff
10bb
bfff
ffff
Description:
Words:
Cycles:
1(2)
Example
HERE
FALSE
TRUE
REG1, 7
Before Instruction
REG1 = 0xC7
After Instruction
REG1 = 0x47
01
BTFSC
GOTO
REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if REG<1> = 0,
PC = address TRUE
if REG<1> =1,
PC = address FALSE
REG1, 7
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A
DS40044F-page 118
PIC16F627A/628A/648A
BTFSS
CALL
Call Subroutine
Syntax:
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b<7
Operands:
0 k 2047
Operation:
Operation:
skip if (f<b>) = 1
Status Affected:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Encoding:
01
Status Affected:
None
Description:
Encoding:
10
Description:
Words:
Cycles:
Example
HERE
Words:
Cycles:
1(2)
Example
HERE
FALSE
TRUE
11bb
BTFSS
GOTO
bfff
ffff
REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
0kkk
CALL
kkkk
kkkk
THERE
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
CLRF
Syntax:
Clear f
[ label ] CLRF
Operands:
0 f 127
Operation:
00h (f)
1Z
Status Affected:
Encoding:
00
Description:
Words:
Cycles:
Example
CLRF
0001
1fff
ffff
REG1
Before Instruction
REG1 = 0x5A
After Instruction
REG1 = 0x00
Z
= 1
DS40044F-page 119
PIC16F627A/628A/648A
CLRW
Clear W
COMF
Complement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
00h (W)
1Z
0 f 127
d [0,1]
Operation:
(f) (dest)
Status Affected:
Status Affected:
Encoding:
00
Encoding:
00
Description:
Description:
Words:
Cycles:
Example
CLRW
Words:
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z = 1
Cycles:
Example
COMF
CLRWDT
DECF
Syntax:
[ label ] CLRWDT
Operands:
None
Operands:
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
0 f 127
d [0,1]
Operation:
(f) - 1 (dest)
Status Affected:
Status Affected:
TO, PD
Encoding:
Encoding:
00
Description:
0001
0000
0011
1001
f,d
dfff
ffff
REG1, 0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W
= 0xEC
Syntax:
Decrement f
[ label ] DECF f,d
00
0011
dfff
ffff
Description:
Decrement register f. If d is
0. the result is stored in the W
register. If d is 1, the result is
stored back in register f.
Words:
Words:
Cycles:
Cycles:
Example
DECF
Example
0000
0110
CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter =
WDT prescaler =
=
TO
=
PD
DS40044F-page 120
0100
0x00
0
1
1
CNT, 1
Before Instruction
CNT = 0x01
Z
= 0
After Instruction
CNT = 0x00
Z
= 1
PIC16F627A/628A/648A
DECFSZ
Decrement f, Skip if 0
GOTO
Unconditional Branch
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 2047
Operation:
(f) - 1 (dest);
0
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
10
00
Description:
Description:
GOTO is an unconditional
branch. The eleven-bit immediate value is loaded into PC bits
<10:0>. The upper bits of PC
are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
Words:
Cycles:
Example
GOTO THERE
Words:
1011
skip if result =
dfff
ffff
1(2)
Example
HERE
DECFSZ
GOTO
CONTINUE
1kkk
kkkk
kkkk
After Instruction
PC = Address THERE
Cycles:
GOTO k
REG1, 1
LOOP
Before Instruction
PC
= address HERE
After Instruction
REG1 = REG1 - 1
if REG1 = 0,
PC = address CONTINUE
if REG1 0,
PC
= address HERE+1
DS40044F-page 121
PIC16F627A/628A/648A
INCF
Increment f
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (dest)
Operation:
Status Affected:
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
Description:
Words:
Cycles:
Example
INCF
Words:
INCF f,d
1010
dfff
ffff
REG1, 1
Before Instruction
REG1 = 0xFF
Z
= 0
After Instruction
REG1 = 0x00
Z
= 1
INCFSZ f,d
1111
Cycles:
1(2)
Example
HERE
dfff
INCFSZ
GOTO
CONTINUE
ffff
REG1, 1
LOOP
Before Instruction
PC
= address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1 0,
PC
= address HERE +1
DS40044F-page 122
PIC16F627A/628A/648A
IORLW
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
0 k 255
Operation:
Operation:
k (W)
Status Affected:
Status Affected:
None
Encoding:
11
Encoding:
11
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Example
MOVLW
Example
IORLW
IORLW k
1000
kkkk
kkkk
0x35
MOVLW k
00xx
kkkk
kkkk
0x5A
After Instruction
W = 0x5A
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) (dest)
Status Affected:
Encoding:
00
Description:
Words:
Cycles:
Example
MOVF
IORWF
MOVF
f,d
Operation:
Status Affected:
Encoding:
00
Description:
Words:
Cycles:
Example
IORWF
0100
dfff
REG1, 0
Before Instruction
REG1 = 0x13
W
= 0x91
After Instruction
REG1 = 0x13
W
= 0x93
Z
= 1
ffff
Move f
MOVF f,d
1000
dfff
ffff
REG1, 0
After Instruction
W= value in REG1 register
Z = 1
DS40044F-page 123
PIC16F627A/628A/648A
MOVWF
Move W to f
OPTION
Syntax:
[ label ]
Syntax:
[ label ]
0 f 127
Operands:
None
Operands:
Operation:
(W) (f)
Operation:
(W) OPTION
Status Affected:
None
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
Words:
Cycles:
MOVWF
0000
1fff
ffff
Description:
Words:
Cycles:
Example
MOVWF
REG1
Before Instruction
REG1 = 0xFF
W
= 0x4F
After Instruction
REG1 = 0x4F
W
= 0x4F
OPTION
0000
0110
0010
Example
To maintain upward compatibility with future PIC MCU
products, do not use this
instruction.
NOP
No Operation
RETFIE
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS PC,
1 GIE
Encoding:
00
Status Affected:
None
Description:
No operation.
Encoding:
00
Words:
Description:
Cycles:
Example
NOP
Words:
Cycles:
Example
RETFIE
NOP
0000
0xx0
0000
RETFIE
0000
0000
1001
After Interrupt
PC = TOS
GIE = 1
DS40044F-page 124
PIC16F627A/628A/648A
RETLW
RLF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
k (W);
TOS PC
0 f 127
d [0,1]
Operation:
Status Affected:
None
Status Affected:
Encoding:
11
Encoding:
00
Description:
Description:
Words:
Cycles:
Example
TABLE
RETLW k
01xx
kkkk
kkkk
Cycles:
Example
RLF
f,d
1101
Words:
RLF
dfff
ffff
REGISTER F
REG1, 0
Before Instruction
REG1=1110 0110
C
= 0
After Instruction
REG1=1110 0110
W = 1100 1100
C
= 1
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Syntax:
[ label ]
Operands:
None
Operation:
TOS PC
Status Affected:
None
Encoding:
00
Description:
Words:
Cycles:
Example
RETURN
RETURN
0000
0000
1000
After Interrupt
PC = TOS
DS40044F-page 125
PIC16F627A/628A/648A
RRF
SUBLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) (W)
Operation:
C, DC, Z
Status Affected:
Status
Affected:
Encoding:
00
Encoding:
11
Description:
Description:
1100
Words:
Cycles:
Example
RRF
RRF f,d
dfff
ffff
REGISTER F
SUBLW k
110x
Words:
Cycles:
Example 1:
SUBLW
kkkk
kkkk
0x02
Before Instruction
W = 1
C = ?
REG1, 0
Before Instruction
REG1 = 1110 0110
C
= 0
After Instruction
REG1 = 1110 0110
W
= 0111 0011
C
= 0
After Instruction
W = 1
C = 1; result is positive
Example 2:
Before Instruction
W = 2
C = ?
After Instruction
W = 0
C = 1; result is zero
SLEEP
Example 3:
Syntax:
[ label ]
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
W =
C =
W =
C =
TO, PD
Encoding:
00
Description:
Words:
Cycles:
Example:
SLEEP
DS40044F-page 126
0110
3
?
After Instruction
Status Affected:
0000
Before Instruction
0xFF
0; result is negative
0011
PIC16F627A/628A/648A
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status
Affected:
C, DC, Z
(f<3:0>) (dest<7:4>),
(f<7:4>) (dest<3:0>)
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
Description:
Words:
Words:
Cycles:
Cycles:
Example 1:
SUBWF
Example
SWAPF
SUBWF f,d
0010
dfff
ffff
REG1, 1
Before Instruction
Example 2:
1
2
1; result is positive
1
0
Before Instruction
REG1 = 2
W
= 2
C
= ?
After Instruction
REG1
W
C
Z
Example 3:
=
=
=
=
REG1 = 1
W
= 2
C
= ?
After Instruction
REG1
W
C
Z
=
=
=
=
0xFF
2
0; result is negative
DC = 0
ffff
REG1, 0
After Instruction
REG1 = 0xA5
W
= 0x5A
TRIS
Syntax:
[ label ] TRIS
Operands:
5f7
Operation:
Status Affected:
None
Encoding:
00
Description:
Words:
Cycles:
0
2
1; result is zero
DC = 1
Before Instruction
dfff
REG1 = 0xA5
After Instruction
=
=
=
=
=
1110
Before Instruction
REG1 = 3
W
= 2
C
= ?
REG1
W
C
DC
Z
SWAPF f,d
0000
0110
0fff
Example
To maintain upward compatibility with future PIC MCU
products, do not use this
instruction.
DS40044F-page 127
PIC16F627A/628A/648A
XORLW
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
Encoding:
00
Description:
Words:
Cycles:
Example
XORWF
XORLW k
Operation:
Status Affected:
Encoding:
11
Description:
1010
Words:
Cycles:
Example:
XORLW
kkkk
0xAF
Before Instruction
W = 0xB5
After Instruction
W = 0x1A
kkkk
XORWF
0110
f,d
dfff
ffff
REG1, 1
Before Instruction
REG1 = 0xAF
W
= 0xB5
After Instruction
REG1 = 0x1A
W
= 0xB5
DS40044F-page 128
PIC16F627A/628A/648A
16.0
DEVELOPMENT SUPPORT
16.1
DS40044F-page 129
PIC16F627A/628A/648A
16.2
MPASM Assembler
16.5
16.6
16.3
16.4
DS40044F-page 130
PIC16F627A/628A/648A
16.7
16.8
16.9
DS40044F-page 131
PIC16F627A/628A/648A
16.11 PICSTART Plus Development
Programmer
DS40044F-page 132
PIC16F627A/628A/648A
17.0
ELECTRICAL SPECIFICATIONS
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than
pulling this pin directly to VSS.
DS40044F-page 133
PIC16F627A/628A/648A
PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 17-1:
6.0
5.5
5.0
VDD
(VOLTS)
4.5
4.0
3.5
3.0
2.5
4
10
20
25
FREQUENCY (MHz)
Note:
The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2:
6.0
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
2.0
0
10
20
25
FREQUENCY (MHz)
Note:
The shaded region indicates the permissible combinations of voltage and frequency.
DS40044F-page 134
PIC16F627A/628A/648A
17.1
PIC16LF627A/628A/648A
(Industrial)
PIC16F627A/628A/648A
(Industrial, Extended)
Param
No.
Sym
VDD
D001
Characteristic/Device
Min
Typ
Max
Units
Conditions
Supply Voltage
PIC16LF627A/628A/648A
2.0
5.5
PIC16F627A/628A/648A
3.0
5.5
1.5*
D002
VDR
D003
VSS
D004
0.05*
V/ms
D005
3.65
4.0
4.35
3.65
4.0
4.4
Legend:
Rows with standard voltage device data only are shaded for improved readability.
Data in Typ column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS40044F-page 135
PIC16F627A/628A/648A
17.2
DC CHARACTERISTICS
Param
No.
Min
LF and F Device
Characteristics
Conditions
Typ
Max
Units
Note
VDD
LF
2.0
5.5
LF/F
3.0
5.5
LF
0.01
0.80
2.0
LF/F
0.01
0.85
3.0
0.02
2.7
5.0
D022
D023
D024
LF
2.0
2.0
LF/F
3.4
3.0
17.0
5.0
LF/F
29
52
4.5
30
55
5.0
LF
15
22
2.0
LF/F
22
37
3.0
44
68
5.0
LF
34
55
2.0
LF/F
50
75
3.0
80
110
5.0
LF
1.2
2.0
2.0
LF/F
D025
1.3
2.2
3.0
1.8
2.9
5.0
10
15
2.0
WDT Current
BOR Current
Comparator Current
(Both comparators enabled)
VREF Current
T1OSC Current
LF/F
D011
D012A
Note 1:
25
3.0
48
5.0
LF
125
190
2.0
175
340
3.0
320
520
5.0
LF
250
350
2.0
450
600
3.0
710
995
5.0
LF
395
465
2.0
LF/F
565
785
3.0
0.895
1.3
mA
5.0
2.5
2.9
mA
4.5
2.75
3.3
mA
5.0
LF/F
D013
15
28
LF/F
LF/F
D012
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 4 MHz
INTOSC
FOSC = 20 MHz
HS Oscillator Mode
The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
DS40044F-page 136
PIC16F627A/628A/648A
17.3
DC CHARACTERISTICS
Param
No.
Device Characteristics
Min
Typ
Max
Units
Note
VDD
3.0
5.5
0.01
3.0
0.02
5.0
3.0
WDT Current
20
5.0
29
52
4.5
30
55
5.0
22
37
3.0
44
68
5.0
Comparator Current
(Both comparators enabled)
50
75
3.0
VREF Current
83
110
5.0
1.3
3.0
1.8
5.0
15
28
3.0
28
54
5.0
175
340
3.0
320
520
5.0
450
650
3.0
0.710
1.1
mA
5.0
565
785
3.0
0.895
1.3
mA
5.0
2.5
2.9
mA
4.5
2.75
3.5
mA
5.0
D020E
BOR Current
T1OSC Current
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 4 MHz
INTOSC
FOSC = 20 MHz
HS Oscillator Mode
The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
DS40044F-page 137
PIC16F627A/628A/648A
17.4
DC CHARACTERISTICS
Param.
No.
Sym
VIL
Characteristic/Device
Min
Typ
Max
Unit
VSS
VSS
VSS
VSS
0.8
0.15 VDD
0.2 VDD
0.2 VDD
V
V
V
V
VSS
VSS
0.3 VDD
0.6
V
V
2.0V
.25 VDD + 0.8V
0.8 VDD
0.8 VDD
1.3
0.9 VDD
0.7 VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
50
200
400
1.0
0.5
1.0
5.0
A
A
A
A
0.6
0.6
V
V
VDD 0.7
VDD 0.7
V
V
8.5*
15
pF
50
pF
D031
D032
D033
VIH
I/O ports
with TTL buffer
D041
D042
D043
D043A
D043B
VOL
I/O ports(4)
D090
D150
VOD
(Note1)
D080
VOH
(Note1)
D060
D061
D063
D040
D070
Conditions
D030
Note
DS40044F-page 138
PIC16F627A/628A/648A
TABLE 17-1:
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ
Max
Units
100K
10K
VMIN
1M
100K
5.5
E/W
E/W
V
Conditions
Endurance
ED
ED
Endurance
VDRW VDD for read/write
D122
D123
40
8*
ms
Year
D124
TREF
1M
10M
E/W
D130
D130A
D131
EP
EP
VPR
Endurance
Endurance
VDD for read
10K
1000
VMIN
100K
10K
5.5
E/W
E/W
V
D132
D132A
4.5
VMIN
5.5
5.5
V
V
D133
D133A
D134
40
4
2
8*
4*
ms
ms
year
-40C TA 85C
85C TA 125C
VMIN = Minimum operating
voltage
Provided no other
specifications are violated
-40C to +85C
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Refer to Section 13.7 Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
DS40044F-page 139
PIC16F627A/628A/648A
TABLE 17-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD <5.5V, -40C < TA < +125C, unless otherwise stated.
Param
No.
Characteristics
Sym
Min
Typ
Max
Units
D300
VIOFF
5.0
10
mV
D301
VICM
VDD 1.5*
D302
CMRR
55*
db
TRESP
300
400*
ns
400
600*
ns
400
600*
ns
300
10*
D303
Response Time
D304
(1)
TMC2OV
Comments
Response time measured with one comparator input at (VDD 1.5)/2, while the other input transitions from
VSS to VDD.
TABLE 17-3:
Operating Conditions: 2.0V < VDD < 5.5V, -40C < TA < +125C, unless otherwise stated.
Spec
No.
Characteristics
Sym
Min
Typ
Max
Units
Comments
D310
Resolution
VRES
VDD/24
VDD/32
LSb
LSb
D311
Absolute Accuracy
VRAA
1/4(2)*
1/2(2)*
LSb
LSb
D312
VRUR
2k*
D313
Time(1)
TSET
10*
Settling
DS40044F-page 140
PIC16F627A/628A/648A
17.5
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Time
CLKOUT
osc
OSC1
io
I/O port
t0
T0CKI
mc
MCLR
Fall
Period
High
Rise
Invalid (High-impedance)
Valid
Low
High-Impedance
FIGURE 17-3:
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
DS40044F-page 141
PIC16F627A/628A/648A
17.6
FIGURE 17-4:
Q1
Q3
Q2
Q4
Q1
OSC1
1
2
CLKOUT
TABLE 17-4:
Parameter
No.
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
TOSC
Oscillator Period(1)
TCY
TosL,
TosH
RC
Min
Typ
Max
Units
Conditions
DC
DC
20
DC
200
0.1
20
200
48
250
ns
50
ns
LP Osc mode
250
ns
RC Osc mode
250
10,000
ns
XT Osc mode
50
1,000
ns
HS Osc mode
LP Osc mode
250
ns
21
200
TCY
DC
ns
TCY = 4/FOSC
100*
ns
10 kHz*
4 MHz
VDD = 5.0V
External Biased RC
Frequency
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at Min values
with an external clock applied to the OSC1 pin. When an external clock input is used, the Max cycle time
limit is DC (no clock) for all devices.
DS40044F-page 142
PIC16F627A/628A/648A
TABLE 17-5:
Parameter
No.
Sym
F10
FIOSC
F13
IOSC
Oscillator Accuracy
F14*
Characteristic
start-up time
Min
Typ
Max
Units
Conditions
MHz
3.96
4.04
3.92
4.08
3.80
4.20
FIGURE 17-5:
Q4
Q2
Q3
OSC1
11
10
22
CLKOUT
23
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
DS40044F-page 143
PIC16F627A/628A/648A
TABLE 17-6:
Parameter
No.
Characteristic
PIC16F62XA
10
10A
Min
Typ
Max
Units
75
200*
ns
PIC16LF62XA
400*
ns
PIC16F62XA
75
200*
ns
PIC16LF62XA
400*
ns
TCKR
PIC16F62XA
35
100*
ns
PIC16LF62XA
200*
ns
TCKF
PIC16F62XA
35
100*
ns
200*
ns
14
TCKL2IOV
20*
ns
15
11
11A
12
12A
13
13A
PIC16LF62XA
PIC16F62XA
TOSC+200 ns*
ns
ns
16
TCKH2IOI
17
TOSH2IOV
PIC16F62XA
PIC16LF62XA
18
TOSH2IOI
ns
50
150*
ns
300*
ns
100*
200*
ns
FIGURE 17-6:
VDD
MCLR
30
Internal
POR
33
PWRT
Time out
32
OST
Time out
Internal
Reset
Watchdog
Timer
Reset
34
31
34
I/O Pins
DS40044F-page 144
PIC16F627A/628A/648A
FIGURE 17-7:
VBOR
VDD
35
TABLE 17-7:
Parameter
No.
Sym
30
TMCL
31
TWDT
32
TOST
33
TPWRT
34
35
Legend:
Characteristic
Min
Typ
Max
Units
Conditions
2000
ns
7*
18
33*
ms
1024 TOSC
28*
72
132*
ms
TIOZ
2.0*
TBOR
100*
TBD = To Be Determined.
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 17-8:
RA4/T0CKI/CMP2
41
40
42
RB6/T1OSO/T1CKI/PGC
46
45
47
48
TMR0 OR
TMR1
DS40044F-page 145
PIC16F627A/628A/648A
TABLE 17-8:
Param
No.
Sym
40
TT0H
41
TT0L
42
TT0P
T0CKI Period
45
TT1H
Characteristic
No Prescaler
Min
Typ
0.5TCY + 20*
With Prescaler
No Prescaler
ns
ns
10*
ns
Greater of:
20 or TCY + 40*
N
ns N = prescale
value (2, 4,
..., 256)
0.5TCY + 20*
ns
15*
ns
25*
ns
30*
ns
50*
ns
0.5TCY + 20*
ns
15*
ns
PIC16LF62XA
T1CKI Low Synchronous, No Prescaler
Time
Synchronous, PIC16F62XA
with Prescaler PIC16LF62XA
Asynchronous PIC16F62XA
PIC16LF62XA
TT1P
47
ns
ns
50*
ns
ns N = prescale
value (1, 2,
4, 8)
Greater of:
TCY + 40*
N
ns
20 or
Asynchronous PIC16F62XA
PIC16LF62XA
48
25*
30*
Greater of:
20 or TCY + 40*
N
PIC16LF62XA
FT1
ns
10*
Asynchronous PIC16F62XA
TT1L
0.5TCY + 20*
With Prescaler
46
60*
100*
ns
32.7(1)
kHz
2TOSC
7TOSC
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
This oscillator is intended to work only with 32.768 kHz watch crystals and their manufactured tolerances.
Higher value crystal frequencies may not be compatible with this crystal driver.
DS40044F-page 146
PIC16F627A/628A/648A
FIGURE 17-9:
CAPTURE/COMPARE/PWM TIMINGS
RB3/CCP1
(CAPTURE MODE)
50
51
52
RB3/CCP1
(COMPARE OR PWM MODE)
53
TABLE 17-9:
CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Sym
No.
TCCL CCP
input low time
50
54
Characteristic
Min
No Prescaler
PIC16F62XA
With Prescaler PIC16LF62XA
51
TCCH CCP
input high time
No Prescaler
PIC16F62XA
With Prescaler PIC16LF62XA
52
53
54
0.5TCY +
20*
ns
10*
ns
20*
ns
0.5TCY +
20*
ns
10*
ns
20*
ns
3TCY + 40*
N
ns
PIC16F62XA
10
25*
ns
PIC16LF62XA
25
45*
ns
PIC16F62XA
10
25*
ns
PIC16LF62XA
25
45*
ns
Conditions
N = prescale
value (1,4 or 16)
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS40044F-page 147
PIC16F627A/628A/648A
NOTES:
DS40044F-page 148
PIC16F627A/628A/648A
18.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. Typical represents the mean of the distribution at 25C. Max or Min represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 18-1:
160
140
120
IPD (nA)
100
80
60
-40C
0C
40
+25C
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS40044F-page 149
PIC16F627A/628A/648A
FIGURE 18-2:
300
280
260
IPD (nA)
240
220
200
+85C
180
160
140
120
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 18-3:
2.4
2.2
IPD (A)
2.0
1.8
+125C
1.6
1.4
1.2
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS40044F-page 150
PIC16F627A/628A/648A
FIGURE 18-4:
40
38
36
IPD (A)
34
125C
85C
25C
0C
-40C
32
30
28
26
24
22
20
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
VDD (Volts)
FIGURE 18-5:
30
25
IPD (A)
20
125C
85C
25C
0C
-40C
15
10
0
2
2.5
3.5
4.5
5.5
VDD (Volts)
DS40044F-page 151
PIC16F627A/628A/648A
FIGURE 18-6:
100
90
80
IPD (A)
70
125C
85C
25C
0C
-40C
60
50
40
30
20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 18-7:
16
14
12
IPD (A)
10
125C
85C
25C
0C
-40C
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS40044F-page 152
PIC16F627A/628A/648A
FIGURE 18-8:
AVERAGE IPD_TIMER1
-40C
IPD (uA)
0C
25C
85C
125
0
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 18-9:
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
-1.0%
-2.0%
-3.0%
-4.0%
-5.0%
-40
25
85
125
Temperature (C)
DS40044F-page 153
PIC16F627A/628A/648A
FIGURE 18-10:
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
-1.0%
-2.0%
-3.0%
-4.0%
-5.0%
-40
25
85
125
Temperature (C)
FIGURE 18-11:
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
-1.0%
-2.0%
-3.0%
-4.0%
-5.0%
-40
25
85
125
Temperature (C)
DS40044F-page 154
PIC16F627A/628A/648A
FIGURE 18-12:
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
-1.0%
-2.0%
-3.0%
-4.0%
-5.0%
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 18-13:
5.0%
4.0%
3.0%
2.0%
1.0%
0.0%
-1.0%
-2.0%
-3.0%
-4.0%
-5.0%
2
2.5
3.5
4.5
5.5
VDD (V)
DS40044F-page 155
PIC16F627A/628A/648A
FIGURE 18-14:
25 C Avg
-40 C
1.40
1.20
IDD (mA)
1.00
0.80
0.60
0.40
0.20
0.00
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 18-15:
60
55
50
45
40
35
30
2
2.5
3.5
4.5
5.5
VDD (V)
DS40044F-page 156
PIC16F627A/628A/648A
FIGURE 18-16:
25 C Avg
-40 C
180
160
140
IPD (A)
120
100
80
60
40
20
0
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 18-17:
SUPPLY CURRENT (IDD vs. VDD, FOSC = 1 MHz (XT OSCILLATOR MODE)
500
450
400
IPD (A)
350
125C
85C
25C
0C
-40C
300
250
200
150
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS40044F-page 157
PIC16F627A/628A/648A
FIGURE 18-18:
SUPPLY CURRENT (IDD vs. VDD, FOSC = 4 MHz (XT OSCILLATOR MODE)
1000
900
800
IPD (A)
700
125C
85C
25C
0C
-40C
600
500
400
300
200
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 18-19:
SUPPLY CURRENT (IDD) vs. VDD, FOSC = 20 MHz (HS OSCILLATOR MODE)
4.0
IDD (mA)
3.5
125C
85C
25C
0C
-40C
3.0
2.5
2.0
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
VDD (Volts)
DS40044F-page 158
PIC16F627A/628A/648A
FIGURE 18-20:
WDT Time-out
50
Time (mS)
45
40
35
-40
30
25
20
15
10
5
85
25
125
0
2
2.5
3.5
4.5
5.5
V DD (V)
DS40044F-page 159
PIC16F627A/628A/648A
NOTES:
DS40044F-page 160
PIC16F627A/628A/648A
19.0
PACKAGING INFORMATION
19.1
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F627A
-I/P e3
0410017
Example
PIC16F628A
-E/SO e3
0410017
YYWWNNN
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Example
PIC16F648A
-I/SS e3
0410017
Example
16F628A
-I/ML e3
0410017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40044F-page 161
PIC16F627A/628A/648A
18-Lead Plastic Dual In-Line (P) 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
3
D
E
A2
A1
b1
b
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
NOM
MAX
18
Pitch
.210
A2
.115
.130
.195
A1
.015
.300
.310
.325
E1
.240
.250
.280
Overall Length
.880
.900
.920
.115
.130
.150
Lead Thickness
.008
.010
.014
b1
.045
.060
.070
.014
.018
.022
eB
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-007B
DS40044F-page 162
PIC16F627A/628A/648A
18-Lead Plastic Small Outline (SO) Wide, 7.50 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2 3
b
h
h
c
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
18
Pitch
Overall Height
1.27 BSC
A2
2.05
Standoff
A1
0.10
0.30
Overall Width
E1
7.50 BSC
Overall Length
11.55 BSC
2.65
10.30 BSC
Chamfer (optional)
0.25
0.75
Foot Length
0.40
1.27
Footprint
L1
1.40 REF
Foot Angle
Lead Thickness
0.20
0.33
Lead Width
0.31
0.51
15
15
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-051B
DS40044F-page 163
PIC16F627A/628A/648A
20-Lead Plastic Shrink Small Outline (SS) 5.30 mm Body [SSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1 2
b
A2
A1
L1
Units
Dimension Limits
Number of Pins
L
MILLIMETERS
MIN
NOM
MAX
20
Pitch
Overall Height
0.65 BSC
2.00
A2
1.65
1.75
1.85
Standoff
A1
0.05
Overall Width
7.40
7.80
8.20
E1
5.00
5.30
5.60
Overall Length
6.90
7.20
7.50
Foot Length
0.55
0.75
0.95
Footprint
L1
1.25 REF
Lead Thickness
0.09
Foot Angle
0.25
8
Lead Width
0.22
0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-072B
DS40044F-page 164
PIC16F627A/628A/648A
28-Lead Plastic Quad Flat, No Lead Package (ML) 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
E2
2
K
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A3
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
28
Pitch
Overall Height
0.80
0.65 BSC
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Width
E2
Overall Length
D2
3.65
3.70
4.20
0.23
0.30
0.35
Contact Length
0.50
0.55
0.70
Contact-to-Exposed Pad
0.20
Contact Width
6.00 BSC
3.65
3.70
4.20
6.00 BSC
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
DS40044F-page 165
PIC16F627A/628A/648A
NOTES:
DS40044F-page 166
PIC16F627A/628A/648A
APPENDIX A:
DATA SHEET
REVISION HISTORY
APPENDIX B:
DEVICE
DIFFERENCES
Revision A
This is a new data sheet.
TABLE B-1:
Revision B
Revised 28-Pin QFN Pin Diagram
Revised Figure 5-4 Block Diagram
Revised Register 7-1 TMR1ON
Revised Example 13-4 Data EEPROM Refresh Routine
Revised Instruction Set SUBWF, Example 1
Revised DC Characteristics 17-2 and 17-3
Revised Tables 17-4 and 17-6
Corrected Table and Figure numbering in Section 17.0
DEVICE DIFFERENCES
Memory
Device
Flash
Program
RAM
Data
EEPROM
Data
PIC16F627A
1024 x 14
224 x 8
128 x 8
PIC16F628A
2048 x 14
224 x 8
128 x 8
PIC16F648A
4096 x 14
256 x 8
256 x 8
Revision C
General revisions throughout. Revisions to Section
14.0 Special Features of the CPU. Section 18,
modified graphs.
Revision D
Revise Example 13-2, Data EEPROM Write
Revise Sections 17.2, Param No. D020 and 17.3,
Param No. D020E
Revise Section 18.0 graphs
Revision E
Section 19.0 Packaging Information:
package drawings and added note.
Replaced
Revision F (03/2007)
Replaced Package Drawings (Rev. AM); Replaced
Development Support Section; Revised Product ID
System.
DS40044F-page 167
PIC16F627A/628A/648A
APPENDIX C:
DEVICE MIGRATIONS
C.1
1.
2.
3.
4.
5.
6.
7.
PIC16F627/628 to a PIC16F627A/
628A
ER mode is now RC mode.
Code protection for the program memory has
changed from code-protect sections of memory
to code-protect of the whole memory. The
configuration bits CP0 and CP1 in the
PIC16F627/628 do not exist in the PIC16F627A/
628A. They have been replaced with one
configuration bit<13> CP.
Brown-out Detect (BOD) terminology has
changed to Brown-out Reset (BOR) to better
represent the function of the Brown-out circuitry.
Enabling Brown-out Reset (BOR) does not
automatically enable the Power-up Timer
(PWRT) the way it did in the PIC16F627/628.
INTRC is now called INTOSC.
Timer1 Oscillator is now designed for
32.768 kHz operation. In the PIC16F627/628,
the Timer1 oscillator was designed to run up to
200 kHz.
The Dual-Speed Oscillator mode only works in
the INTOSC oscillator mode. In the PIC16F627/
628, the Dual-Speed Oscillator mode worked in
both the INTRC and ER oscillator modes.
DS40044F-page 168
APPENDIX D:
MIGRATING FROM
OTHER PIC
DEVICES
D.1
PIC16C62X/CE62X to PIC16F627A/
628A/648A Migration
See
Microchip
web
(www.microchip.com).
D.2
for
availability
PIC16C622A to PIC16F627A/628A/
648A Migration
See
Microchip
web
(www.microchip.com).
Note:
site
site
for
availability
PIC16F627A/628A/648A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
DS40044F-page 169
PIC16F627A/628A/648A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16F627A/628A/648A
N
Literature Number: DS40044F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS40044F-page 170
PIC16F627A/628A/648A
INDEX
A
A/D
Special Event Trigger (CCP)....................................... 57
Absolute Maximum Ratings .............................................. 133
ADDLW Instruction ........................................................... 117
ADDWF Instruction ........................................................... 117
ANDLW Instruction ........................................................... 117
ANDWF Instruction ........................................................... 117
Architectural Overview .......................................................... 9
Assembler
MPASM Assembler................................................... 130
B
Baud Rate Error .................................................................. 73
Baud Rate Formula ............................................................. 73
BCF Instruction ................................................................. 118
Block Diagrams
Comparator
I/O Operating Modes .......................................... 62
Modified Comparator Output .............................. 64
I/O Ports
RB0/INT Pin ........................................................ 36
RB1/RX/DT Pin ................................................... 37
RB2/TX/CK Pin ................................................... 37
RB3/CCP1 Pin .................................................... 38
RB4/PGM Pin ..................................................... 39
RB5 Pin............................................................... 40
RB6/T1OSO/T1CKI Pin ...................................... 41
RB7/T1OSI Pin ................................................... 42
RC Oscillator Mode..................................................... 99
USART Receive.......................................................... 80
USART Transmit......................................................... 78
BRGH bit ............................................................................. 73
Brown-Out Reset (BOR) ................................................... 101
BSF Instruction ................................................................. 118
BTFSC Instruction............................................................. 118
BTFSS Instruction ............................................................. 119
C
C Compilers
MPLAB C18 .............................................................. 130
MPLAB C30 .............................................................. 130
CALL Instruction ............................................................... 119
Capture (CCP Module) ....................................................... 56
Block Diagram............................................................. 56
CCP Pin Configuration................................................ 56
CCPR1H:CCPR1L Registers...................................... 56
Changing Between Capture Prescalers...................... 56
Prescaler..................................................................... 56
Software Interrupt ....................................................... 56
Timer1 Mode Selection ............................................... 56
Capture/Compare/PWM (CCP)........................................... 55
Capture Mode. See Capture
CCP1 .......................................................................... 55
CCPR1H Register............................................... 55
CCPR1L Register ............................................... 55
CCP2 .......................................................................... 55
Compare Mode. See Compare
PWM Mode. See PWM
Timer Resources......................................................... 55
CCP1CON Register ............................................................ 55
CCP1M Bits ................................................................ 55
CCP1X:CCP1Y Bits .................................................... 55
CCP2CON Register
CCP2M<3:2> Bits....................................................... 55
CCP2X:CCP2Y Bits.................................................... 55
Clocking Scheme/Instruction Cycle .................................... 13
CLRF Instruction............................................................... 119
CLRW Instruction.............................................................. 120
CLRWDT Instruction......................................................... 120
CMCON Register................................................................ 61
Code Examples
Data EEPROM Refresh Routine ................................ 92
Code Protection ................................................................ 111
COMF Instruction.............................................................. 120
Comparator
Block Diagrams
I/O Operating Modes .......................................... 62
Modified Comparator Output .............................. 64
Comparator Module.................................................... 61
Configuration .............................................................. 62
Interrupts .................................................................... 65
Operation.................................................................... 63
Reference ................................................................... 63
Compare (CCP Module) ..................................................... 56
Block Diagram ............................................................ 56
CCP Pin Configuration ............................................... 57
CCPR1H:CCPR1L Registers ..................................... 56
Software Interrupt ....................................................... 57
Special Event Trigger ................................................. 57
Timer1 Mode Selection............................................... 57
CONFIG Register ............................................................... 96
Configuration Bits ............................................................... 95
Crystal Operation................................................................ 97
Customer Change Notification Service............................. 169
Customer Notification Service .......................................... 169
Customer Support............................................................. 169
D
Data EEPROM Memory...................................................... 89
EECON1 Register ...................................................... 89
EECON2 Register ...................................................... 89
Operation During Code Protection ............................. 93
Reading ...................................................................... 91
Spurious Write Protection........................................... 91
Using .......................................................................... 92
Write Verify ................................................................. 91
Writing to .................................................................... 91
Data Memory Organization................................................. 15
DECF Instruction .............................................................. 120
DECFSZ Instruction.......................................................... 121
Development Support ....................................................... 129
Device Differences............................................................ 167
Device Migrations ............................................................. 168
Dual-speed Oscillator Modes.............................................. 99
E
EECON1 Register............................................................... 90
EECON1 register ................................................................ 90
EECON2 register ................................................................ 90
Errata .................................................................................... 3
External Crystal Oscillator Circuit ....................................... 98
F
Fuses. See Configuration Bits
G
General Purpose Register File ........................................... 15
GOTO Instruction.............................................................. 121
DS40044F-page 171
PIC16F627A/628A/648A
I
I/O Ports .............................................................................. 31
Bidirectional ................................................................ 44
Block Diagrams
RB0/INT Pin ........................................................ 36
RB1/RX/DT Pin ................................................... 37
RB2/TX/CK Pin ................................................... 37
RB3/CCP1 Pin .................................................... 38
RB4/PGM Pin...................................................... 39
RB5 Pin............................................................... 40
RB6/T1OSO/T1CKI Pin ...................................... 41
RB7/T1OSI Pin ................................................... 42
PORTA........................................................................ 31
PORTB........................................................................ 36
Programming Considerations ..................................... 44
Successive Operations ............................................... 44
TRISA ......................................................................... 31
TRISB ......................................................................... 36
ID Locations ...................................................................... 111
INCF Instruction ................................................................ 122
INCFSZ Instruction............................................................ 122
In-Circuit Serial Programming ....................................... 112
Indirect Addressing, INDF and FSR Registers.................... 28
Instruction Flow/Pipelining .................................................. 13
Instruction Set
ADDLW ..................................................................... 117
ADDWF ..................................................................... 117
ANDLW ..................................................................... 117
ANDWF ..................................................................... 117
BCF ........................................................................... 118
BSF ........................................................................... 118
BTFSC ...................................................................... 118
BTFSS ...................................................................... 119
CALL ......................................................................... 119
CLRF......................................................................... 119
CLRW ....................................................................... 120
CLRWDT................................................................... 120
COMF ....................................................................... 120
DECF ........................................................................ 120
DECFSZ.................................................................... 121
GOTO ....................................................................... 121
INCF.......................................................................... 122
INCFSZ ..................................................................... 122
IORLW ...................................................................... 123
IORWF ...................................................................... 123
MOVF........................................................................ 123
MOVLW .................................................................... 123
MOVWF .................................................................... 124
NOP .......................................................................... 124
OPTION .................................................................... 124
RETFIE ..................................................................... 124
RETLW ..................................................................... 125
RETURN ................................................................... 125
RLF ........................................................................... 125
RRF........................................................................... 126
SLEEP ...................................................................... 126
SUBLW ..................................................................... 126
SUBWF ..................................................................... 127
SWAPF ..................................................................... 127
TRIS .......................................................................... 127
XORLW ..................................................................... 128
XORWF..................................................................... 128
Instruction Set Summary................................................... 115
INT Interrupt ...................................................................... 108
INTCON Register ................................................................ 24
DS40044F-page 172
M
Memory Organization
Data EEPROM Memory.................................. 89, 91, 93
Microchip Internet Web Site.............................................. 169
Migrating from other PIC Devices..................................... 168
MOVF Instruction.............................................................. 123
MOVLW Instruction........................................................... 123
MOVWF Instruction .......................................................... 124
MPLAB ASM30 Assembler, Linker, Librarian ................... 130
MPLAB ICD 2 In-Circuit Debugger ................................... 131
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ................................................... 131
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator ................................................... 131
MPLAB Integrated Development Environment Software.. 129
MPLAB PM3 Device Programmer .................................... 131
MPLINK Object Linker/MPLIB Object Librarian ................ 130
N
NOP Instruction ................................................................ 124
O
OPTION Instruction .......................................................... 124
OPTION Register................................................................ 23
OPTION_REG Register...................................................... 23
Oscillator Configurations..................................................... 97
Oscillator Start-up Timer (OST) ........................................ 101
P
Package Marking Information ........................................... 161
Packaging Information ...................................................... 161
PCL and PCLATH............................................................... 28
Stack........................................................................... 28
PCON Register ................................................................... 27
PICSTART Plus Development Programmer..................... 132
PIE1 Register...................................................................... 25
Pin Functions
RC6/TX/CK ........................................................... 7187
RC7/RX/DT........................................................... 7187
PIR1 Register ..................................................................... 26
PORTA ............................................................................... 31
PORTB ............................................................................... 36
PORTB Interrupt ............................................................... 108
Power Control/Status Register (PCON)............................ 102
Power-Down Mode (Sleep)............................................... 110
Power-On Reset (POR) .................................................... 101
Power-up Timer (PWRT) .................................................. 101
PR2 Register ................................................................ 52, 58
Program Memory Organization........................................... 15
PWM (CCP Module) ........................................................... 58
Block Diagram ............................................................ 58
Simplified PWM .................................................. 58
CCPR1H:CCPR1L Registers...................................... 58
PIC16F627A/628A/648A
Duty Cycle................................................................... 59
Example Frequencies/Resolutions ............................. 59
Period.......................................................................... 58
Set-Up for PWM Operation ......................................... 59
TMR2 to PR2 Match ................................................... 58
Q
Q-Clock ............................................................................... 59
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator ....................................................................... 99
RC Oscillator Mode
Block Diagram............................................................. 99
Reader Response ............................................................. 170
Registers
CCP1CON (CCP Operation)....................................... 55
CMCON (Comparator Configuration).......................... 61
CONFIG (Configuration Word).................................... 96
EECON1 (EEPROM Control Register 1) .................... 90
INTCON (Interrupt Control)......................................... 24
Maps
PIC16F627A ................................................. 16, 17
PIC16F628A ................................................. 16, 17
OPTION_REG (Option) .............................................. 23
PCON (Power Control) ............................................... 27
PIE1 (Peripheral Interrupt Enable 1)........................... 25
PIR1 (Peripheral Interrupt Register 1) ........................ 26
Status.......................................................................... 22
T1CON Timer1 Control).............................................. 48
T2CON Timer2 Control).............................................. 53
Reset................................................................................... 99
RETFIE Instruction............................................................ 124
RETLW Instruction ............................................................ 125
RETURN Instruction ......................................................... 125
Revision History ................................................................ 167
RLF Instruction.................................................................. 125
RRF Instruction ................................................................. 126
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Production (SQTP) Devices ... 7
SLEEP Instruction ............................................................. 126
Software Simulator (MPLAB SIM)..................................... 130
Special Event Trigger. See Compare
Special Features of the CPU .............................................. 95
Special Function Registers ................................................. 18
Status Register ................................................................... 22
SUBLW Instruction............................................................ 126
SUBWF Instruction ........................................................... 127
SWAPF Instruction............................................................ 127
T
T1CKPS0 bit ....................................................................... 48
T1CKPS1 bit ....................................................................... 48
T1CON Register ................................................................. 48
T1OSCEN bit ...................................................................... 48
T1SYNC bit ......................................................................... 48
T2CKPS0 bit ....................................................................... 53
T2CKPS1 bit ....................................................................... 53
T2CON Register ................................................................. 53
Timer0
Block Diagrams
Timer0/WDT ....................................................... 46
External Clock Input.................................................... 45
Interrupt....................................................................... 45
Prescaler .................................................................... 46
Switching Prescaler Assignment ................................ 47
Timer0 Module............................................................ 45
Timer1
Asynchronous Counter Mode ..................................... 50
Capacitor Selection .................................................... 51
External Clock Input ................................................... 49
External Clock Input Timing........................................ 50
Oscillator..................................................................... 51
Prescaler .............................................................. 49, 51
Resetting Timer1 ........................................................ 51
Resetting Timer1 Registers ........................................ 51
Special Event Trigger (CCP) ...................................... 57
Synchronized Counter Mode ...................................... 49
Timer Mode ................................................................ 49
TMR1H ....................................................................... 50
TMR1L........................................................................ 50
Timer2
Block Diagram ............................................................ 52
Postscaler................................................................... 52
PR2 register................................................................ 52
Prescaler .............................................................. 52, 59
Timer2 Module............................................................ 52
TMR2 output ............................................................... 52
TMR2 to PR2 Match Interrupt..................................... 58
Timing Diagrams
Timer0 ...................................................................... 145
Timer1 ...................................................................... 145
USART
Asynchronous Receiver...................................... 81
USART Asynchronous Master Transmission ............. 78
USART Asynchronous Reception .............................. 81
USART Synchronous Reception ................................ 87
USART Synchronous Transmission ........................... 85
Timing Diagrams and Specifications ................................ 142
TMR0 Interrupt.................................................................. 108
TMR1CS bit ........................................................................ 48
TMR1ON bit........................................................................ 48
TMR2ON bit........................................................................ 53
TOUTPS0 bit ...................................................................... 53
TOUTPS1 bit ...................................................................... 53
TOUTPS2 bit ...................................................................... 53
TOUTPS3 bit ...................................................................... 53
TRIS Instruction ................................................................ 127
TRISA ................................................................................. 31
TRISB ................................................................................. 36
U
Universal Synchronous Asynchronous Receiver
Transmitter (USART)................................................. 71
Asynchronous Receiver
Setting Up Reception.......................................... 83
Asynchronous Receiver Mode
Address Detect ................................................... 83
Block Diagram .................................................... 83
USART
Asynchronous Mode................................................... 77
Asynchronous Receiver.............................................. 80
Asynchronous Reception............................................ 82
Asynchronous Transmission ...................................... 78
Asynchronous Transmitter.......................................... 77
Baud Rate Generator (BRG) ...................................... 73
Block Diagrams
Transmit.............................................................. 78
USART Receive ................................................. 80
BRGH bit .................................................................... 73
DS40044F-page 173
PIC16F627A/628A/648A
Sampling ......................................................... 74, 75, 76
Synchronous Master Mode ......................................... 84
Synchronous Master Reception .................................. 86
Synchronous Master Transmission............................. 84
Synchronous Slave Mode ........................................... 87
Synchronous Slave Reception .................................... 88
Synchronous Slave Transmit ...................................... 87
V
Voltage Reference
Configuration............................................................... 67
Voltage Reference Module ......................................... 67
W
Watchdog Timer (WDT) .................................................... 109
WWW Address.................................................................. 169
WWW, On-Line Support........................................................ 3
X
XORLW Instruction ........................................................... 128
XORWF Instruction ........................................................... 128
DS40044F-page 174
PIC16F627A/628A/648A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Device:
Temperature
Range:
I
E
= -40C to +85C
= -40C to+125C
Package:
P
SO
SS
ML
=
=
=
=
Examples:
a)
b)
PDIP
SOIC (Gull Wing, 7.50 mm body)
SSOP (5.30 mm
QFN (28 Lead)
DS40044F-page 175
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS40044F-page 176